CoCalc -- phyreg

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/contrib/dev/broadcom/brcm80211/brcmsmac/phy/phyreg_n.h
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// SPDX-License-Identifier: ISC
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/*
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 * Copyright (c) 2010 Broadcom Corporation
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 */
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#define NPHY_TBL_ID_GAIN1		0
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#define NPHY_TBL_ID_GAIN2		1
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#define NPHY_TBL_ID_GAINBITS1		2
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#define NPHY_TBL_ID_GAINBITS2		3
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#define NPHY_TBL_ID_GAINLIMIT		4
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#define NPHY_TBL_ID_WRSSIGainLimit	5
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#define NPHY_TBL_ID_RFSEQ		7
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#define NPHY_TBL_ID_AFECTRL		8
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#define NPHY_TBL_ID_ANTSWCTRLLUT	9
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#define NPHY_TBL_ID_IQLOCAL		15
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#define NPHY_TBL_ID_NOISEVAR		16
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#define NPHY_TBL_ID_SAMPLEPLAY		17
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#define NPHY_TBL_ID_CORE1TXPWRCTL	26
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#define NPHY_TBL_ID_CORE2TXPWRCTL	27
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#define NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL	30
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#define NPHY_TBL_ID_EPSILONTBL0   31
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#define NPHY_TBL_ID_SCALARTBL0    32
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#define NPHY_TBL_ID_EPSILONTBL1   33
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#define NPHY_TBL_ID_SCALARTBL1    34
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#define	NPHY_TO_BPHY_OFF	0xc00
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#define NPHY_BandControl_currentBand			0x0001
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#define RFCC_CHIP0_PU			0x0400
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#define RFCC_POR_FORCE			0x0040
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#define RFCC_OE_POR_FORCE		0x0080
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#define NPHY_RfctrlIntc_override_OFF			0
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#define NPHY_RfctrlIntc_override_TRSW			1
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#define NPHY_RfctrlIntc_override_PA				2
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#define NPHY_RfctrlIntc_override_EXT_LNA_PU		3
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#define NPHY_RfctrlIntc_override_EXT_LNA_GAIN	4
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#define RIFS_ENABLE			0x80
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#define BPHY_BAND_SEL_UP20		0x10
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#define NPHY_MLenable			0x02
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#define NPHY_RfseqMode_CoreActv_override 0x0001
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#define NPHY_RfseqMode_Trigger_override	0x0002
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#define NPHY_RfseqCoreActv_TxRxChain0	(0x11)
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#define NPHY_RfseqCoreActv_TxRxChain1	(0x22)
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#define NPHY_RfseqTrigger_rx2tx		0x0001
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#define NPHY_RfseqTrigger_tx2rx		0x0002
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#define NPHY_RfseqTrigger_updategainh	0x0004
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#define NPHY_RfseqTrigger_updategainl	0x0008
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#define NPHY_RfseqTrigger_updategainu	0x0010
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#define NPHY_RfseqTrigger_reset2rx	0x0020
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#define NPHY_RfseqStatus_rx2tx		0x0001
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#define NPHY_RfseqStatus_tx2rx		0x0002
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#define NPHY_RfseqStatus_updategainh	0x0004
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#define NPHY_RfseqStatus_updategainl	0x0008
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#define NPHY_RfseqStatus_updategainu	0x0010
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#define NPHY_RfseqStatus_reset2rx	0x0020
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#define NPHY_ClassifierCtrl_cck_en	0x1
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#define NPHY_ClassifierCtrl_ofdm_en	0x2
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#define NPHY_ClassifierCtrl_waited_en	0x4
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#define NPHY_IQFlip_ADC1		0x0001
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#define NPHY_IQFlip_ADC2		0x0010
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#define NPHY_sampleCmd_STOP		0x0002
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#define RX_GF_OR_MM			0x0004
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#define RX_GF_MM_AUTO			0x0100
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#define NPHY_iqloCalCmdGctl_IQLO_CAL_EN	0x8000
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#define NPHY_IqestCmd_iqstart		0x1
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#define NPHY_IqestCmd_iqMode		0x2
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#define NPHY_TxPwrCtrlCmd_pwrIndex_init		0x40
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#define NPHY_TxPwrCtrlCmd_pwrIndex_init_rev7	0x19
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#define PRIM_SEL_UP20		0x8000
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#define NPHY_RFSEQ_RX2TX		0x0
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#define NPHY_RFSEQ_TX2RX		0x1
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#define NPHY_RFSEQ_RESET2RX		0x2
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#define NPHY_RFSEQ_UPDATEGAINH		0x3
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#define NPHY_RFSEQ_UPDATEGAINL		0x4
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#define NPHY_RFSEQ_UPDATEGAINU		0x5
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#define NPHY_RFSEQ_CMD_NOP		0x0
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#define NPHY_RFSEQ_CMD_RXG_FBW		0x1
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#define NPHY_RFSEQ_CMD_TR_SWITCH	0x2
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#define NPHY_RFSEQ_CMD_EXT_PA		0x3
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#define NPHY_RFSEQ_CMD_RXPD_TXPD	0x4
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#define NPHY_RFSEQ_CMD_TX_GAIN		0x5
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#define NPHY_RFSEQ_CMD_RX_GAIN		0x6
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#define NPHY_RFSEQ_CMD_SET_HPF_BW	0x7
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#define NPHY_RFSEQ_CMD_CLR_HIQ_DIS	0x8
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#define NPHY_RFSEQ_CMD_END		0xf
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#define NPHY_REV3_RFSEQ_CMD_NOP		0x0
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#define NPHY_REV3_RFSEQ_CMD_RXG_FBW	0x1
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#define NPHY_REV3_RFSEQ_CMD_TR_SWITCH	0x2
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#define NPHY_REV3_RFSEQ_CMD_INT_PA_PU	0x3
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#define NPHY_REV3_RFSEQ_CMD_EXT_PA	0x4
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#define NPHY_REV3_RFSEQ_CMD_RXPD_TXPD	0x5
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#define NPHY_REV3_RFSEQ_CMD_TX_GAIN	0x6
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#define NPHY_REV3_RFSEQ_CMD_RX_GAIN	0x7
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#define NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS	0x8
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#define NPHY_REV3_RFSEQ_CMD_SET_HPF_H_HPC	0x9
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#define NPHY_REV3_RFSEQ_CMD_SET_LPF_H_HPC	0xa
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#define NPHY_REV3_RFSEQ_CMD_SET_HPF_M_HPC	0xb
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#define NPHY_REV3_RFSEQ_CMD_SET_LPF_M_HPC	0xc
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#define NPHY_REV3_RFSEQ_CMD_SET_HPF_L_HPC	0xd
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#define NPHY_REV3_RFSEQ_CMD_SET_LPF_L_HPC	0xe
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#define NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS	0xf
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#define NPHY_REV3_RFSEQ_CMD_END		0x1f
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#define NPHY_RSSI_SEL_W1		0x0
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#define NPHY_RSSI_SEL_W2		0x1
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#define NPHY_RSSI_SEL_NB		0x2
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#define NPHY_RSSI_SEL_IQ		0x3
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#define NPHY_RSSI_SEL_TSSI_2G		0x4
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#define NPHY_RSSI_SEL_TSSI_5G		0x5
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#define NPHY_RSSI_SEL_TBD		0x6
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#define NPHY_RAIL_I			0x0
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#define NPHY_RAIL_Q			0x1
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#define NPHY_FORCESIG_DECODEGATEDCLKS	0x8
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#define NPHY_REV7_RfctrlOverride_cmd_rxrf_pu 0x0
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#define NPHY_REV7_RfctrlOverride_cmd_rx_pu   0x1
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#define NPHY_REV7_RfctrlOverride_cmd_tx_pu   0x2
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#define NPHY_REV7_RfctrlOverride_cmd_rxgain  0x3
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#define NPHY_REV7_RfctrlOverride_cmd_txgain  0x4
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#define NPHY_REV7_RXGAINCODE_RFMXGAIN_MASK 0x000ff
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#define NPHY_REV7_RXGAINCODE_LPFGAIN_MASK  0x0ff00
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#define NPHY_REV7_RXGAINCODE_DVGAGAIN_MASK 0xf0000
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#define NPHY_REV7_TXGAINCODE_TGAIN_MASK     0x7fff
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#define NPHY_REV7_TXGAINCODE_LPFGAIN_MASK   0x8000
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#define NPHY_REV7_TXGAINCODE_BIQ0GAIN_SHIFT 14
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#define NPHY_REV7_RFCTRLOVERRIDE_ID0 0x0
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#define NPHY_REV7_RFCTRLOVERRIDE_ID1 0x1
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#define NPHY_REV7_RFCTRLOVERRIDE_ID2 0x2
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#define NPHY_IqestIqAccLo(core)  ((core == 0) ? 0x12c : 0x134)
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#define NPHY_IqestIqAccHi(core)  ((core == 0) ? 0x12d : 0x135)
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#define NPHY_IqestipwrAccLo(core)  ((core == 0) ? 0x12e : 0x136)
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#define NPHY_IqestipwrAccHi(core)  ((core == 0) ? 0x12f : 0x137)
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#define NPHY_IqestqpwrAccLo(core)  ((core == 0) ? 0x130 : 0x138)
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#define NPHY_IqestqpwrAccHi(core)  ((core == 0) ? 0x131 : 0x139)
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