Path: blob/main/sys/contrib/dev/mediatek/mt76/mt7603/mt7603.h
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/* SPDX-License-Identifier: ISC */12#ifndef __MT7603_H3#define __MT7603_H45#include <linux/interrupt.h>6#include <linux/ktime.h>7#include "../mt76.h"8#include "regs.h"910#define MT7603_MAX_INTERFACES 411#define MT7603_WTBL_SIZE 12812#define MT7603_WTBL_RESERVED (MT7603_WTBL_SIZE - 1)13#define MT7603_WTBL_STA (MT7603_WTBL_RESERVED - MT7603_MAX_INTERFACES)1415#define MT7603_RATE_RETRY 21617#define MT7603_MCU_RX_RING_SIZE 6418#define MT7603_RX_RING_SIZE 12819#define MT7603_TX_RING_SIZE 25620#define MT7603_PSD_RING_SIZE 1282122#define MT7603_FIRMWARE_E1 "mt7603_e1.bin"23#define MT7603_FIRMWARE_E2 "mt7603_e2.bin"24#define MT7628_FIRMWARE_E1 "mt7628_e1.bin"25#define MT7628_FIRMWARE_E2 "mt7628_e2.bin"2627#define MT7603_EEPROM_SIZE 10242829#define MT_AGG_SIZE_LIMIT(_n) (((_n) + 1) * 4)3031#define MT7603_PRE_TBTT_TIME 5000 /* ms */3233#define MT7603_WATCHDOG_TIME 100 /* ms */34#define MT7603_WATCHDOG_TIMEOUT 10 /* number of checks */3536#define MT7603_EDCCA_BLOCK_TH 103738#define MT7603_CFEND_RATE_DEFAULT 0x69 /* chip default (24M) */39#define MT7603_CFEND_RATE_11B 0x03 /* 11B LP, 11M */4041struct mt7603_vif;42struct mt7603_sta;4344enum {45MT7603_REV_E1 = 0x00,46MT7603_REV_E2 = 0x10,47MT7628_REV_E1 = 0x8a00,48};4950enum mt7603_bw {51MT_BW_20,52MT_BW_40,53MT_BW_80,54};5556struct mt7603_rate_set {57struct ieee80211_tx_rate probe_rate;58struct ieee80211_tx_rate rates[4];59};6061struct mt7603_sta {62struct mt76_wcid wcid; /* must be first */6364struct mt7603_vif *vif;6566u32 tx_airtime_ac[4];6768struct sk_buff_head psq;6970struct ieee80211_tx_rate rates[4];7172struct mt7603_rate_set rateset[2];73u32 rate_set_tsf;7475u8 rate_count;76u8 n_rates;7778u8 rate_probe;79u8 smps;8081u8 ps;82};8384struct mt7603_vif {85struct mt7603_sta sta; /* must be first */8687u8 idx;88};8990enum mt7603_reset_cause {91RESET_CAUSE_TX_HANG,92RESET_CAUSE_TX_BUSY,93RESET_CAUSE_RX_BUSY,94RESET_CAUSE_BEACON_STUCK,95RESET_CAUSE_RX_PSE_BUSY,96RESET_CAUSE_MCU_HANG,97RESET_CAUSE_RESET_FAILED,98__RESET_CAUSE_MAX99};100101struct mt7603_dev {102union { /* must be first */103struct mt76_dev mt76;104struct mt76_phy mphy;105};106107const struct mt76_bus_ops *bus_ops;108109u32 rxfilter;110111struct mt7603_sta global_sta;112113u32 agc0, agc3;114u32 false_cca_ofdm, false_cca_cck;115unsigned long last_cca_adj;116117u32 ampdu_ref;118u32 rx_ampdu_ts;119u8 rssi_offset[3];120121u8 slottime;122s16 coverage_class;123124s8 tx_power_limit;125126ktime_t ed_time;127128spinlock_t ps_lock;129130u8 mcu_running;131132u8 ed_monitor_enabled;133u8 ed_monitor;134s8 ed_trigger;135u8 ed_strict_mode;136u8 ed_strong_signal;137138bool dynamic_sensitivity;139s8 sensitivity;140u8 sensitivity_limit;141142u8 beacon_check;143u8 tx_hang_check;144u8 tx_dma_check;145u8 rx_dma_check;146u8 rx_pse_check;147u8 mcu_hang;148149enum mt7603_reset_cause cur_reset_cause;150151u16 tx_dma_idx[4];152u16 rx_dma_idx;153154u32 reset_test;155156unsigned int reset_cause[__RESET_CAUSE_MAX];157};158159extern const struct mt76_driver_ops mt7603_drv_ops;160extern const struct ieee80211_ops mt7603_ops;161extern struct pci_driver mt7603_pci_driver;162extern struct platform_driver mt76_wmac_driver;163164static inline bool is_mt7603(struct mt7603_dev *dev)165{166return mt76xx_chip(dev) == 0x7603;167}168169static inline bool is_mt7628(struct mt7603_dev *dev)170{171return mt76xx_chip(dev) == 0x7628;172}173174/* need offset to prevent conflict with ampdu_ack_len */175#define MT_RATE_DRIVER_DATA_OFFSET 4176177u32 mt7603_reg_map(struct mt7603_dev *dev, u32 addr);178179irqreturn_t mt7603_irq_handler(int irq, void *dev_instance);180181int mt7603_register_device(struct mt7603_dev *dev);182void mt7603_unregister_device(struct mt7603_dev *dev);183int mt7603_eeprom_init(struct mt7603_dev *dev);184int mt7603_dma_init(struct mt7603_dev *dev);185void mt7603_dma_cleanup(struct mt7603_dev *dev);186int mt7603_mcu_init(struct mt7603_dev *dev);187void mt7603_init_debugfs(struct mt7603_dev *dev);188189static inline void mt7603_irq_enable(struct mt7603_dev *dev, u32 mask)190{191mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, 0, mask);192}193194static inline void mt7603_irq_disable(struct mt7603_dev *dev, u32 mask)195{196mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);197}198199void mt7603_mac_reset_counters(struct mt7603_dev *dev);200void mt7603_mac_dma_start(struct mt7603_dev *dev);201void mt7603_mac_start(struct mt7603_dev *dev);202void mt7603_mac_stop(struct mt7603_dev *dev);203void mt7603_mac_work(struct work_struct *work);204void mt7603_mac_set_timing(struct mt7603_dev *dev);205void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval);206int mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb);207void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data);208void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid);209void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid,210int ba_size);211void mt7603_mac_sta_poll(struct mt7603_dev *dev);212213void mt7603_pse_client_reset(struct mt7603_dev *dev);214215int mt7603_set_channel(struct mt76_phy *mphy);216int mt7603_mcu_set_channel(struct mt7603_dev *dev);217int mt7603_mcu_set_eeprom(struct mt7603_dev *dev);218void mt7603_mcu_exit(struct mt7603_dev *dev);219220void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif,221const u8 *mac_addr);222void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx);223void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta);224void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta,225struct ieee80211_tx_rate *probe_rate,226struct ieee80211_tx_rate *rates);227int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid,228struct ieee80211_key_conf *key);229void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta,230bool enabled);231void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta,232bool enabled);233void mt7603_filter_tx(struct mt7603_dev *dev, int mac_idx, int idx, bool abort);234235int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,236enum mt76_txq_id qid, struct mt76_wcid *wcid,237struct ieee80211_sta *sta,238struct mt76_tx_info *tx_info);239240void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);241242void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,243struct sk_buff *skb, u32 *info);244void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);245void mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);246int mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,247struct ieee80211_sta *sta);248int mt7603_sta_event(struct mt76_dev *mdev, struct ieee80211_vif *vif,249struct ieee80211_sta *sta, enum mt76_sta_event ev);250void mt7603_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,251struct ieee80211_sta *sta);252253void mt7603_pre_tbtt_tasklet(struct tasklet_struct *t);254255void mt7603_update_channel(struct mt76_phy *mphy);256257void mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val);258void mt7603_cca_stats_reset(struct mt7603_dev *dev);259260void mt7603_init_edcca(struct mt7603_dev *dev);261#endif262263264