Path: blob/main/sys/contrib/dev/mediatek/mt76/mt76_connac.h
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/* SPDX-License-Identifier: ISC */1/* Copyright (C) 2020 MediaTek Inc. */23#ifndef __MT76_CONNAC_H4#define __MT76_CONNAC_H56#include "mt76.h"78enum rx_pkt_type {9PKT_TYPE_TXS,10PKT_TYPE_TXRXV,11PKT_TYPE_NORMAL,12PKT_TYPE_RX_DUP_RFB,13PKT_TYPE_RX_TMR,14PKT_TYPE_RETRIEVE,15PKT_TYPE_TXRX_NOTIFY,16PKT_TYPE_RX_EVENT,17PKT_TYPE_NORMAL_MCU,18PKT_TYPE_RX_FW_MONITOR = 0x0c,19PKT_TYPE_TXRX_NOTIFY_V0 = 0x18,20};2122#define MT76_CONNAC_SCAN_IE_LEN 60023#define MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL 1024#define MT76_CONNAC_MAX_TIME_SCHED_SCAN_INTERVAL U16_MAX25#define MT76_CONNAC_MAX_SCHED_SCAN_SSID 1026#define MT76_CONNAC_MAX_SCAN_MATCH 162728#define MT76_CONNAC_MAX_WMM_SETS 42930#define MT76_CONNAC_COREDUMP_TIMEOUT (HZ / 20)31#define MT76_CONNAC_COREDUMP_SZ (1300 * 1024)3233#define MT_TXD_SIZE (8 * 4)3435#define MT_USB_TXD_SIZE (MT_TXD_SIZE + 8 * 4)36#define MT_USB_HDR_SIZE 437#define MT_USB_TAIL_SIZE 43839#define MT_SDIO_TXD_SIZE (MT_TXD_SIZE + 8 * 4)40#define MT_SDIO_TAIL_SIZE 841#define MT_SDIO_HDR_SIZE 44243#define MT_MSDU_ID_VALID BIT(15)4445#define MT_TXD_LEN_LAST BIT(15)46#define MT_TXD_LEN_MASK GENMASK(11, 0)47#define MT_TXD_LEN_MSDU_LAST BIT(14)48#define MT_TXD_LEN_AMSDU_LAST BIT(15)4950enum {51CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20,52CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40,53CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80,54CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160,55CMD_CBW_10MHZ,56CMD_CBW_5MHZ,57CMD_CBW_8080MHZ,58CMD_CBW_320MHZ,5960CMD_HE_MCS_BW80 = 0,61CMD_HE_MCS_BW160,62CMD_HE_MCS_BW8080,63CMD_HE_MCS_BW_NUM64};6566enum {67HW_BSSID_0 = 0x0,68HW_BSSID_1,69HW_BSSID_2,70HW_BSSID_3,71HW_BSSID_MAX = HW_BSSID_3,72EXT_BSSID_START = 0x10,73EXT_BSSID_1,74EXT_BSSID_15 = 0x1f,75EXT_BSSID_MAX = EXT_BSSID_15,76REPEATER_BSSID_START = 0x20,77REPEATER_BSSID_MAX = 0x3f,78};7980struct mt76_connac_reg_map {81u32 phys;82u32 maps;83u32 size;84};8586struct mt76_connac_pm {87bool enable:1;88bool enable_user:1;89bool ds_enable:1;90bool ds_enable_user:1;91bool suspended:1;9293spinlock_t txq_lock;94struct {95struct mt76_wcid *wcid;96struct sk_buff *skb;97} tx_q[IEEE80211_NUM_ACS];9899struct work_struct wake_work;100wait_queue_head_t wait;101102struct {103spinlock_t lock;104u32 count;105} wake;106struct mutex mutex;107108struct delayed_work ps_work;109unsigned long last_activity;110unsigned long idle_timeout;111112struct {113unsigned long last_wake_event;114unsigned long awake_time;115unsigned long last_doze_event;116unsigned long doze_time;117unsigned int lp_wake;118} stats;119};120121struct mt76_connac_coredump {122struct sk_buff_head msg_list;123struct delayed_work work;124unsigned long last_activity;125};126127struct mt76_connac_sta_key_conf {128s8 keyidx;129u8 key[16];130};131132#define MT_TXP_MAX_BUF_NUM 6133134struct mt76_connac_fw_txp {135__le16 flags;136__le16 token;137u8 bss_idx;138__le16 rept_wds_wcid;139u8 nbuf;140__le32 buf[MT_TXP_MAX_BUF_NUM];141__le16 len[MT_TXP_MAX_BUF_NUM];142} __packed __aligned(4);143144#define MT_HW_TXP_MAX_MSDU_NUM 4145#define MT_HW_TXP_MAX_BUF_NUM 4146147struct mt76_connac_txp_ptr {148__le32 buf0;149__le16 len0;150__le16 len1;151__le32 buf1;152} __packed __aligned(4);153154struct mt76_connac_hw_txp {155__le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM];156struct mt76_connac_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2];157} __packed __aligned(4);158159struct mt76_connac_txp_common {160union {161struct mt76_connac_fw_txp fw;162struct mt76_connac_hw_txp hw;163};164};165166struct mt76_connac_tx_free {167__le16 rx_byte_cnt;168__le16 ctrl;169__le32 txd;170} __packed __aligned(4);171172extern const struct wiphy_wowlan_support mt76_connac_wowlan_support;173174static inline bool is_mt7925(struct mt76_dev *dev)175{176return mt76_chip(dev) == 0x7925;177}178179static inline bool is_mt7920(struct mt76_dev *dev)180{181return mt76_chip(dev) == 0x7920;182}183184static inline bool is_mt7922(struct mt76_dev *dev)185{186return mt76_chip(dev) == 0x7922;187}188189static inline bool is_mt7921(struct mt76_dev *dev)190{191return mt76_chip(dev) == 0x7961 || is_mt7922(dev) || is_mt7920(dev);192}193194static inline bool is_mt7663(struct mt76_dev *dev)195{196return mt76_chip(dev) == 0x7663;197}198199static inline bool is_mt7915(struct mt76_dev *dev)200{201return mt76_chip(dev) == 0x7915;202}203204static inline bool is_mt7916(struct mt76_dev *dev)205{206return mt76_chip(dev) == 0x7906;207}208209static inline bool is_mt7981(struct mt76_dev *dev)210{211return mt76_chip(dev) == 0x7981;212}213214static inline bool is_mt7986(struct mt76_dev *dev)215{216return mt76_chip(dev) == 0x7986;217}218219static inline bool is_mt798x(struct mt76_dev *dev)220{221return is_mt7981(dev) || is_mt7986(dev);222}223224static inline bool is_mt7996(struct mt76_dev *dev)225{226return mt76_chip(dev) == 0x7990;227}228229static inline bool is_mt7992(struct mt76_dev *dev)230{231return mt76_chip(dev) == 0x7992;232}233234static inline bool is_mt7990(struct mt76_dev *dev)235{236return mt76_chip(dev) == 0x7993;237}238239static inline bool is_mt799x(struct mt76_dev *dev)240{241return is_mt7996(dev) || is_mt7992(dev) || is_mt7990(dev);242}243244static inline bool is_mt7622(struct mt76_dev *dev)245{246if (!IS_ENABLED(CONFIG_MT7622_WMAC))247return false;248249return mt76_chip(dev) == 0x7622;250}251252static inline bool is_mt7615(struct mt76_dev *dev)253{254return mt76_chip(dev) == 0x7615 || mt76_chip(dev) == 0x7611;255}256257static inline bool is_mt7611(struct mt76_dev *dev)258{259return mt76_chip(dev) == 0x7611;260}261262static inline bool is_connac_v1(struct mt76_dev *dev)263{264return is_mt7615(dev) || is_mt7663(dev) || is_mt7622(dev);265}266267static inline bool is_mt76_fw_txp(struct mt76_dev *dev)268{269switch (mt76_chip(dev)) {270case 0x7961:271case 0x7920:272case 0x7922:273case 0x7925:274case 0x7663:275case 0x7622:276return false;277default:278return true;279}280}281282static inline u8 mt76_connac_chan_bw(struct cfg80211_chan_def *chandef)283{284static const u8 width_to_bw[] = {285[NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ,286[NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ,287[NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ,288[NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ,289[NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ,290[NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ,291[NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ,292[NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ,293[NL80211_CHAN_WIDTH_320] = CMD_CBW_320MHZ,294};295296if (chandef->width >= ARRAY_SIZE(width_to_bw))297return 0;298299return width_to_bw[chandef->width];300}301302static inline u8 mt76_connac_lmac_mapping(u8 ac)303{304/* LMAC uses the reverse order of mac80211 AC indexes */305return 3 - ac;306}307308static inline void *309mt76_connac_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)310{311u8 *txwi;312313if (!t)314return NULL;315316txwi = mt76_get_txwi_ptr(dev, t);317318return (void *)(txwi + MT_TXD_SIZE);319}320321static inline u8 mt76_connac_spe_idx(u8 antenna_mask)322{323static const u8 ant_to_spe[] = {0, 0, 1, 0, 3, 2, 4, 0,3249, 8, 6, 10, 16, 12, 18, 0};325326if (antenna_mask >= sizeof(ant_to_spe))327return 0;328329return ant_to_spe[antenna_mask];330}331332static inline void mt76_connac_irq_enable(struct mt76_dev *dev, u32 mask)333{334mt76_set_irq_mask(dev, 0, 0, mask);335tasklet_schedule(&dev->irq_tasklet);336}337338int mt76_connac_pm_wake(struct mt76_phy *phy, struct mt76_connac_pm *pm);339void mt76_connac_power_save_sched(struct mt76_phy *phy,340struct mt76_connac_pm *pm);341void mt76_connac_free_pending_tx_skbs(struct mt76_connac_pm *pm,342struct mt76_wcid *wcid);343344static inline void mt76_connac_tx_cleanup(struct mt76_dev *dev)345{346dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WM], false);347dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WA], false);348}349350static inline bool351mt76_connac_pm_ref(struct mt76_phy *phy, struct mt76_connac_pm *pm)352{353bool ret = false;354355spin_lock_bh(&pm->wake.lock);356if (test_bit(MT76_STATE_PM, &phy->state))357goto out;358359pm->wake.count++;360ret = true;361out:362spin_unlock_bh(&pm->wake.lock);363364return ret;365}366367static inline void368mt76_connac_pm_unref(struct mt76_phy *phy, struct mt76_connac_pm *pm)369{370spin_lock_bh(&pm->wake.lock);371372pm->last_activity = jiffies;373if (--pm->wake.count == 0 &&374test_bit(MT76_STATE_MCU_RUNNING, &phy->state))375mt76_connac_power_save_sched(phy, pm);376377spin_unlock_bh(&pm->wake.lock);378}379380static inline bool381mt76_connac_skip_fw_pmctrl(struct mt76_phy *phy, struct mt76_connac_pm *pm)382{383struct mt76_dev *dev = phy->dev;384bool ret;385386if (dev->token_count)387return true;388389spin_lock_bh(&pm->wake.lock);390ret = pm->wake.count || test_and_set_bit(MT76_STATE_PM, &phy->state);391spin_unlock_bh(&pm->wake.lock);392393return ret;394}395396static inline void397mt76_connac_mutex_acquire(struct mt76_dev *dev, struct mt76_connac_pm *pm)398__acquires(&dev->mutex)399{400mutex_lock(&dev->mutex);401mt76_connac_pm_wake(&dev->phy, pm);402}403404static inline void405mt76_connac_mutex_release(struct mt76_dev *dev, struct mt76_connac_pm *pm)406__releases(&dev->mutex)407{408mt76_connac_power_save_sched(&dev->phy, pm);409mutex_unlock(&dev->mutex);410}411412void mt76_connac_gen_ppe_thresh(u8 *he_ppet, int nss, enum nl80211_band band);413int mt76_connac_init_tx_queues(struct mt76_phy *phy, int idx, int n_desc,414int ring_base, void *wed, u32 flags);415416void mt76_connac_write_hw_txp(struct mt76_dev *dev,417struct mt76_tx_info *tx_info,418void *txp_ptr, u32 id);419void mt76_connac_txp_skb_unmap(struct mt76_dev *dev,420struct mt76_txwi_cache *txwi);421void mt76_connac_tx_complete_skb(struct mt76_dev *mdev,422struct mt76_queue_entry *e);423void mt76_connac_pm_queue_skb(struct ieee80211_hw *hw,424struct mt76_connac_pm *pm,425struct mt76_wcid *wcid,426struct sk_buff *skb);427void mt76_connac_pm_dequeue_skbs(struct mt76_phy *phy,428struct mt76_connac_pm *pm);429void mt76_connac2_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,430struct sk_buff *skb, struct mt76_wcid *wcid,431struct ieee80211_key_conf *key, int pid,432enum mt76_txq_id qid, u32 changed);433u16 mt76_connac2_mac_tx_rate_val(struct mt76_phy *mphy,434struct ieee80211_bss_conf *conf,435bool beacon, bool mcast);436bool mt76_connac2_mac_fill_txs(struct mt76_dev *dev, struct mt76_wcid *wcid,437__le32 *txs_data);438bool mt76_connac2_mac_add_txs_skb(struct mt76_dev *dev, struct mt76_wcid *wcid,439int pid, __le32 *txs_data);440void mt76_connac2_mac_decode_he_radiotap(struct mt76_dev *dev,441struct sk_buff *skb,442__le32 *rxv, u32 mode);443int mt76_connac2_reverse_frag0_hdr_trans(struct ieee80211_vif *vif,444struct sk_buff *skb, u16 hdr_offset);445int mt76_connac2_mac_fill_rx_rate(struct mt76_dev *dev,446struct mt76_rx_status *status,447struct ieee80211_supported_band *sband,448__le32 *rxv, u8 *mode);449void mt76_connac2_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi);450void mt76_connac2_txwi_free(struct mt76_dev *dev, struct mt76_txwi_cache *t,451struct ieee80211_sta *sta,452struct list_head *free_list);453void mt76_connac2_tx_token_put(struct mt76_dev *dev);454455/* connac3 */456void mt76_connac3_mac_decode_he_radiotap(struct sk_buff *skb, __le32 *rxv,457u8 mode);458void mt76_connac3_mac_decode_eht_radiotap(struct sk_buff *skb, __le32 *rxv,459u8 mode);460#endif /* __MT76_CONNAC_H */461462463