Path: blob/main/sys/contrib/dev/mediatek/mt76/mt76x02_dma.h
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/* SPDX-License-Identifier: ISC */1/*2* Copyright (C) 2018 Lorenzo Bianconi <[email protected]>3*/45#ifndef __MT76x02_DMA_H6#define __MT76x02_DMA_H78#include "mt76x02.h"9#include "dma.h"1011#define MT_TXD_INFO_LEN GENMASK(15, 0)12#define MT_TXD_INFO_NEXT_VLD BIT(16)13#define MT_TXD_INFO_TX_BURST BIT(17)14#define MT_TXD_INFO_80211 BIT(19)15#define MT_TXD_INFO_TSO BIT(20)16#define MT_TXD_INFO_CSO BIT(21)17#define MT_TXD_INFO_WIV BIT(24)18#define MT_TXD_INFO_QSEL GENMASK(26, 25)19#define MT_TXD_INFO_DPORT GENMASK(29, 27)20#define MT_TXD_INFO_TYPE GENMASK(31, 30)2122#define MT_RX_FCE_INFO_LEN GENMASK(13, 0)23#define MT_RX_FCE_INFO_SELF_GEN BIT(15)24#define MT_RX_FCE_INFO_CMD_SEQ GENMASK(19, 16)25#define MT_RX_FCE_INFO_EVT_TYPE GENMASK(23, 20)26#define MT_RX_FCE_INFO_PCIE_INTR BIT(24)27#define MT_RX_FCE_INFO_QSEL GENMASK(26, 25)28#define MT_RX_FCE_INFO_D_PORT GENMASK(29, 27)29#define MT_RX_FCE_INFO_TYPE GENMASK(31, 30)3031/* MCU request message header */32#define MT_MCU_MSG_LEN GENMASK(15, 0)33#define MT_MCU_MSG_CMD_SEQ GENMASK(19, 16)34#define MT_MCU_MSG_CMD_TYPE GENMASK(26, 20)35#define MT_MCU_MSG_PORT GENMASK(29, 27)36#define MT_MCU_MSG_TYPE GENMASK(31, 30)37#define MT_MCU_MSG_TYPE_CMD BIT(30)3839#define MT_RX_HEADROOM 3240#define MT76X02_RX_RING_SIZE 2564142enum dma_msg_port {43WLAN_PORT,44CPU_RX_PORT,45CPU_TX_PORT,46HOST_PORT,47VIRTUAL_CPU_RX_PORT,48VIRTUAL_CPU_TX_PORT,49DISCARD,50};5152static inline bool53mt76x02_wait_for_wpdma(struct mt76_dev *dev, int timeout)54{55return __mt76_poll(dev, MT_WPDMA_GLO_CFG,56MT_WPDMA_GLO_CFG_TX_DMA_BUSY |57MT_WPDMA_GLO_CFG_RX_DMA_BUSY,580, timeout);59}6061int mt76x02_dma_init(struct mt76x02_dev *dev);62void mt76x02_dma_disable(struct mt76x02_dev *dev);6364#endif /* __MT76x02_DMA_H */656667