Path: blob/main/sys/contrib/dev/mediatek/mt76/mt76x02_phy.h
48378 views
/* SPDX-License-Identifier: ISC */1/*2* Copyright (C) 2018 Lorenzo Bianconi <[email protected]>3*/45#ifndef __MT76x02_PHY_H6#define __MT76x02_PHY_H78#include "mt76x02_regs.h"910static inline int11mt76x02_get_rssi_gain_thresh(struct mt76x02_dev *dev)12{13switch (dev->mphy.chandef.width) {14case NL80211_CHAN_WIDTH_80:15return -62;16case NL80211_CHAN_WIDTH_40:17return -65;18default:19return -68;20}21}2223static inline int24mt76x02_get_low_rssi_gain_thresh(struct mt76x02_dev *dev)25{26switch (dev->mphy.chandef.width) {27case NL80211_CHAN_WIDTH_80:28return -76;29case NL80211_CHAN_WIDTH_40:30return -79;31default:32return -82;33}34}3536void mt76x02_add_rate_power_offset(struct mt76x02_rate_power *r, int offset);37void mt76x02_phy_set_txpower(struct mt76x02_dev *dev, int txp_0, int txp_2);38void mt76x02_limit_rate_power(struct mt76x02_rate_power *r, int limit);39int mt76x02_get_max_rate_power(struct mt76x02_rate_power *r);40void mt76x02_phy_set_rxpath(struct mt76x02_dev *dev);41void mt76x02_phy_set_txdac(struct mt76x02_dev *dev);42void mt76x02_phy_set_bw(struct mt76x02_dev *dev, int width, u8 ctrl);43void mt76x02_phy_set_band(struct mt76x02_dev *dev, int band,44bool primary_upper);45bool mt76x02_phy_adjust_vga_gain(struct mt76x02_dev *dev);46void mt76x02_init_agc_gain(struct mt76x02_dev *dev);4748#endif /* __MT76x02_PHY_H */495051