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freebsd
GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/contrib/dev/mediatek/mt76/mt7915/init.c
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// SPDX-License-Identifier: BSD-3-Clause-Clear
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/* Copyright (C) 2020 MediaTek Inc. */
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#include <linux/etherdevice.h>
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#include <linux/hwmon.h>
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#include <linux/hwmon-sysfs.h>
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#include <linux/of.h>
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#include <linux/thermal.h>
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#if defined(__FreeBSD__)
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#include <linux/delay.h>
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#endif
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#include "mt7915.h"
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#include "mac.h"
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#include "mcu.h"
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#include "coredump.h"
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#include "eeprom.h"
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static const struct ieee80211_iface_limit if_limits[] = {
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{
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.max = 1,
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.types = BIT(NL80211_IFTYPE_ADHOC)
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}, {
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.max = 16,
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.types = BIT(NL80211_IFTYPE_AP)
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#ifdef CONFIG_MAC80211_MESH
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| BIT(NL80211_IFTYPE_MESH_POINT)
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#endif
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}, {
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.max = MT7915_MAX_INTERFACES,
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.types = BIT(NL80211_IFTYPE_STATION)
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}
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};
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static const struct ieee80211_iface_combination if_comb[] = {
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{
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.limits = if_limits,
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.n_limits = ARRAY_SIZE(if_limits),
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.max_interfaces = MT7915_MAX_INTERFACES,
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.num_different_channels = 1,
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.beacon_int_infra_match = true,
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.radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
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BIT(NL80211_CHAN_WIDTH_20) |
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BIT(NL80211_CHAN_WIDTH_40) |
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BIT(NL80211_CHAN_WIDTH_80) |
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BIT(NL80211_CHAN_WIDTH_160),
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}
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};
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#if defined(__linux__)
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static ssize_t mt7915_thermal_temp_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct mt7915_phy *phy = dev_get_drvdata(dev);
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int i = to_sensor_dev_attr(attr)->index;
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int temperature;
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58
switch (i) {
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case 0:
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mutex_lock(&phy->dev->mt76.mutex);
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temperature = mt7915_mcu_get_temperature(phy);
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mutex_unlock(&phy->dev->mt76.mutex);
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if (temperature < 0)
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return temperature;
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/* display in millidegree celcius */
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return sprintf(buf, "%u\n", temperature * 1000);
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case 1:
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case 2:
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return sprintf(buf, "%u\n",
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phy->throttle_temp[i - 1] * 1000);
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case 3:
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return sprintf(buf, "%hhu\n", phy->throttle_state);
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default:
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return -EINVAL;
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}
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}
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static ssize_t mt7915_thermal_temp_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct mt7915_phy *phy = dev_get_drvdata(dev);
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int ret, i = to_sensor_dev_attr(attr)->index;
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long val;
85
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ret = kstrtol(buf, 10, &val);
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if (ret < 0)
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return ret;
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mutex_lock(&phy->dev->mt76.mutex);
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val = DIV_ROUND_CLOSEST(clamp_val(val, 60 * 1000, 130 * 1000), 1000);
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if ((i - 1 == MT7915_CRIT_TEMP_IDX &&
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val > phy->throttle_temp[MT7915_MAX_TEMP_IDX]) ||
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(i - 1 == MT7915_MAX_TEMP_IDX &&
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val < phy->throttle_temp[MT7915_CRIT_TEMP_IDX])) {
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dev_err(phy->dev->mt76.dev,
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"temp1_max shall be greater than temp1_crit.");
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mutex_unlock(&phy->dev->mt76.mutex);
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return -EINVAL;
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}
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phy->throttle_temp[i - 1] = val;
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ret = mt7915_mcu_set_thermal_protect(phy);
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mutex_unlock(&phy->dev->mt76.mutex);
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if (ret)
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return ret;
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109
return count;
110
}
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static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0);
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static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1);
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static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2);
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static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3);
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static struct attribute *mt7915_hwmon_attrs[] = {
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&sensor_dev_attr_temp1_input.dev_attr.attr,
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&sensor_dev_attr_temp1_crit.dev_attr.attr,
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&sensor_dev_attr_temp1_max.dev_attr.attr,
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&sensor_dev_attr_throttle1.dev_attr.attr,
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NULL,
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};
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ATTRIBUTE_GROUPS(mt7915_hwmon);
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static int
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mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev,
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unsigned long *state)
129
{
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*state = MT7915_CDEV_THROTTLE_MAX;
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return 0;
133
}
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static int
136
mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev,
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unsigned long *state)
138
{
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struct mt7915_phy *phy = cdev->devdata;
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*state = phy->cdev_state;
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return 0;
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}
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static int
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mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev,
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unsigned long state)
149
{
150
struct mt7915_phy *phy = cdev->devdata;
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u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state;
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int ret;
153
154
if (state > MT7915_CDEV_THROTTLE_MAX) {
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dev_err(phy->dev->mt76.dev,
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"please specify a valid throttling state\n");
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return -EINVAL;
158
}
159
160
if (state == phy->cdev_state)
161
return 0;
162
163
/*
164
* cooling_device convention: 0 = no cooling, more = more cooling
165
* mcu convention: 1 = max cooling, more = less cooling
166
*/
167
mutex_lock(&phy->dev->mt76.mutex);
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ret = mt7915_mcu_set_thermal_throttling(phy, throttling);
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mutex_unlock(&phy->dev->mt76.mutex);
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if (ret)
171
return ret;
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phy->cdev_state = state;
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175
return 0;
176
}
177
178
static const struct thermal_cooling_device_ops mt7915_thermal_ops = {
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.get_max_state = mt7915_thermal_get_max_throttle_state,
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.get_cur_state = mt7915_thermal_get_cur_throttle_state,
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.set_cur_state = mt7915_thermal_set_cur_throttle_state,
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};
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static void mt7915_unregister_thermal(struct mt7915_phy *phy)
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{
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struct wiphy *wiphy = phy->mt76->hw->wiphy;
187
188
if (!phy->cdev)
189
return;
190
191
sysfs_remove_link(&wiphy->dev.kobj, "cooling_device");
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thermal_cooling_device_unregister(phy->cdev);
193
}
194
#endif
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196
static int mt7915_thermal_init(struct mt7915_phy *phy)
197
{
198
#if defined(__linux__)
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struct wiphy *wiphy = phy->mt76->hw->wiphy;
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struct thermal_cooling_device *cdev;
201
struct device *hwmon;
202
const char *name;
203
204
name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s",
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wiphy_name(wiphy));
206
if (!name)
207
return -ENOMEM;
208
209
cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops);
210
if (!IS_ERR(cdev)) {
211
if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj,
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"cooling_device") < 0)
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thermal_cooling_device_unregister(cdev);
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else
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phy->cdev = cdev;
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}
217
218
/* initialize critical/maximum high temperature */
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phy->throttle_temp[MT7915_CRIT_TEMP_IDX] = MT7915_CRIT_TEMP;
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phy->throttle_temp[MT7915_MAX_TEMP_IDX] = MT7915_MAX_TEMP;
221
222
if (!IS_REACHABLE(CONFIG_HWMON))
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return 0;
224
225
hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy,
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mt7915_hwmon_groups);
227
return PTR_ERR_OR_ZERO(hwmon);
228
#elif defined(__FreeBSD__)
229
return 0;
230
#endif
231
}
232
233
#if defined(CONFIG_MT76_LEDS)
234
static void mt7915_led_set_config(struct led_classdev *led_cdev,
235
u8 delay_on, u8 delay_off)
236
{
237
struct mt7915_dev *dev;
238
struct mt76_phy *mphy;
239
u32 val;
240
241
mphy = container_of(led_cdev, struct mt76_phy, leds.cdev);
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dev = container_of(mphy->dev, struct mt7915_dev, mt76);
243
244
/* set PWM mode */
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val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) |
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FIELD_PREP(MT_LED_STATUS_OFF, delay_off) |
247
FIELD_PREP(MT_LED_STATUS_ON, delay_on);
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mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val);
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mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val);
250
251
/* enable LED */
252
mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1);
253
254
/* control LED */
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val = MT_LED_CTRL_KICK;
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if (dev->mphy.leds.al)
257
val |= MT_LED_CTRL_POLARITY;
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if (mphy->band_idx)
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val |= MT_LED_CTRL_BAND;
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261
mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val);
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mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK);
263
}
264
#endif
265
266
static int mt7915_led_set_blink(struct led_classdev *led_cdev,
267
unsigned long *delay_on,
268
unsigned long *delay_off)
269
{
270
#if defined(CONFIG_MT76_LEDS)
271
u16 delta_on = 0, delta_off = 0;
272
273
#define HW_TICK 10
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#define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK)
275
276
if (*delay_on)
277
delta_on = TO_HW_TICK(*delay_on);
278
if (*delay_off)
279
delta_off = TO_HW_TICK(*delay_off);
280
281
mt7915_led_set_config(led_cdev, delta_on, delta_off);
282
#endif
283
284
return 0;
285
}
286
287
static void mt7915_led_set_brightness(struct led_classdev *led_cdev,
288
enum led_brightness brightness)
289
{
290
#if defined(CONFIG_MT76_LEDS)
291
if (!brightness)
292
mt7915_led_set_config(led_cdev, 0, 0xff);
293
else
294
mt7915_led_set_config(led_cdev, 0xff, 0);
295
#endif
296
}
297
298
static void __mt7915_init_txpower(struct mt7915_phy *phy,
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struct ieee80211_supported_band *sband)
300
{
301
struct mt7915_dev *dev = phy->dev;
302
int i, n_chains = hweight16(phy->mt76->chainmask);
303
int path_delta = mt76_tx_power_path_delta(n_chains);
304
int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band);
305
struct mt76_power_limits limits;
306
307
phy->sku_limit_en = true;
308
phy->sku_path_en = true;
309
for (i = 0; i < sband->n_channels; i++) {
310
struct ieee80211_channel *chan = &sband->channels[i];
311
u32 target_power = 0;
312
int j;
313
314
for (j = 0; j < n_chains; j++) {
315
u32 val;
316
317
val = mt7915_eeprom_get_target_power(dev, chan, j);
318
target_power = max(target_power, val);
319
}
320
321
target_power += pwr_delta;
322
target_power = mt76_get_rate_power_limits(phy->mt76, chan,
323
&limits,
324
target_power);
325
326
/* MT7915N can not enable Backoff table without setting value in dts */
327
if (!limits.path.ofdm[0])
328
phy->sku_path_en = false;
329
330
target_power += path_delta;
331
target_power = DIV_ROUND_UP(target_power, 2);
332
chan->max_power = min_t(int, chan->max_reg_power,
333
target_power);
334
chan->orig_mpwr = target_power;
335
}
336
}
337
338
void mt7915_init_txpower(struct mt7915_phy *phy)
339
{
340
if (!phy)
341
return;
342
343
if (phy->mt76->cap.has_2ghz)
344
__mt7915_init_txpower(phy, &phy->mt76->sband_2g.sband);
345
if (phy->mt76->cap.has_5ghz)
346
__mt7915_init_txpower(phy, &phy->mt76->sband_5g.sband);
347
if (phy->mt76->cap.has_6ghz)
348
__mt7915_init_txpower(phy, &phy->mt76->sband_6g.sband);
349
}
350
351
static void
352
mt7915_regd_notifier(struct wiphy *wiphy,
353
struct regulatory_request *request)
354
{
355
struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
356
struct mt7915_dev *dev = mt7915_hw_dev(hw);
357
struct mt76_phy *mphy = hw->priv;
358
struct mt7915_phy *phy = mphy->priv;
359
360
memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2));
361
dev->mt76.region = request->dfs_region;
362
363
if (dev->mt76.region == NL80211_DFS_UNSET)
364
mt7915_mcu_rdd_background_enable(phy, NULL);
365
366
mt7915_init_txpower(phy);
367
368
mphy->dfs_state = MT_DFS_STATE_UNKNOWN;
369
mt7915_dfs_init_radar_detector(phy);
370
}
371
372
static void
373
mt7915_init_wiphy(struct mt7915_phy *phy)
374
{
375
struct mt76_phy *mphy = phy->mt76;
376
struct ieee80211_hw *hw = mphy->hw;
377
struct mt76_dev *mdev = &phy->dev->mt76;
378
struct wiphy *wiphy = hw->wiphy;
379
struct mt7915_dev *dev = phy->dev;
380
381
hw->queues = 4;
382
hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE;
383
hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE;
384
hw->netdev_features = NETIF_F_RXCSUM;
385
386
if (mtk_wed_device_active(&mdev->mmio.wed))
387
hw->netdev_features |= NETIF_F_HW_TC;
388
389
hw->radiotap_timestamp.units_pos =
390
IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US;
391
392
phy->slottime = 9;
393
394
hw->sta_data_size = sizeof(struct mt7915_sta);
395
hw->vif_data_size = sizeof(struct mt7915_vif);
396
397
wiphy->iface_combinations = if_comb;
398
wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
399
wiphy->reg_notifier = mt7915_regd_notifier;
400
wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
401
wiphy->mbssid_max_interfaces = 16;
402
403
wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR);
404
wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
405
wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY);
406
wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT);
407
wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT);
408
wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE);
409
wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP);
410
wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY);
411
wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT);
412
wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
413
414
if (!is_mt7915(&dev->mt76))
415
wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR);
416
417
if (mt7915_eeprom_has_background_radar(phy->dev) &&
418
#if defined(CONFIG_OF)
419
(!mdev->dev->of_node ||
420
!of_property_read_bool(mdev->dev->of_node,
421
"mediatek,disable-radar-background")))
422
#else
423
1)
424
#endif
425
wiphy_ext_feature_set(wiphy,
426
NL80211_EXT_FEATURE_RADAR_BACKGROUND);
427
428
ieee80211_hw_set(hw, HAS_RATE_CONTROL);
429
ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD);
430
ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD);
431
ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
432
ieee80211_hw_set(hw, WANT_MONITOR_VIF);
433
ieee80211_hw_set(hw, SUPPORTS_TX_FRAG);
434
435
hw->max_tx_fragments = 4;
436
437
if (phy->mt76->cap.has_2ghz) {
438
phy->mt76->sband_2g.sband.ht_cap.cap |=
439
IEEE80211_HT_CAP_LDPC_CODING |
440
IEEE80211_HT_CAP_MAX_AMSDU;
441
if (is_mt7915(&dev->mt76))
442
phy->mt76->sband_2g.sband.ht_cap.ampdu_density =
443
IEEE80211_HT_MPDU_DENSITY_4;
444
else
445
phy->mt76->sband_2g.sband.ht_cap.ampdu_density =
446
IEEE80211_HT_MPDU_DENSITY_2;
447
}
448
449
if (phy->mt76->cap.has_5ghz) {
450
struct ieee80211_sta_vht_cap *vht_cap;
451
452
vht_cap = &phy->mt76->sband_5g.sband.vht_cap;
453
phy->mt76->sband_5g.sband.ht_cap.cap |=
454
IEEE80211_HT_CAP_LDPC_CODING |
455
IEEE80211_HT_CAP_MAX_AMSDU;
456
457
if (is_mt7915(&dev->mt76)) {
458
phy->mt76->sband_5g.sband.ht_cap.ampdu_density =
459
IEEE80211_HT_MPDU_DENSITY_4;
460
461
vht_cap->cap |=
462
IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 |
463
IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
464
465
if (!dev->dbdc_support)
466
vht_cap->cap |=
467
IEEE80211_VHT_CAP_SHORT_GI_160 |
468
FIELD_PREP(IEEE80211_VHT_CAP_EXT_NSS_BW_MASK, 1);
469
} else {
470
phy->mt76->sband_5g.sband.ht_cap.ampdu_density =
471
IEEE80211_HT_MPDU_DENSITY_2;
472
473
vht_cap->cap |=
474
IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
475
IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
476
477
/* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */
478
vht_cap->cap |=
479
IEEE80211_VHT_CAP_SHORT_GI_160 |
480
IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
481
}
482
483
if (!is_mt7915(&dev->mt76) || !dev->dbdc_support)
484
ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
485
}
486
487
mt76_set_stream_caps(phy->mt76, true);
488
mt7915_set_stream_vht_txbf_caps(phy);
489
mt7915_set_stream_he_caps(phy);
490
mt7915_init_txpower(phy);
491
492
wiphy->available_antennas_rx = phy->mt76->antenna_mask;
493
wiphy->available_antennas_tx = phy->mt76->antenna_mask;
494
495
/* init led callbacks */
496
if (IS_ENABLED(CONFIG_MT76_LEDS)) {
497
mphy->leds.cdev.brightness_set = mt7915_led_set_brightness;
498
mphy->leds.cdev.blink_set = mt7915_led_set_blink;
499
}
500
}
501
502
static void
503
mt7915_mac_init_band(struct mt7915_dev *dev, u8 band)
504
{
505
u32 mask, set;
506
507
mt76_rmw_field(dev, MT_TMAC_CTCR0(band),
508
MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f);
509
mt76_set(dev, MT_TMAC_CTCR0(band),
510
MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN |
511
MT_TMAC_CTCR0_INS_DDLMT_EN);
512
513
mask = MT_MDP_RCFR0_MCU_RX_MGMT |
514
MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR |
515
MT_MDP_RCFR0_MCU_RX_CTL_BAR;
516
set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) |
517
FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) |
518
FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF);
519
mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set);
520
521
mask = MT_MDP_RCFR1_MCU_RX_BYPASS |
522
MT_MDP_RCFR1_RX_DROPPED_UCAST |
523
MT_MDP_RCFR1_RX_DROPPED_MCAST;
524
set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) |
525
FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) |
526
FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF);
527
mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set);
528
529
mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680);
530
531
/* mt7915: disable rx rate report by default due to hw issues */
532
mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN);
533
534
/* clear estimated value of EIFS for Rx duration & OBSS time */
535
mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR);
536
537
/* clear backoff time for Rx duration */
538
mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band),
539
MT_WF_RMAC_MIB_NONQOSD_BACKOFF);
540
mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band),
541
MT_WF_RMAC_MIB_QOS01_BACKOFF);
542
mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band),
543
MT_WF_RMAC_MIB_QOS23_BACKOFF);
544
545
/* clear backoff time for Tx duration */
546
mt76_clear(dev, MT_WTBLOFF_TOP_ACR(band),
547
MT_WTBLOFF_TOP_ADM_BACKOFFTIME);
548
549
/* exclude estimated backoff time for Tx duration on MT7915 */
550
if (is_mt7915(&dev->mt76))
551
mt76_set(dev, MT_AGG_ATCR0(band),
552
MT_AGG_ATCR_MAC_BFF_TIME_EN);
553
554
/* clear backoff time and set software compensation for OBSS time */
555
mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET;
556
set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) |
557
FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4);
558
mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set);
559
560
/* filter out non-resp frames and get instanstaeous signal reporting */
561
mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM;
562
set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) |
563
FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3);
564
mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set);
565
566
/* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than
567
* MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set.
568
*/
569
if (mtk_wed_device_active(&dev->mt76.mmio.wed))
570
mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H);
571
}
572
573
static void
574
mt7915_init_led_mux(struct mt7915_dev *dev)
575
{
576
if (!IS_ENABLED(CONFIG_MT76_LEDS))
577
return;
578
579
if (dev->dbdc_support) {
580
switch (mt76_chip(&dev->mt76)) {
581
case 0x7915:
582
mt76_rmw_field(dev, MT_LED_GPIO_MUX2,
583
GENMASK(11, 8), 4);
584
mt76_rmw_field(dev, MT_LED_GPIO_MUX3,
585
GENMASK(11, 8), 4);
586
break;
587
case 0x7986:
588
mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
589
GENMASK(7, 4), 1);
590
mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
591
GENMASK(11, 8), 1);
592
break;
593
case 0x7916:
594
mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
595
GENMASK(27, 24), 3);
596
mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
597
GENMASK(31, 28), 3);
598
break;
599
default:
600
break;
601
}
602
} else if (dev->mphy.leds.pin) {
603
switch (mt76_chip(&dev->mt76)) {
604
case 0x7915:
605
mt76_rmw_field(dev, MT_LED_GPIO_MUX3,
606
GENMASK(11, 8), 4);
607
break;
608
case 0x7986:
609
mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
610
GENMASK(11, 8), 1);
611
break;
612
case 0x7916:
613
mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
614
GENMASK(31, 28), 3);
615
break;
616
default:
617
break;
618
}
619
} else {
620
switch (mt76_chip(&dev->mt76)) {
621
case 0x7915:
622
mt76_rmw_field(dev, MT_LED_GPIO_MUX2,
623
GENMASK(11, 8), 4);
624
break;
625
case 0x7986:
626
mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
627
GENMASK(7, 4), 1);
628
break;
629
case 0x7916:
630
mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
631
GENMASK(27, 24), 3);
632
break;
633
default:
634
break;
635
}
636
}
637
}
638
639
void mt7915_mac_init(struct mt7915_dev *dev)
640
{
641
int i;
642
u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680;
643
644
/* config pse qid6 wfdma port selection */
645
if (!is_mt7915(&dev->mt76) && dev->hif2)
646
mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0,
647
MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK);
648
649
mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len);
650
651
if (!is_mt7915(&dev->mt76))
652
mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT);
653
else
654
mt76_clear(dev, MT_PLE_HOST_RPT0, MT_PLE_HOST_RPT0_TX_LATENCY);
655
656
/* enable hardware de-agg */
657
mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN);
658
659
for (i = 0; i < mt7915_wtbl_size(dev); i++)
660
mt7915_mac_wtbl_update(dev, i,
661
MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
662
for (i = 0; i < 2; i++)
663
mt7915_mac_init_band(dev, i);
664
665
mt7915_init_led_mux(dev);
666
}
667
668
int mt7915_txbf_init(struct mt7915_dev *dev)
669
{
670
int ret;
671
672
if (dev->dbdc_support) {
673
ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE);
674
if (ret)
675
return ret;
676
}
677
678
/* trigger sounding packets */
679
ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON);
680
if (ret)
681
return ret;
682
683
/* enable eBF */
684
return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE);
685
}
686
687
static struct mt7915_phy *
688
mt7915_alloc_ext_phy(struct mt7915_dev *dev)
689
{
690
struct mt7915_phy *phy;
691
struct mt76_phy *mphy;
692
693
if (!dev->dbdc_support)
694
return NULL;
695
696
mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1);
697
if (!mphy)
698
return ERR_PTR(-ENOMEM);
699
700
phy = mphy->priv;
701
phy->dev = dev;
702
phy->mt76 = mphy;
703
704
/* Bind main phy to band0 and ext_phy to band1 for dbdc case */
705
phy->mt76->band_idx = 1;
706
707
return phy;
708
}
709
710
static int
711
mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy)
712
{
713
struct mt76_phy *mphy = phy->mt76;
714
int ret;
715
716
INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work);
717
718
mt7915_eeprom_parse_hw_cap(dev, phy);
719
720
#if defined(__linux__)
721
memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2,
722
#elif defined(__FreeBSD__)
723
memcpy(mphy->macaddr, (u8 *)dev->mt76.eeprom.data + MT_EE_MAC_ADDR2,
724
#endif
725
ETH_ALEN);
726
/* Make the secondary PHY MAC address local without overlapping with
727
* the usual MAC address allocation scheme on multiple virtual interfaces
728
*/
729
if (!is_valid_ether_addr(mphy->macaddr)) {
730
#if defined(__linux__)
731
memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
732
#elif defined(__FreeBSD__)
733
memcpy(mphy->macaddr, (u8 *)dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
734
#endif
735
ETH_ALEN);
736
mphy->macaddr[0] |= 2;
737
mphy->macaddr[0] ^= BIT(7);
738
}
739
ret = mt76_eeprom_override(mphy);
740
if (ret)
741
return ret;
742
743
/* init wiphy according to mphy and phy */
744
mt7915_init_wiphy(phy);
745
746
ret = mt76_register_phy(mphy, true, mt76_rates,
747
ARRAY_SIZE(mt76_rates));
748
if (ret)
749
return ret;
750
751
ret = mt7915_thermal_init(phy);
752
if (ret)
753
goto unreg;
754
755
#if !defined(__FreeBSD__) || defined(CONFIG_MT7915_DEBUGFS)
756
mt7915_init_debugfs(phy);
757
#endif
758
759
return 0;
760
761
unreg:
762
mt76_unregister_phy(mphy);
763
return ret;
764
}
765
766
static void mt7915_init_work(struct work_struct *work)
767
{
768
struct mt7915_dev *dev = container_of(work, struct mt7915_dev,
769
init_work);
770
771
mt7915_mcu_set_eeprom(dev);
772
mt7915_mac_init(dev);
773
mt7915_txbf_init(dev);
774
}
775
776
void mt7915_wfsys_reset(struct mt7915_dev *dev)
777
{
778
#define MT_MCU_DUMMY_RANDOM GENMASK(15, 0)
779
#define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16)
780
781
if (is_mt7915(&dev->mt76)) {
782
u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON;
783
784
mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM);
785
786
/* change to software control */
787
val |= MT_TOP_PWR_SW_RST;
788
mt76_wr(dev, MT_TOP_PWR_CTRL, val);
789
790
/* reset wfsys */
791
val &= ~MT_TOP_PWR_SW_RST;
792
mt76_wr(dev, MT_TOP_PWR_CTRL, val);
793
794
/* release wfsys then mcu re-executes romcode */
795
val |= MT_TOP_PWR_SW_RST;
796
mt76_wr(dev, MT_TOP_PWR_CTRL, val);
797
798
/* switch to hw control */
799
val &= ~MT_TOP_PWR_SW_RST;
800
val |= MT_TOP_PWR_HW_CTRL;
801
mt76_wr(dev, MT_TOP_PWR_CTRL, val);
802
803
/* check whether mcu resets to default */
804
if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR,
805
MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT,
806
1000)) {
807
dev_err(dev->mt76.dev, "wifi subsystem reset failure\n");
808
return;
809
}
810
811
/* wfsys reset won't clear host registers */
812
mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE);
813
814
msleep(100);
815
} else if (is_mt798x(&dev->mt76)) {
816
mt7986_wmac_disable(dev);
817
msleep(20);
818
819
mt7986_wmac_enable(dev);
820
msleep(20);
821
} else {
822
mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
823
msleep(20);
824
825
mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
826
msleep(20);
827
}
828
}
829
830
static bool mt7915_band_config(struct mt7915_dev *dev)
831
{
832
bool ret = true;
833
834
dev->phy.mt76->band_idx = 0;
835
836
if (is_mt798x(&dev->mt76)) {
837
u32 sku = mt7915_check_adie(dev, true);
838
839
/*
840
* for mt7986, dbdc support is determined by the number
841
* of adie chips and the main phy is bound to band1 when
842
* dbdc is disabled.
843
*/
844
if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) {
845
dev->phy.mt76->band_idx = 1;
846
ret = false;
847
}
848
} else {
849
ret = is_mt7915(&dev->mt76) ?
850
!!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true;
851
}
852
853
return ret;
854
}
855
856
static int
857
mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2)
858
{
859
int ret, idx;
860
861
mt76_wr(dev, MT_INT_MASK_CSR, 0);
862
mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
863
864
INIT_WORK(&dev->init_work, mt7915_init_work);
865
866
ret = mt7915_dma_init(dev, phy2);
867
if (ret)
868
return ret;
869
870
set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
871
872
ret = mt7915_mcu_init(dev);
873
if (ret)
874
return ret;
875
876
ret = mt7915_eeprom_init(dev);
877
if (ret < 0)
878
return ret;
879
880
if (dev->cal) {
881
ret = mt7915_mcu_apply_group_cal(dev);
882
if (ret)
883
return ret;
884
}
885
886
/* Beacon and mgmt frames should occupy wcid 0 */
887
idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA);
888
if (idx)
889
return -ENOSPC;
890
891
dev->mt76.global_wcid.idx = idx;
892
dev->mt76.global_wcid.hw_key_idx = -1;
893
dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET;
894
rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid);
895
896
return 0;
897
}
898
899
void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy)
900
{
901
int sts;
902
u32 *cap;
903
904
if (!phy->mt76->cap.has_5ghz)
905
return;
906
907
sts = hweight8(phy->mt76->chainmask);
908
cap = &phy->mt76->sband_5g.sband.vht_cap.cap;
909
910
*cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
911
IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
912
FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK,
913
sts - 1);
914
915
*cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK |
916
IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
917
IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE);
918
919
if (sts < 2)
920
return;
921
922
*cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
923
IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE |
924
FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK,
925
sts - 1);
926
}
927
928
static void
929
mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy,
930
struct ieee80211_sta_he_cap *he_cap, int vif)
931
{
932
struct mt7915_dev *dev = phy->dev;
933
struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem;
934
int sts = hweight8(phy->mt76->chainmask);
935
u8 c, sts_160 = sts;
936
937
/* Can do 1/2 of STS in 160Mhz mode for mt7915 */
938
if (is_mt7915(&dev->mt76)) {
939
if (!dev->dbdc_support)
940
sts_160 /= 2;
941
else
942
sts_160 = 0;
943
}
944
945
#ifdef CONFIG_MAC80211_MESH
946
if (vif == NL80211_IFTYPE_MESH_POINT)
947
return;
948
#endif
949
950
elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
951
elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
952
953
c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK;
954
if (sts_160)
955
c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK;
956
elem->phy_cap_info[5] &= ~c;
957
958
c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
959
IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
960
elem->phy_cap_info[6] &= ~c;
961
962
elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
963
964
c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US;
965
if (!is_mt7915(&dev->mt76))
966
c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO;
967
elem->phy_cap_info[2] |= c;
968
969
c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
970
IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4;
971
if (sts_160)
972
c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
973
elem->phy_cap_info[4] |= c;
974
975
/* do not support NG16 due to spec D4.0 changes subcarrier idx */
976
c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
977
IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU;
978
979
if (vif == NL80211_IFTYPE_STATION)
980
c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO;
981
982
elem->phy_cap_info[6] |= c;
983
984
if (sts < 2)
985
return;
986
987
/* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */
988
elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3;
989
990
if (vif != NL80211_IFTYPE_AP && vif != NL80211_IFTYPE_STATION)
991
return;
992
993
elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
994
995
c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
996
sts - 1);
997
if (sts_160)
998
c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK,
999
sts_160 - 1);
1000
elem->phy_cap_info[5] |= c;
1001
1002
if (vif != NL80211_IFTYPE_AP)
1003
return;
1004
1005
elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
1006
1007
c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
1008
IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
1009
elem->phy_cap_info[6] |= c;
1010
1011
if (!is_mt7915(&dev->mt76)) {
1012
c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ |
1013
IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
1014
elem->phy_cap_info[7] |= c;
1015
}
1016
}
1017
1018
static int
1019
mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band,
1020
struct ieee80211_sband_iftype_data *data)
1021
{
1022
struct mt7915_dev *dev = phy->dev;
1023
int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask);
1024
u16 mcs_map = 0;
1025
u16 mcs_map_160 = 0;
1026
u8 nss_160;
1027
1028
if (!is_mt7915(&dev->mt76))
1029
nss_160 = nss;
1030
else if (!dev->dbdc_support)
1031
/* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */
1032
nss_160 = nss / 2;
1033
else
1034
/* Can't do 160MHz with mt7915 dbdc */
1035
nss_160 = 0;
1036
1037
for (i = 0; i < 8; i++) {
1038
if (i < nss)
1039
mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
1040
else
1041
mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
1042
1043
if (i < nss_160)
1044
mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
1045
else
1046
mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
1047
}
1048
1049
for (i = 0; i < NUM_NL80211_IFTYPES; i++) {
1050
struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap;
1051
struct ieee80211_he_cap_elem *he_cap_elem =
1052
&he_cap->he_cap_elem;
1053
struct ieee80211_he_mcs_nss_supp *he_mcs =
1054
&he_cap->he_mcs_nss_supp;
1055
1056
switch (i) {
1057
case NL80211_IFTYPE_STATION:
1058
case NL80211_IFTYPE_AP:
1059
#ifdef CONFIG_MAC80211_MESH
1060
case NL80211_IFTYPE_MESH_POINT:
1061
#endif
1062
break;
1063
default:
1064
continue;
1065
}
1066
1067
data[idx].types_mask = BIT(i);
1068
he_cap->has_he = true;
1069
1070
he_cap_elem->mac_cap_info[0] =
1071
IEEE80211_HE_MAC_CAP0_HTC_HE;
1072
he_cap_elem->mac_cap_info[3] =
1073
IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
1074
IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
1075
he_cap_elem->mac_cap_info[4] =
1076
IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
1077
1078
if (band == NL80211_BAND_2GHZ)
1079
he_cap_elem->phy_cap_info[0] =
1080
IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
1081
else if (nss_160)
1082
he_cap_elem->phy_cap_info[0] =
1083
IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
1084
IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
1085
else
1086
he_cap_elem->phy_cap_info[0] =
1087
IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G;
1088
1089
he_cap_elem->phy_cap_info[1] =
1090
IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD;
1091
he_cap_elem->phy_cap_info[2] =
1092
IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
1093
IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
1094
1095
switch (i) {
1096
case NL80211_IFTYPE_AP:
1097
he_cap_elem->mac_cap_info[0] |=
1098
IEEE80211_HE_MAC_CAP0_TWT_RES;
1099
he_cap_elem->mac_cap_info[2] |=
1100
IEEE80211_HE_MAC_CAP2_BSR;
1101
he_cap_elem->mac_cap_info[4] |=
1102
IEEE80211_HE_MAC_CAP4_BQR;
1103
he_cap_elem->mac_cap_info[5] |=
1104
IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX;
1105
he_cap_elem->phy_cap_info[3] |=
1106
IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1107
IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1108
he_cap_elem->phy_cap_info[6] |=
1109
IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1110
IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1111
he_cap_elem->phy_cap_info[9] |=
1112
IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1113
IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
1114
break;
1115
case NL80211_IFTYPE_STATION:
1116
he_cap_elem->mac_cap_info[1] |=
1117
IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
1118
1119
if (band == NL80211_BAND_2GHZ)
1120
he_cap_elem->phy_cap_info[0] |=
1121
IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G;
1122
else
1123
he_cap_elem->phy_cap_info[0] |=
1124
IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G;
1125
1126
he_cap_elem->phy_cap_info[1] |=
1127
IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
1128
IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
1129
he_cap_elem->phy_cap_info[3] |=
1130
IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1131
IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1132
he_cap_elem->phy_cap_info[6] |=
1133
IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB |
1134
IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1135
IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1136
he_cap_elem->phy_cap_info[7] |=
1137
IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
1138
IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI;
1139
he_cap_elem->phy_cap_info[8] |=
1140
IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
1141
IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484;
1142
if (nss_160)
1143
he_cap_elem->phy_cap_info[8] |=
1144
IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
1145
IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;
1146
he_cap_elem->phy_cap_info[9] |=
1147
IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
1148
IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
1149
IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1150
IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
1151
IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
1152
IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB;
1153
break;
1154
}
1155
1156
memset(he_mcs, 0, sizeof(*he_mcs));
1157
he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map);
1158
he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map);
1159
he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160);
1160
he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160);
1161
1162
mt7915_set_stream_he_txbf_caps(phy, he_cap, i);
1163
1164
memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres));
1165
if (he_cap_elem->phy_cap_info[6] &
1166
IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) {
1167
mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band);
1168
} else {
1169
he_cap_elem->phy_cap_info[9] |=
1170
u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
1171
IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
1172
}
1173
1174
if (band == NL80211_BAND_6GHZ) {
1175
u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS |
1176
IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
1177
1178
cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2,
1179
IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
1180
u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
1181
IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
1182
u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
1183
IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
1184
1185
data[idx].he_6ghz_capa.capa = cpu_to_le16(cap);
1186
}
1187
1188
idx++;
1189
}
1190
1191
return idx;
1192
}
1193
1194
void mt7915_set_stream_he_caps(struct mt7915_phy *phy)
1195
{
1196
struct ieee80211_sband_iftype_data *data;
1197
struct ieee80211_supported_band *band;
1198
int n;
1199
1200
if (phy->mt76->cap.has_2ghz) {
1201
data = phy->iftype[NL80211_BAND_2GHZ];
1202
n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data);
1203
1204
band = &phy->mt76->sband_2g.sband;
1205
_ieee80211_set_sband_iftype_data(band, data, n);
1206
}
1207
1208
if (phy->mt76->cap.has_5ghz) {
1209
data = phy->iftype[NL80211_BAND_5GHZ];
1210
n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data);
1211
1212
band = &phy->mt76->sband_5g.sband;
1213
_ieee80211_set_sband_iftype_data(band, data, n);
1214
}
1215
1216
if (phy->mt76->cap.has_6ghz) {
1217
data = phy->iftype[NL80211_BAND_6GHZ];
1218
n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data);
1219
1220
band = &phy->mt76->sband_6g.sband;
1221
_ieee80211_set_sband_iftype_data(band, data, n);
1222
}
1223
}
1224
1225
static void mt7915_unregister_ext_phy(struct mt7915_dev *dev)
1226
{
1227
struct mt7915_phy *phy = mt7915_ext_phy(dev);
1228
struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1];
1229
1230
if (!phy)
1231
return;
1232
1233
#if defined(__linux__)
1234
mt7915_unregister_thermal(phy);
1235
#endif
1236
mt76_unregister_phy(mphy);
1237
ieee80211_free_hw(mphy->hw);
1238
}
1239
1240
static void mt7915_stop_hardware(struct mt7915_dev *dev)
1241
{
1242
mt7915_mcu_exit(dev);
1243
mt76_connac2_tx_token_put(&dev->mt76);
1244
mt7915_dma_cleanup(dev);
1245
tasklet_disable(&dev->mt76.irq_tasklet);
1246
1247
if (is_mt798x(&dev->mt76))
1248
mt7986_wmac_disable(dev);
1249
}
1250
1251
int mt7915_register_device(struct mt7915_dev *dev)
1252
{
1253
struct mt7915_phy *phy2;
1254
int ret;
1255
1256
dev->phy.dev = dev;
1257
dev->phy.mt76 = &dev->mt76.phy;
1258
dev->mt76.phy.priv = &dev->phy;
1259
INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work);
1260
INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work);
1261
INIT_LIST_HEAD(&dev->sta_rc_list);
1262
INIT_LIST_HEAD(&dev->twt_list);
1263
1264
init_waitqueue_head(&dev->reset_wait);
1265
INIT_WORK(&dev->reset_work, mt7915_mac_reset_work);
1266
INIT_WORK(&dev->dump_work, mt7915_mac_dump_work);
1267
mutex_init(&dev->dump_mutex);
1268
1269
dev->dbdc_support = mt7915_band_config(dev);
1270
1271
phy2 = mt7915_alloc_ext_phy(dev);
1272
if (IS_ERR(phy2))
1273
return PTR_ERR(phy2);
1274
1275
ret = mt7915_init_hardware(dev, phy2);
1276
if (ret)
1277
goto free_phy2;
1278
1279
mt7915_init_wiphy(&dev->phy);
1280
1281
#ifdef CONFIG_NL80211_TESTMODE
1282
dev->mt76.test_ops = &mt7915_testmode_ops;
1283
#endif
1284
1285
ret = mt76_register_device(&dev->mt76, true, mt76_rates,
1286
ARRAY_SIZE(mt76_rates));
1287
if (ret)
1288
goto stop_hw;
1289
1290
ret = mt7915_thermal_init(&dev->phy);
1291
if (ret)
1292
goto unreg_dev;
1293
1294
if (phy2) {
1295
ret = mt7915_register_ext_phy(dev, phy2);
1296
if (ret)
1297
goto unreg_thermal;
1298
}
1299
1300
ieee80211_queue_work(mt76_hw(dev), &dev->init_work);
1301
1302
dev->recovery.hw_init_done = true;
1303
1304
#if !defined(__FreeBSD__) || defined(CONFIG_MT7915_DEBUGFS)
1305
ret = mt7915_init_debugfs(&dev->phy);
1306
if (ret)
1307
goto unreg_thermal;
1308
#endif
1309
1310
ret = mt7915_coredump_register(dev);
1311
if (ret)
1312
goto unreg_thermal;
1313
1314
return 0;
1315
1316
unreg_thermal:
1317
#if defined(__linux__)
1318
mt7915_unregister_thermal(&dev->phy);
1319
#endif
1320
unreg_dev:
1321
mt76_unregister_device(&dev->mt76);
1322
stop_hw:
1323
mt7915_stop_hardware(dev);
1324
free_phy2:
1325
if (phy2)
1326
ieee80211_free_hw(phy2->mt76->hw);
1327
return ret;
1328
}
1329
1330
void mt7915_unregister_device(struct mt7915_dev *dev)
1331
{
1332
mt7915_unregister_ext_phy(dev);
1333
mt7915_coredump_unregister(dev);
1334
#if defined(__linux__)
1335
mt7915_unregister_thermal(&dev->phy);
1336
#endif
1337
mt76_unregister_device(&dev->mt76);
1338
mt7915_stop_hardware(dev);
1339
1340
mt76_free_device(&dev->mt76);
1341
}
1342
1343