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freebsd
GitHub Repository: freebsd/freebsd-src
 Path: blob/main/sys/contrib/dev/rtw88/rtw8703b.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */

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/* Copyright Fiona Klute <[email protected]> */

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#ifndef __RTW8703B_H__

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#define __RTW8703B_H__

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#include "rtw8723x.h"

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extern const struct rtw_chip_info rtw8703b_hw_spec;

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/* phy status parsing */

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#define VGA_BITS GENMASK(4, 0)

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#define LNA_L_BITS GENMASK(7, 5)

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#define LNA_H_BIT BIT(7)

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/* masks for assembling LNA index from high and low bits */

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#define BIT_LNA_H_MASK BIT(3)

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#define BIT_LNA_L_MASK GENMASK(2, 0)

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struct phy_rx_agc_info {

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#ifdef __LITTLE_ENDIAN

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	u8 gain: 7;

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	u8 trsw: 1;

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#else

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	u8 trsw: 1;

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	u8 gain: 7;

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#endif

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} __packed;

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/* This struct is called phy_status_rpt_8192cd in the vendor driver,

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 * there might be potential to share it with drivers for other chips

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 * of the same generation.

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 */

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struct phy_status_8703b {

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	struct phy_rx_agc_info path_agc[2];

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	u8 ch_corr[2];

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	u8 cck_sig_qual_ofdm_pwdb_all;

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	/* for CCK: bits 0:4: VGA index, bits 5:7: LNA index (low) */

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	u8 cck_agc_rpt_ofdm_cfosho_a;

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	/* for CCK: bit 7 is high bit of LNA index if long report type */

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	u8 cck_rpt_b_ofdm_cfosho_b;

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	u8 reserved_1;

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	u8 noise_power_db_msb;

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	s8 path_cfotail[2];

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	u8 pcts_mask[2];

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	s8 stream_rxevm[2];

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	u8 path_rxsnr[2];

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	u8 noise_power_db_lsb;

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	u8 reserved_2[3];

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	u8 stream_csi[2];

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	u8 stream_target_csi[2];

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	s8 sig_evm;

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	u8 reserved_3;

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#ifdef __LITTLE_ENDIAN

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	u8 antsel_rx_keep_2: 1;

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	u8 sgi_en: 1;

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	u8 rxsc: 2;

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	u8 idle_long: 1;

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	u8 r_ant_train_en: 1;

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	u8 ant_sel_b: 1;

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	u8 ant_sel: 1;

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#else /* __BIG_ENDIAN */

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	u8 ant_sel: 1;

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	u8 ant_sel_b: 1;

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	u8 r_ant_train_en: 1;

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	u8 idle_long: 1;

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	u8 rxsc: 2;

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	u8 sgi_en: 1;

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	u8 antsel_rx_keep_2: 1;

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#endif

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} __packed;

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/* Baseband registers */

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#define REG_BB_PWR_SAV5_11N 0x0818

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/* BIT(11) should be 1 for 8703B *and* 8723D, which means LNA uses 4

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 * bit for CCK rates in report, not 3. Vendor driver logs a warning if

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 * it's 0, but handles the case.

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 *

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 * Purpose of other parts of this register is unknown, 8723cs driver

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 * code indicates some other chips use certain bits for antenna

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 * diversity.

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 */

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#define REG_BB_AMP 0x0950

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#define BIT_MASK_RX_LNA (BIT(11))

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/* 0xaXX: 40MHz channel settings */

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#define REG_CCK_TXSF2 0x0a24  /* CCK TX filter 2 */

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#define REG_CCK_DBG 0x0a28  /* debug port */

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#define REG_OFDM0_A_TX_AFE 0x0c84

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#define REG_TXIQK_MATRIXB_LSB2_11N 0x0c9c

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#define REG_OFDM0_TX_PSD_NOISE 0x0ce4  /* TX pseudo noise weighting */

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#define REG_IQK_RDY 0x0e90  /* is != 0 when IQK is done */

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/* RF registers */

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#define RF_RCK1 0x1E

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#define AGG_BURST_NUM 3

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#define AGG_BURST_SIZE 0 /* 1K */

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#define BIT_MASK_AGG_BURST_NUM (GENMASK(3, 2))

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#define BIT_MASK_AGG_BURST_SIZE (GENMASK(5, 4))

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#endif /* __RTW8703B_H__ */

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