CoCalc -- rtw8851b_rfk

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/contrib/dev/rtw89/rtw8851b_rfk_table.c
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/* Copyright(c) 2022-2023  Realtek Corporation
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 */
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#include "rtw8851b_rfk_table.h"
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static const struct rtw89_reg5_def rtw8851b_dadck_setup_defs[] = {
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	RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
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	RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
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	RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
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	RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
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	RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
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	RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
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	RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
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	RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
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	RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
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	RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
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	RTW89_DECL_RFK_WM(0x030c, 0x0f000000, 0x3),
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	RTW89_DECL_RFK_WM(0xc0f4, BIT(2), 0x0),
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	RTW89_DECL_RFK_WM(0xc0f4, BIT(4), 0x0),
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	RTW89_DECL_RFK_WM(0xc0f4, BIT(11), 0x1),
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	RTW89_DECL_RFK_WM(0xc0f4, BIT(11), 0x0),
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	RTW89_DECL_RFK_DELAY(1),
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	RTW89_DECL_RFK_WM(0xc0f4, 0x300, 0x1),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_dadck_setup_defs);
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static const struct rtw89_reg5_def rtw8851b_dadck_post_defs[] = {
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	RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x1),
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	RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x0),
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	RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0xc),
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	RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x1),
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	RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x0),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_dadck_post_defs);
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static const struct rtw89_reg5_def rtw8851b_dack_s0_1_defs[] = {
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	RTW89_DECL_RFK_WM(0x12a0, BIT(15), 0x1),
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	RTW89_DECL_RFK_WM(0x12a0, 0x7000, 0x3),
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	RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
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	RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
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	RTW89_DECL_RFK_WM(0x032c, 0x80000000, 0x0),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_dack_s0_1_defs);
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static const struct rtw89_reg5_def rtw8851b_dack_s0_2_defs[] = {
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	RTW89_DECL_RFK_WM(0xc004, BIT(0), 0x0),
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	RTW89_DECL_RFK_WM(0x12a0, BIT(15), 0x0),
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	RTW89_DECL_RFK_WM(0x12a0, 0x7000, 0x7),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_dack_s0_2_defs);
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static const struct rtw89_reg5_def rtw8851b_dack_manual_off_defs[] = {
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	RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x0),
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	RTW89_DECL_RFK_WM(0xc210, BIT(0), 0x0),
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	RTW89_DECL_RFK_WM(0xc224, BIT(0), 0x0),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_dack_manual_off_defs);
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static const struct rtw89_reg5_def rtw8851b_iqk_rxclk_80_defs[] = {
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	RTW89_DECL_RFK_WM(0x5670, 0x60000000, 0x1),
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	RTW89_DECL_RFK_WM(0xc0ec, 0x00006000, 0x0),
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	RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x1),
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	RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x0f),
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	RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x03),
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	RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0001),
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	RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041),
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	RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x1101),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_rxclk_80_defs);
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static const struct rtw89_reg5_def rtw8851b_iqk_rxclk_others_defs[] = {
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	RTW89_DECL_RFK_WM(0x5670, 0x60000000, 0x0),
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	RTW89_DECL_RFK_WM(0xc0ec, 0x00006000, 0x2),
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	RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x1),
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	RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x0f),
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	RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x03),
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	RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0001),
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	RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041),
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	RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x1101),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_rxclk_others_defs);
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static const struct rtw89_reg5_def rtw8851b_iqk_txk_2ghz_defs[] = {
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x51, 0x80000, 0x0),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x51, 0x00800, 0x0),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x52, 0x00800, 0x0),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x55, 0x0001f, 0x4),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0xef, 0x00004, 0x1),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x00, 0xffff0, 0x403e),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x11, 0x00003, 0x0),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x11, 0x00070, 0x6),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x11, 0x1f000, 0x10),
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	RTW89_DECL_RFK_DELAY(1),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_txk_2ghz_defs);
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static const struct rtw89_reg5_def rtw8851b_iqk_txk_5ghz_defs[] = {
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x60, 0x00007, 0x0),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x55, 0x0001f, 0x4),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0xef, 0x00004, 0x1),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x00, 0xffff0, 0x403e),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x11, 0x00003, 0x0),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x11, 0x00070, 0x7),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x11, 0x1f000, 0x7),
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	RTW89_DECL_RFK_DELAY(1),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_txk_5ghz_defs);
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static const struct rtw89_reg5_def rtw8851b_iqk_afebb_restore_defs[] = {
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	RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x0),
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	RTW89_DECL_RFK_WM(0x20fc, 0x00010000, 0x1),
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	RTW89_DECL_RFK_WM(0x20fc, 0x00100000, 0x0),
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	RTW89_DECL_RFK_WM(0x20fc, 0x01000000, 0x1),
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	RTW89_DECL_RFK_WM(0x20fc, 0x10000000, 0x0),
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	RTW89_DECL_RFK_WM(0x5670, MASKDWORD, 0x00000000),
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	RTW89_DECL_RFK_WM(0x12a0, 0x000ff000, 0x00),
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	RTW89_DECL_RFK_WM(0x20fc, 0x00010000, 0x0),
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	RTW89_DECL_RFK_WM(0x20fc, 0x01000000, 0x0),
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x10005, 0x00001, 0x1),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_afebb_restore_defs);
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static const struct rtw89_reg5_def rtw8851b_iqk_macbb_defs[] = {
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	RTW89_DECL_RFK_WRF(RF_PATH_A, 0x10005, 0x00001, 0x0),
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	RTW89_DECL_RFK_WM(0x20fc, 0x00010000, 0x1),
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	RTW89_DECL_RFK_WM(0x20fc, 0x00100000, 0x0),
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	RTW89_DECL_RFK_WM(0x20fc, 0x01000000, 0x1),
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	RTW89_DECL_RFK_WM(0x20fc, 0x10000000, 0x0),
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	RTW89_DECL_RFK_WM(0x5670, MASKDWORD, 0xf801fffd),
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	RTW89_DECL_RFK_WM(0x5670, 0x00004000, 0x1),
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	RTW89_DECL_RFK_WM(0x5670, 0x80000000, 0x1),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_macbb_defs);
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static const struct rtw89_reg5_def rtw8851b_iqk_macbb_bh_defs[] = {
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	RTW89_DECL_RFK_WM(0x5670, 0x60000000, 0x2),
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	RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x1),
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	RTW89_DECL_RFK_DELAY(2),
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	RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x1f),
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	RTW89_DECL_RFK_DELAY(10),
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	RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x13),
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	RTW89_DECL_RFK_DELAY(2),
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	RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0001),
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	RTW89_DECL_RFK_DELAY(2),
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	RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041),
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	RTW89_DECL_RFK_DELAY(10),
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	RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x1),
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	RTW89_DECL_RFK_DELAY(2),
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	RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x1f),
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	RTW89_DECL_RFK_DELAY(10),
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	RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x13),
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	RTW89_DECL_RFK_DELAY(2),
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	RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0001),
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	RTW89_DECL_RFK_DELAY(2),
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	RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041),
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	RTW89_DECL_RFK_DELAY(10),
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	RTW89_DECL_RFK_WM(0x20fc, 0x00100000, 0x1),
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	RTW89_DECL_RFK_WM(0x20fc, 0x10000000, 0x1),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_macbb_bh_defs);
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static const struct rtw89_reg5_def rtw8851b_tssi_sys_defs[] = {
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	RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0xb5b5),
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	RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0xb5b5),
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	RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16),
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	RTW89_DECL_RFK_WM(0x0304, 0x0000ffff, 0x1f19),
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	RTW89_DECL_RFK_WM(0x0308, 0xff000000, 0x1c),
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	RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041),
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	RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041),
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	RTW89_DECL_RFK_WM(0x0324, 0xffff0000, 0x2001),
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	RTW89_DECL_RFK_WM(0x0020, 0x00006000, 0x3),
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	RTW89_DECL_RFK_WM(0x0024, 0x00006000, 0x3),
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	RTW89_DECL_RFK_WM(0x0704, 0xffff0000, 0x601e),
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	RTW89_DECL_RFK_WM(0x2704, 0xffff0000, 0x601e),
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	RTW89_DECL_RFK_WM(0x0700, 0xf0000000, 0x4),
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	RTW89_DECL_RFK_WM(0x2700, 0xf0000000, 0x4),
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	RTW89_DECL_RFK_WM(0x0650, 0x3c000000, 0x0),
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	RTW89_DECL_RFK_WM(0x2650, 0x3c000000, 0x0),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_sys_defs);
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static const struct rtw89_reg5_def rtw8851b_tssi_sys_a_defs_2g[] = {
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	RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x33),
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	RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x33),
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	RTW89_DECL_RFK_WM(0x58f8, 0x40000000, 0x1),
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	RTW89_DECL_RFK_WM(0x5814, 0x20000000, 0x0),
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};
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RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_sys_a_defs_2g);
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static const struct rtw89_reg5_def rtw8851b_tssi_sys_a_defs_5g[] = {
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	RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x44),
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	RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x44),
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	RTW89_DECL_RFK_WM(0x58f8, 0x40000000, 0x0),
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	RTW89_DECL_RFK_WM(0x5814, 0x20000000, 0x0),
210
};
211

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RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_sys_a_defs_5g);
213

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static const struct rtw89_reg5_def rtw8851b_tssi_init_txpwr_defs_a[] = {
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	RTW89_DECL_RFK_WM(0x566c, 0x00001000, 0x0),
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	RTW89_DECL_RFK_WM(0x5800, 0xffffffff, 0x003f807f),
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	RTW89_DECL_RFK_WM(0x580c, 0x0000007f, 0x40),
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	RTW89_DECL_RFK_WM(0x580c, 0x0fffff00, 0x00040),
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	RTW89_DECL_RFK_WM(0x5810, 0xffffffff, 0x59010000),
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	RTW89_DECL_RFK_WM(0x5814, 0x01ffffff, 0x026d000),
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	RTW89_DECL_RFK_WM(0x5814, 0xf8000000, 0x00),
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	RTW89_DECL_RFK_WM(0x5818, 0x00ffffff, 0x2c18e8),
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	RTW89_DECL_RFK_WM(0x5818, 0x07000000, 0x0),
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	RTW89_DECL_RFK_WM(0x5818, 0xf0000000, 0x0),
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	RTW89_DECL_RFK_WM(0x581c, 0x3fffffff, 0x3dc80280),
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	RTW89_DECL_RFK_WM(0x5820, 0xffffffff, 0x00000080),
227
	RTW89_DECL_RFK_WM(0x58e8, 0x0000003f, 0x04),
228
	RTW89_DECL_RFK_WM(0x580c, 0x10000000, 0x1),
229
	RTW89_DECL_RFK_WM(0x580c, 0x40000000, 0x1),
230
	RTW89_DECL_RFK_WM(0x5834, 0x3fffffff, 0x000115f2),
231
	RTW89_DECL_RFK_WM(0x5838, 0x7fffffff, 0x0000121),
232
	RTW89_DECL_RFK_WM(0x5854, 0x3fffffff, 0x000115f2),
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	RTW89_DECL_RFK_WM(0x5858, 0x7fffffff, 0x0000121),
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	RTW89_DECL_RFK_WM(0x5860, 0x80000000, 0x0),
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	RTW89_DECL_RFK_WM(0x5864, 0x07ffffff, 0x00801ff),
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	RTW89_DECL_RFK_WM(0x5898, MASKDWORD, 0x00000000),
237
	RTW89_DECL_RFK_WM(0x589c, MASKDWORD, 0x00000000),
238
	RTW89_DECL_RFK_WM(0x58a4, 0x000000ff, 0x16),
239
	RTW89_DECL_RFK_WM(0x58b0, MASKDWORD, 0x00000000),
240
	RTW89_DECL_RFK_WM(0x58b4, 0x7fffffff, 0x0a002000),
241
	RTW89_DECL_RFK_WM(0x58b8, 0x7fffffff, 0x00007628),
242
	RTW89_DECL_RFK_WM(0x58bc, 0x07ffffff, 0x7a7807f),
243
	RTW89_DECL_RFK_WM(0x58c0, 0xfffe0000, 0x003f),
244
	RTW89_DECL_RFK_WM(0x58c4, 0xffffffff, 0x0003ffff),
245
	RTW89_DECL_RFK_WM(0x58c8, 0x00ffffff, 0x000000),
246
	RTW89_DECL_RFK_WM(0x58c8, 0xf0000000, 0x0),
247
	RTW89_DECL_RFK_WM(0x58cc, MASKDWORD, 0x00000000),
248
	RTW89_DECL_RFK_WM(0x58d0, 0x07ffffff, 0x2008101),
249
	RTW89_DECL_RFK_WM(0x58d4, 0x000000ff, 0x00),
250
	RTW89_DECL_RFK_WM(0x58d4, 0x0003fe00, 0x0ff),
251
	RTW89_DECL_RFK_WM(0x58d4, 0x07fc0000, 0x100),
252
	RTW89_DECL_RFK_WM(0x58d8, 0xffffffff, 0x8008016c),
253
	RTW89_DECL_RFK_WM(0x58dc, 0x0001ffff, 0x0807f),
254
	RTW89_DECL_RFK_WM(0x58dc, 0xfff00000, 0x800),
255
	RTW89_DECL_RFK_WM(0x58f0, 0x0003ffff, 0x001ff),
256
	RTW89_DECL_RFK_WM(0x58f4, 0x000fffff, 0x00000),
257
	RTW89_DECL_RFK_WM(0x58f8, 0x000fffff, 0x00000),
258
};
259

260
RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_init_txpwr_defs_a);
261

262
static const struct rtw89_reg5_def rtw8851b_tssi_init_txpwr_he_tb_defs_a[] = {
263
	RTW89_DECL_RFK_WM(0x58a0, MASKDWORD, 0x000000fe),
264
	RTW89_DECL_RFK_WM(0x58e4, 0x0000007f, 0x1f),
265
};
266

267
RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_init_txpwr_he_tb_defs_a);
268

269
static const struct rtw89_reg5_def rtw8851b_tssi_dck_defs_a[] = {
270
	RTW89_DECL_RFK_WM(0x580c, 0x0fff0000, 0x000),
271
	RTW89_DECL_RFK_WM(0x5814, 0x00001000, 0x1),
272
	RTW89_DECL_RFK_WM(0x5814, 0x00002000, 0x1),
273
	RTW89_DECL_RFK_WM(0x5814, 0x00004000, 0x1),
274
	RTW89_DECL_RFK_WM(0x5814, 0x00038000, 0x3),
275
	RTW89_DECL_RFK_WM(0x5814, 0x003c0000, 0x5),
276
	RTW89_DECL_RFK_WM(0x5814, 0x18000000, 0x0),
277
};
278

279
RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_dck_defs_a);
280

281
static const struct rtw89_reg5_def rtw8851b_tssi_dac_gain_defs_a[] = {
282
	RTW89_DECL_RFK_WM(0x58b0, 0x00000fff, 0x000),
283
	RTW89_DECL_RFK_WM(0x5a00, MASKDWORD, 0x00000000),
284
	RTW89_DECL_RFK_WM(0x5a04, MASKDWORD, 0x00000000),
285
	RTW89_DECL_RFK_WM(0x5a08, MASKDWORD, 0x00000000),
286
	RTW89_DECL_RFK_WM(0x5a0c, MASKDWORD, 0x00000000),
287
	RTW89_DECL_RFK_WM(0x5a10, MASKDWORD, 0x00000000),
288
	RTW89_DECL_RFK_WM(0x5a14, MASKDWORD, 0x00000000),
289
	RTW89_DECL_RFK_WM(0x5a18, MASKDWORD, 0x00000000),
290
	RTW89_DECL_RFK_WM(0x5a1c, MASKDWORD, 0x00000000),
291
	RTW89_DECL_RFK_WM(0x5a20, MASKDWORD, 0x00000000),
292
	RTW89_DECL_RFK_WM(0x5a24, MASKDWORD, 0x00000000),
293
	RTW89_DECL_RFK_WM(0x5a28, MASKDWORD, 0x00000000),
294
	RTW89_DECL_RFK_WM(0x5a2c, MASKDWORD, 0x00000000),
295
	RTW89_DECL_RFK_WM(0x5a30, MASKDWORD, 0x00000000),
296
	RTW89_DECL_RFK_WM(0x5a34, MASKDWORD, 0x00000000),
297
	RTW89_DECL_RFK_WM(0x5a38, MASKDWORD, 0x00000000),
298
	RTW89_DECL_RFK_WM(0x5a3c, MASKDWORD, 0x00000000),
299
	RTW89_DECL_RFK_WM(0x5a40, MASKDWORD, 0x00000000),
300
	RTW89_DECL_RFK_WM(0x5a44, MASKDWORD, 0x00000000),
301
	RTW89_DECL_RFK_WM(0x5a48, MASKDWORD, 0x00000000),
302
	RTW89_DECL_RFK_WM(0x5a4c, MASKDWORD, 0x00000000),
303
	RTW89_DECL_RFK_WM(0x5a50, MASKDWORD, 0x00000000),
304
	RTW89_DECL_RFK_WM(0x5a54, MASKDWORD, 0x00000000),
305
	RTW89_DECL_RFK_WM(0x5a58, MASKDWORD, 0x00000000),
306
	RTW89_DECL_RFK_WM(0x5a5c, MASKDWORD, 0x00000000),
307
	RTW89_DECL_RFK_WM(0x5a60, MASKDWORD, 0x00000000),
308
	RTW89_DECL_RFK_WM(0x5a64, MASKDWORD, 0x00000000),
309
	RTW89_DECL_RFK_WM(0x5a68, MASKDWORD, 0x00000000),
310
	RTW89_DECL_RFK_WM(0x5a6c, MASKDWORD, 0x00000000),
311
	RTW89_DECL_RFK_WM(0x5a70, MASKDWORD, 0x00000000),
312
	RTW89_DECL_RFK_WM(0x5a74, MASKDWORD, 0x00000000),
313
	RTW89_DECL_RFK_WM(0x5a78, MASKDWORD, 0x00000000),
314
	RTW89_DECL_RFK_WM(0x5a7c, MASKDWORD, 0x00000000),
315
	RTW89_DECL_RFK_WM(0x5a80, MASKDWORD, 0x00000000),
316
	RTW89_DECL_RFK_WM(0x5a84, MASKDWORD, 0x00000000),
317
	RTW89_DECL_RFK_WM(0x5a88, MASKDWORD, 0x00000000),
318
	RTW89_DECL_RFK_WM(0x5a8c, MASKDWORD, 0x00000000),
319
	RTW89_DECL_RFK_WM(0x5a90, MASKDWORD, 0x00000000),
320
	RTW89_DECL_RFK_WM(0x5a94, MASKDWORD, 0x00000000),
321
	RTW89_DECL_RFK_WM(0x5a98, MASKDWORD, 0x00000000),
322
	RTW89_DECL_RFK_WM(0x5a9c, MASKDWORD, 0x00000000),
323
	RTW89_DECL_RFK_WM(0x5aa0, MASKDWORD, 0x00000000),
324
	RTW89_DECL_RFK_WM(0x5aa4, MASKDWORD, 0x00000000),
325
	RTW89_DECL_RFK_WM(0x5aa8, MASKDWORD, 0x00000000),
326
	RTW89_DECL_RFK_WM(0x5aac, MASKDWORD, 0x00000000),
327
	RTW89_DECL_RFK_WM(0x5ab0, MASKDWORD, 0x00000000),
328
	RTW89_DECL_RFK_WM(0x5ab4, MASKDWORD, 0x00000000),
329
	RTW89_DECL_RFK_WM(0x5ab8, MASKDWORD, 0x00000000),
330
	RTW89_DECL_RFK_WM(0x5abc, MASKDWORD, 0x00000000),
331
	RTW89_DECL_RFK_WM(0x5ac0, MASKDWORD, 0x00000000),
332
};
333

334
RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_dac_gain_defs_a);
335

336
static const struct rtw89_reg5_def rtw8851b_tssi_slope_a_defs_2g[] = {
337
	RTW89_DECL_RFK_WM(0x5608, 0x07ffffff, 0x0201008),
338
	RTW89_DECL_RFK_WM(0x560c, 0x07ffffff, 0x0201008),
339
	RTW89_DECL_RFK_WM(0x5610, 0x07ffffff, 0x0200e08),
340
	RTW89_DECL_RFK_WM(0x5614, 0x07ffffff, 0x0201008),
341
	RTW89_DECL_RFK_WM(0x5618, 0x07ffffff, 0x0201008),
342
	RTW89_DECL_RFK_WM(0x561c, 0x000001ff, 0x007),
343
	RTW89_DECL_RFK_WM(0x561c, 0xffff0000, 0x0808),
344
	RTW89_DECL_RFK_WM(0x5620, 0xffffffff, 0x08080808),
345
	RTW89_DECL_RFK_WM(0x5624, 0xffffffff, 0x08080808),
346
	RTW89_DECL_RFK_WM(0x5628, 0xffffffff, 0x08080808),
347
	RTW89_DECL_RFK_WM(0x562c, 0x0000ffff, 0x0808),
348
	RTW89_DECL_RFK_WM(0x581c, 0x00100000, 0x1),
349
};
350

351
RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_slope_a_defs_2g);
352

353
static const struct rtw89_reg5_def rtw8851b_tssi_slope_a_defs_5g[] = {
354
	RTW89_DECL_RFK_WM(0x5608, 0x07ffffff, 0x0201008),
355
	RTW89_DECL_RFK_WM(0x560c, 0x07ffffff, 0x0341a08),
356
	RTW89_DECL_RFK_WM(0x5610, 0x07ffffff, 0x0201417),
357
	RTW89_DECL_RFK_WM(0x5614, 0x07ffffff, 0x0201008),
358
	RTW89_DECL_RFK_WM(0x5618, 0x07ffffff, 0x0201008),
359
	RTW89_DECL_RFK_WM(0x561c, 0x000001ff, 0x008),
360
	RTW89_DECL_RFK_WM(0x561c, 0xffff0000, 0x0808),
361
	RTW89_DECL_RFK_WM(0x5620, 0xffffffff, 0x0e0e0808),
362
	RTW89_DECL_RFK_WM(0x5624, 0xffffffff, 0x08080d18),
363
	RTW89_DECL_RFK_WM(0x5628, 0xffffffff, 0x08080808),
364
	RTW89_DECL_RFK_WM(0x562c, 0x0000ffff, 0x0808),
365
	RTW89_DECL_RFK_WM(0x581c, 0x00100000, 0x1),
366
};
367

368
RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_slope_a_defs_5g);
369

370
static const struct rtw89_reg5_def rtw8851b_tssi_align_a_2g_defs[] = {
371
	RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
372
	RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x000000),
373
	RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x2d2400),
374
	RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x00000000),
375
	RTW89_DECL_RFK_WM(0x5634, 0x000003ff, 0x000),
376
	RTW89_DECL_RFK_WM(0x5634, 0x000ffc00, 0x000),
377
	RTW89_DECL_RFK_WM(0x5634, 0x3ff00000, 0x3fa),
378
	RTW89_DECL_RFK_WM(0x5638, 0x000003ff, 0x02e),
379
	RTW89_DECL_RFK_WM(0x5638, 0x000ffc00, 0x09c),
380
	RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
381
	RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x3fb00000),
382
	RTW89_DECL_RFK_WM(0x5644, 0x000003ff, 0x02f),
383
	RTW89_DECL_RFK_WM(0x5644, 0x000ffc00, 0x09c),
384
};
385

386
RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_align_a_2g_defs);
387

388
static const struct rtw89_reg5_def rtw8851b_tssi_align_a_5g_defs[] = {
389
	RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
390
	RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x000000),
391
	RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x3b2d24),
392
	RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x00000000),
393
	RTW89_DECL_RFK_WM(0x5634, 0x000003ff, 0x000),
394
	RTW89_DECL_RFK_WM(0x5634, 0x000ffc00, 0x3cb),
395
	RTW89_DECL_RFK_WM(0x5634, 0x3ff00000, 0x030),
396
	RTW89_DECL_RFK_WM(0x5638, 0x000003ff, 0x73),
397
	RTW89_DECL_RFK_WM(0x5638, 0x000ffc00, 0xd4),
398
	RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
399
	RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
400
	RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
401
};
402

403
RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_align_a_5g_defs);
404

405
static const struct rtw89_reg5_def rtw8851b_tssi_slope_defs_a[] = {
406
	RTW89_DECL_RFK_WM(0x5820, 0x80000000, 0x0),
407
	RTW89_DECL_RFK_WM(0x5818, 0x10000000, 0x0),
408
	RTW89_DECL_RFK_WM(0x5814, 0x00000800, 0x1),
409
	RTW89_DECL_RFK_WM(0x581c, 0x20000000, 0x1),
410
	RTW89_DECL_RFK_WM(0x5820, 0x0000f000, 0xf),
411
	RTW89_DECL_RFK_WM(0x581c, 0x000003ff, 0x280),
412
	RTW89_DECL_RFK_WM(0x581c, 0x000ffc00, 0x200),
413
	RTW89_DECL_RFK_WM(0x58b8, 0x007f0000, 0x00),
414
	RTW89_DECL_RFK_WM(0x58b8, 0x7f000000, 0x00),
415
	RTW89_DECL_RFK_WM(0x58b4, 0x7f000000, 0x0a),
416
	RTW89_DECL_RFK_WM(0x58b8, 0x0000007f, 0x28),
417
	RTW89_DECL_RFK_WM(0x58b8, 0x00007f00, 0x76),
418
	RTW89_DECL_RFK_WM(0x5810, 0x20000000, 0x0),
419
	RTW89_DECL_RFK_WM(0x580c, 0x10000000, 0x1),
420
	RTW89_DECL_RFK_WM(0x580c, 0x40000000, 0x1),
421
	RTW89_DECL_RFK_WM(0x5834, 0x0003ffff, 0x115f2),
422
	RTW89_DECL_RFK_WM(0x5834, 0x3ffc0000, 0x000),
423
	RTW89_DECL_RFK_WM(0x5838, 0x00000fff, 0x121),
424
	RTW89_DECL_RFK_WM(0x5838, 0x003ff000, 0x000),
425
	RTW89_DECL_RFK_WM(0x5854, 0x0003ffff, 0x115f2),
426
	RTW89_DECL_RFK_WM(0x5854, 0x3ffc0000, 0x000),
427
	RTW89_DECL_RFK_WM(0x5858, 0x00000fff, 0x121),
428
	RTW89_DECL_RFK_WM(0x5858, 0x003ff000, 0x000),
429
	RTW89_DECL_RFK_WM(0x5824, 0x0003ffff, 0x115f2),
430
	RTW89_DECL_RFK_WM(0x5824, 0x3ffc0000, 0x000),
431
	RTW89_DECL_RFK_WM(0x5828, 0x00000fff, 0x121),
432
	RTW89_DECL_RFK_WM(0x5828, 0x003ff000, 0x000),
433
	RTW89_DECL_RFK_WM(0x582c, 0x0003ffff, 0x115f2),
434
	RTW89_DECL_RFK_WM(0x582c, 0x3ffc0000, 0x000),
435
	RTW89_DECL_RFK_WM(0x5830, 0x00000fff, 0x121),
436
	RTW89_DECL_RFK_WM(0x5830, 0x003ff000, 0x000),
437
	RTW89_DECL_RFK_WM(0x583c, 0x0003ffff, 0x115f2),
438
	RTW89_DECL_RFK_WM(0x583c, 0x3ffc0000, 0x000),
439
	RTW89_DECL_RFK_WM(0x5840, 0x00000fff, 0x121),
440
	RTW89_DECL_RFK_WM(0x5840, 0x003ff000, 0x000),
441
	RTW89_DECL_RFK_WM(0x5844, 0x0003ffff, 0x115f2),
442
	RTW89_DECL_RFK_WM(0x5844, 0x3ffc0000, 0x000),
443
	RTW89_DECL_RFK_WM(0x5848, 0x00000fff, 0x121),
444
	RTW89_DECL_RFK_WM(0x5848, 0x003ff000, 0x000),
445
	RTW89_DECL_RFK_WM(0x584c, 0x0003ffff, 0x115f2),
446
	RTW89_DECL_RFK_WM(0x584c, 0x3ffc0000, 0x000),
447
	RTW89_DECL_RFK_WM(0x5850, 0x00000fff, 0x121),
448
	RTW89_DECL_RFK_WM(0x5850, 0x003ff000, 0x000),
449
	RTW89_DECL_RFK_WM(0x585c, 0x0003ffff, 0x115f2),
450
	RTW89_DECL_RFK_WM(0x585c, 0x3ffc0000, 0x000),
451
	RTW89_DECL_RFK_WM(0x5860, 0x00000fff, 0x121),
452
	RTW89_DECL_RFK_WM(0x5860, 0x003ff000, 0x000),
453
};
454

455
RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_slope_defs_a);
456

457
static const struct rtw89_reg5_def rtw8851b_tssi_track_defs_a[] = {
458
	RTW89_DECL_RFK_WM(0x5820, 0x80000000, 0x0),
459
	RTW89_DECL_RFK_WM(0x5818, 0x10000000, 0x0),
460
	RTW89_DECL_RFK_WM(0x5814, 0x00000800, 0x0),
461
	RTW89_DECL_RFK_WM(0x581c, 0x20000000, 0x1),
462
	RTW89_DECL_RFK_WM(0x5864, 0x000003ff, 0x1ff),
463
	RTW89_DECL_RFK_WM(0x5864, 0x000ffc00, 0x200),
464
	RTW89_DECL_RFK_WM(0x5820, 0x00000fff, 0x080),
465
	RTW89_DECL_RFK_WM(0x5814, 0x01000000, 0x0),
466
};
467

468
RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_track_defs_a);
469

470
static const struct rtw89_reg5_def rtw8851b_tssi_mv_avg_defs_a[] = {
471
	RTW89_DECL_RFK_WM(0x58e4, 0x00003800, 0x1),
472
	RTW89_DECL_RFK_WM(0x58e4, 0x00004000, 0x0),
473
	RTW89_DECL_RFK_WM(0x58e4, 0x00008000, 0x1),
474
	RTW89_DECL_RFK_WM(0x58e4, 0x000f0000, 0x0),
475
};
476

477
RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_mv_avg_defs_a);
478

479
static const struct rtw89_reg5_def rtw8851b_nctl_post_defs[] = {
480
	RTW89_DECL_RFK_WM(0x5864, 0x18000000, 0x3),
481
	RTW89_DECL_RFK_WM(0x7864, 0x18000000, 0x3),
482
	RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x13),
483
	RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041),
484
	RTW89_DECL_RFK_WM(0x12b8, 0x10000000, 0x1),
485
	RTW89_DECL_RFK_WM(0x2008, 0x01ffffff, 0x00fffff),
486
	RTW89_DECL_RFK_WM(0x0c60, 0x00000003, 0x3),
487
	RTW89_DECL_RFK_WM(0x0c6c, 0x00000001, 0x1),
488
	RTW89_DECL_RFK_WM(0x58ac, 0x08000000, 0x1),
489
	RTW89_DECL_RFK_WM(0x78ac, 0x08000000, 0x1),
490
	RTW89_DECL_RFK_WM(0x0730, 0x00003800, 0x7),
491
	RTW89_DECL_RFK_WM(0x2730, 0x00003800, 0x7),
492
	RTW89_DECL_RFK_WM(0x0c7c, 0x00e00000, 0x1),
493
	RTW89_DECL_RFK_WM(0x58c0, 0x0001ffff, 0x00000),
494
	RTW89_DECL_RFK_WM(0x78c0, 0x0001ffff, 0x00000),
495
	RTW89_DECL_RFK_WM(0x58fc, 0x3f000000, 0x00),
496
	RTW89_DECL_RFK_WM(0x78fc, 0x3f000000, 0x00),
497
};
498

499
RTW89_DECLARE_RFK_TBL(rtw8851b_nctl_post_defs);
500

501
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