Path: blob/main/sys/contrib/device-tree/Bindings/ata/rockchip,dwc-ahci.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Synopsys DWC AHCI SATA controller for Rockchip devices78maintainers:9- Serge Semin <fancer.lancer@gmail.com>1011description:12This document defines device tree bindings for the Synopsys DWC13implementation of the AHCI SATA controller found in Rockchip14devices.1516select:17properties:18compatible:19contains:20enum:21- rockchip,rk3568-dwc-ahci22- rockchip,rk3588-dwc-ahci23required:24- compatible2526properties:27compatible:28items:29- enum:30- rockchip,rk3568-dwc-ahci31- rockchip,rk3588-dwc-ahci32- const: snps,dwc-ahci3334ports-implemented:35const: 13637power-domains:38maxItems: 13940sata-port@0:41$ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port4243properties:44reg:45const: 04647unevaluatedProperties: false4849patternProperties:50"^sata-port@[1-9a-e]$": false5152required:53- compatible54- reg55- interrupts56- clocks57- clock-names58- ports-implemented5960allOf:61- $ref: snps,dwc-ahci-common.yaml#62- if:63properties:64compatible:65contains:66enum:67- rockchip,rk3588-dwc-ahci68then:69properties:70clocks:71maxItems: 572clock-names:73items:74- const: sata75- const: pmalive76- const: rxoob77- const: ref78- const: asic79- if:80properties:81compatible:82contains:83enum:84- rockchip,rk3568-dwc-ahci85then:86properties:87clocks:88maxItems: 389clock-names:90items:91- const: sata92- const: pmalive93- const: rxoob9495unevaluatedProperties: false9697examples:98- |99#include <dt-bindings/clock/rockchip,rk3588-cru.h>100#include <dt-bindings/interrupt-controller/arm-gic.h>101#include <dt-bindings/ata/ahci.h>102#include <dt-bindings/phy/phy.h>103104sata@fe210000 {105compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";106reg = <0xfe210000 0x1000>;107clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,108<&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,109<&cru CLK_PIPEPHY0_PIPE_ASIC_G>;110clock-names = "sata", "pmalive", "rxoob", "ref", "asic";111interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;112ports-implemented = <0x1>;113#address-cells = <1>;114#size-cells = <0>;115116sata-port@0 {117reg = <0>;118hba-port-cap = <HBA_PORT_FBSCP>;119phys = <&combphy0_ps PHY_TYPE_SATA>;120phy-names = "sata-phy";121snps,rx-ts-max = <32>;122snps,tx-ts-max = <32>;123};124};125126...127128129