Path: blob/main/sys/contrib/device-tree/Bindings/crypto/atmel,at91sam9g46-aes.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries2%YAML 1.23---4$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-aes.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#67title: Atmel Advanced Encryption Standard (AES) HW cryptographic accelerator89maintainers:10- Tudor Ambarus <tudor.ambarus@linaro.org>1112properties:13compatible:14oneOf:15- const: atmel,at91sam9g46-aes16- items:17- const: microchip,sam9x7-aes18- const: atmel,at91sam9g46-aes1920reg:21maxItems: 12223interrupts:24maxItems: 12526clocks:27maxItems: 12829clock-names:30const: aes_clk3132dmas:33items:34- description: TX DMA Channel35- description: RX DMA Channel3637dma-names:38items:39- const: tx40- const: rx4142required:43- compatible44- reg45- interrupts46- clocks47- clock-names48- dmas49- dma-names5051additionalProperties: false5253examples:54- |55#include <dt-bindings/interrupt-controller/irq.h>56#include <dt-bindings/interrupt-controller/arm-gic.h>57#include <dt-bindings/clock/at91.h>58#include <dt-bindings/dma/at91.h>5960aes: crypto@e1810000 {61compatible = "atmel,at91sam9g46-aes";62reg = <0xe1810000 0x100>;63interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;64clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;65clock-names = "aes_clk";66dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,67<&dma0 AT91_XDMAC_DT_PERID(2)>;68dma-names = "tx", "rx";69};707172