Path: blob/main/sys/contrib/device-tree/Bindings/crypto/atmel,at91sam9g46-sha.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries2%YAML 1.23---4$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-sha.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#67title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator89maintainers:10- Tudor Ambarus <tudor.ambarus@linaro.org>1112properties:13compatible:14oneOf:15- const: atmel,at91sam9g46-sha16- items:17- const: microchip,sam9x7-sha18- const: atmel,at91sam9g46-sha1920reg:21maxItems: 12223interrupts:24maxItems: 12526clocks:27maxItems: 12829clock-names:30const: sha_clk3132dmas:33maxItems: 134description: TX DMA Channel3536dma-names:37const: tx3839required:40- compatible41- reg42- interrupts43- clocks44- clock-names4546additionalProperties: false4748examples:49- |50#include <dt-bindings/interrupt-controller/irq.h>51#include <dt-bindings/interrupt-controller/arm-gic.h>52#include <dt-bindings/clock/at91.h>53#include <dt-bindings/dma/at91.h>5455sha: crypto@e1814000 {56compatible = "atmel,at91sam9g46-sha";57reg = <0xe1814000 0x100>;58interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;59clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;60clock-names = "sha_clk";61dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;62dma-names = "tx";63};646566