Path: blob/main/sys/contrib/device-tree/Bindings/crypto/fsl-sec6.txt
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SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).1Currently Freescale powerpc chip C29X is embedded with SEC 6.2SEC 6 device tree binding include:3-SEC 6 Node4-Job Ring Node5-Full Example67=====================================================================8SEC 6 Node910Description1112Node defines the base address of the SEC 6 block.13This block specifies the address range of all global14configuration registers for the SEC 6 block.15For example, In C293, we could see three SEC 6 node.1617PROPERTIES1819- compatible20Usage: required21Value type: <string>22Definition: Must include "fsl,sec-v6.0".2324- fsl,sec-era25Usage: optional26Value type: <u32>27Definition: A standard property. Define the 'ERA' of the SEC28device.2930- #address-cells31Usage: required32Value type: <u32>33Definition: A standard property. Defines the number of cells34for representing physical addresses in child nodes.3536- #size-cells37Usage: required38Value type: <u32>39Definition: A standard property. Defines the number of cells40for representing the size of physical addresses in41child nodes.4243- reg44Usage: required45Value type: <prop-encoded-array>46Definition: A standard property. Specifies the physical47address and length of the SEC 6 configuration registers.4849- ranges50Usage: required51Value type: <prop-encoded-array>52Definition: A standard property. Specifies the physical address53range of the SEC 6.0 register space (-SNVS not included). A54triplet that includes the child address, parent address, &55length.5657Note: All other standard properties (see the Devicetree Specification)58are allowed but are optional.5960EXAMPLE61crypto@a0000 {62compatible = "fsl,sec-v6.0";63fsl,sec-era = <6>;64#address-cells = <1>;65#size-cells = <1>;66reg = <0xa0000 0x20000>;67ranges = <0 0xa0000 0x20000>;68};6970=====================================================================71Job Ring (JR) Node7273Child of the crypto node defines data processing interface to SEC 674across the peripheral bus for purposes of processing75cryptographic descriptors. The specified address76range can be made visible to one (or more) cores.77The interrupt defined for this node is controlled within78the address range of this node.7980- compatible81Usage: required82Value type: <string>83Definition: Must include "fsl,sec-v6.0-job-ring".8485- reg86Usage: required87Value type: <prop-encoded-array>88Definition: Specifies a two JR parameters: an offset from89the parent physical address and the length the JR registers.9091- interrupts92Usage: required93Value type: <prop_encoded-array>94Definition: Specifies the interrupts generated by this95device. The value of the interrupts property96consists of one interrupt specifier. The format97of the specifier is defined by the binding document98describing the node's interrupt parent.99100EXAMPLE101jr@1000 {102compatible = "fsl,sec-v6.0-job-ring";103reg = <0x1000 0x1000>;104interrupts = <49 2 0 0>;105};106107===================================================================108Full Example109110Since some chips may contain more than one SEC, the dtsi contains111only the node contents, not the node itself. A chip using the SEC112should include the dtsi inside each SEC node. Example:113114In qoriq-sec6.0.dtsi:115116compatible = "fsl,sec-v6.0";117fsl,sec-era = <6>;118#address-cells = <1>;119#size-cells = <1>;120121jr@1000 {122compatible = "fsl,sec-v6.0-job-ring",123"fsl,sec-v5.2-job-ring",124"fsl,sec-v5.0-job-ring",125"fsl,sec-v4.4-job-ring",126"fsl,sec-v4.0-job-ring";127reg = <0x1000 0x1000>;128};129130jr@2000 {131compatible = "fsl,sec-v6.0-job-ring",132"fsl,sec-v5.2-job-ring",133"fsl,sec-v5.0-job-ring",134"fsl,sec-v4.4-job-ring",135"fsl,sec-v4.0-job-ring";136reg = <0x2000 0x1000>;137};138139In the C293 device tree, we add the include of public property:140141crypto@a0000 {142/include/ "qoriq-sec6.0.dtsi"143}144145crypto@a0000 {146reg = <0xa0000 0x20000>;147ranges = <0 0xa0000 0x20000>;148149jr@1000 {150interrupts = <49 2 0 0>;151};152153jr@2000 {154interrupts = <50 2 0 0>;155};156};157158159