Path: blob/main/sys/contrib/device-tree/Bindings/crypto/inside-secure-safexcel.txt
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Inside Secure SafeXcel cryptographic engine12Required properties:3- compatible: Should be "inside-secure,safexcel-eip197b",4"inside-secure,safexcel-eip197d" or5"inside-secure,safexcel-eip97ies".6- reg: Base physical address of the engine and length of memory mapped region.7- interrupts: Interrupt numbers for the rings and engine.8- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".910Optional properties:11- clocks: Reference to the crypto engine clocks, the second clock is12needed for the Armada 7K/8K SoCs.13- clock-names: mandatory if there is a second clock, in this case the14name must be "core" for the first clock and "reg" for15the second one.1617Backward compatibility:18Two compatibles are kept for backward compatibility, but shouldn't be used for19new submissions:20- "inside-secure,safexcel-eip197" is equivalent to21"inside-secure,safexcel-eip197b".22- "inside-secure,safexcel-eip97" is equivalent to23"inside-secure,safexcel-eip97ies".2425Example:2627crypto: crypto@800000 {28compatible = "inside-secure,safexcel-eip197b";29reg = <0x800000 0x200000>;30interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,31<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,32<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,33<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,34<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,35<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;36interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",37"eip";38clocks = <&cpm_syscon0 1 26>;39};404142