Path: blob/main/sys/contrib/device-tree/Bindings/display/bridge/cdns,dsi.txt
48403 views
Cadence DSI bridge1==================23The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.45Required properties:6- compatible: should be set to "cdns,dsi".7- reg: physical base address and length of the controller's registers.8- interrupts: interrupt line connected to the DSI bridge.9- clocks: DSI bridge clocks.10- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".11- phys: phandle link to the MIPI D-PHY controller.12- phy-names: must contain "dphy".13- #address-cells: must be set to 1.14- #size-cells: must be set to 0.1516Optional properties:17- resets: DSI reset lines.18- reset-names: can contain "dsi_p_rst".1920Required subnodes:21- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.222 ports are available:23* port 0: this port is only needed if some of your DSI devices are24controlled through an external bus like I2C or SPI. Can have at25most 4 endpoints. The endpoint number is directly encoding the26DSI virtual channel used by this device.27* port 1: represents the DPI input.28Other ports will be added later to support the new kind of inputs.2930- one subnode per DSI device connected on the DSI bus. Each DSI device should31contain a reg property encoding its virtual channel.3233Example:34dsi0: dsi@fd0c0000 {35compatible = "cdns,dsi";36reg = <0x0 0xfd0c0000 0x0 0x1000>;37clocks = <&pclk>, <&sysclk>;38clock-names = "dsi_p_clk", "dsi_sys_clk";39interrupts = <1>;40phys = <&dphy0>;41phy-names = "dphy";42#address-cells = <1>;43#size-cells = <0>;4445ports {46#address-cells = <1>;47#size-cells = <0>;4849port@1 {50reg = <1>;51dsi0_dpi_input: endpoint {52remote-endpoint = <&xxx_dpi_output>;53};54};55};5657panel: dsi-dev@0 {58compatible = "<vendor,panel>";59reg = <0>;60};61};6263or6465dsi0: dsi@fd0c0000 {66compatible = "cdns,dsi";67reg = <0x0 0xfd0c0000 0x0 0x1000>;68clocks = <&pclk>, <&sysclk>;69clock-names = "dsi_p_clk", "dsi_sys_clk";70interrupts = <1>;71phys = <&dphy1>;72phy-names = "dphy";73#address-cells = <1>;74#size-cells = <0>;7576ports {77#address-cells = <1>;78#size-cells = <0>;7980port@0 {81reg = <0>;82#address-cells = <1>;83#size-cells = <0>;8485dsi0_output: endpoint@0 {86reg = <0>;87remote-endpoint = <&dsi_panel_input>;88};89};9091port@1 {92reg = <1>;93dsi0_dpi_input: endpoint {94remote-endpoint = <&xxx_dpi_output>;95};96};97};98};99100i2c@xxx {101panel: panel@59 {102compatible = "<vendor,panel>";103reg = <0x59>;104105port {106dsi_panel_input: endpoint {107remote-endpoint = <&dsi0_output>;108};109};110};111};112113114