Path: blob/main/sys/contrib/device-tree/Bindings/display/bridge/renesas,lvds.txt
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Renesas R-Car LVDS Encoder1==========================23These DT bindings describe the LVDS encoder embedded in the Renesas R-Car4Gen2, R-Car Gen3 and RZ/G SoCs.56Required properties:78- compatible : Shall contain one of9- "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders10- "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders11- "renesas,r8a774a1-lvds" for R8A774A1 (RZ/G2M) compatible LVDS encoders12- "renesas,r8a774b1-lvds" for R8A774B1 (RZ/G2N) compatible LVDS encoders13- "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders14- "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders15- "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders16- "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders17- "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders18- "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders19- "renesas,r8a77965-lvds" for R8A77965 (R-Car M3-N) compatible LVDS encoders20- "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders21- "renesas,r8a77980-lvds" for R8A77980 (R-Car V3H) compatible LVDS encoders22- "renesas,r8a77990-lvds" for R8A77990 (R-Car E3) compatible LVDS encoders23- "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders2425- reg: Base address and length for the memory-mapped registers26- clocks: A list of phandles + clock-specifier pairs, one for each entry in27the clock-names property.28- clock-names: Name of the clocks. This property is model-dependent.29- The functional clock, which mandatory for all models, shall be listed30first, and shall be named "fck".31- On R8A77990, R8A77995 and R8A774C0, the LVDS encoder can use the EXTAL or32DU_DOTCLKINx clocks. Those clocks are optional. When supplied they must be33named "extal" and "dclkin.x" respectively, with "x" being the DU_DOTCLKIN34numerical index.35- When the clocks property only contains the functional clock, the36clock-names property may be omitted.37- resets: A phandle + reset specifier for the module reset3839Required nodes:4041The LVDS encoder has two video ports. Their connections are modelled using the42OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.4344- Video port 0 corresponds to the parallel RGB input45- Video port 1 corresponds to the LVDS output4647Each port shall have a single endpoint.4849Optional properties:5051- renesas,companion : phandle to the companion LVDS encoder. This property is52mandatory for the first LVDS encoder on D3 and E3 SoCs, and shall point to53the second encoder to be used as a companion in dual-link mode. It shall not54be set for any other LVDS encoder.555657Example:5859lvds0: lvds@feb90000 {60compatible = "renesas,r8a77990-lvds";61reg = <0 0xfeb90000 0 0x20>;62clocks = <&cpg CPG_MOD 727>;63power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;64resets = <&cpg 727>;6566renesas,companion = <&lvds1>;6768ports {69#address-cells = <1>;70#size-cells = <0>;7172port@0 {73reg = <0>;74lvds0_in: endpoint {75remote-endpoint = <&du_out_lvds0>;76};77};78port@1 {79reg = <1>;80lvds0_out: endpoint {81};82};83};84};858687