Path: blob/main/sys/contrib/device-tree/Bindings/display/exynos/exynos5433-decon.txt
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Device-Tree bindings for Samsung Exynos SoC display controller (DECON)12DECON (Display and Enhancement Controller) is the Display Controller for the3Exynos series of SoCs which transfers the image data from a video memory4buffer to an external LCD interface.56Required properties:7- compatible: value should be one of:8"samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";9- reg: physical base address and length of the DECON registers set.10- interrupt-names: should contain the interrupt names depending on mode of work:11video mode: "vsync",12command mode: "lcd_sys",13command mode with software trigger: "lcd_sys", "te".14- interrupts or interrupts-extended: list of interrupt specifiers corresponding15to names privided in interrupt-names, as described in16interrupt-controller/interrupts.txt17- clocks: must include clock specifiers corresponding to entries in the18clock-names property.19- clock-names: list of clock names sorted in the same order as the clocks20property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",21"aclk_xiu_decon0x", "pclk_smmu_decon0x", "aclk_smmu_decon1x",22"aclk_xiu_decon1x", "pclk_smmu_decon1x", clk_decon_vclk",23"sclk_decon_eclk"24- ports: contains a port which is connected to mic node. address-cells and25size-cells must 1 and 0, respectively.26- port: contains an endpoint node which is connected to the endpoint in the mic27node. The reg value muset be 0.2829Example:30SoC specific DT entry:31decon: decon@13800000 {32compatible = "samsung,exynos5433-decon";33reg = <0x13800000 0x2104>;34clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>,35<&cmu_disp CLK_ACLK_XIU_DECON0X>,36<&cmu_disp CLK_PCLK_SMMU_DECON0X>,37<&cmu_disp CLK_ACLK_SMMU_DECON1X>,38<&cmu_disp CLK_ACLK_XIU_DECON1X>,39<&cmu_disp CLK_PCLK_SMMU_DECON1X>,40<&cmu_disp CLK_SCLK_DECON_VCLK>,41<&cmu_disp CLK_SCLK_DECON_ECLK>;42clock-names = "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x",43"pclk_smmu_decon0x", "aclk_smmu_decon1x", "aclk_xiu_decon1x",44"pclk_smmu_decon1x", "sclk_decon_vclk", "sclk_decon_eclk";45interrupt-names = "vsync", "lcd_sys";46interrupts = <0 202 0>, <0 203 0>;4748ports {49#address-cells = <1>;50#size-cells = <0>;5152port@0 {53reg = <0>;54decon_to_mic: endpoint {55remote-endpoint = <&mic_to_decon>;56};57};58};59};606162