Path: blob/main/sys/contrib/device-tree/Bindings/dma/fsl-qdma.txt
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NXP Layerscape SoC qDMA Controller1==================================23This device follows the generic DMA bindings defined in dma/dma.txt.45Required properties:67- compatible: Must be one of8"fsl,ls1021a-qdma": for LS1021A Board9"fsl,ls1028a-qdma": for LS1028A Board10"fsl,ls1043a-qdma": for ls1043A Board11"fsl,ls1046a-qdma": for ls1046A Board12- reg: Should contain the register's base address and length.13- interrupts: Should contain a reference to the interrupt used by this14device.15- interrupt-names: Should contain interrupt names:16"qdma-queue0": the block0 interrupt17"qdma-queue1": the block1 interrupt18"qdma-queue2": the block2 interrupt19"qdma-queue3": the block3 interrupt20"qdma-error": the error interrupt21- fsl,dma-queues: Should contain number of queues supported.22- dma-channels: Number of DMA channels supported23- block-number: the virtual block number24- block-offset: the offset of different virtual block25- status-sizes: status queue size of per virtual block26- queue-sizes: command queue size of per virtual block, the size number27based on queues2829Optional properties:3031- dma-channels: Number of DMA channels supported by the controller.32- big-endian: If present registers and hardware scatter/gather descriptors33of the qDMA are implemented in big endian mode, otherwise in little34mode.3536Examples:3738qdma: dma-controller@8390000 {39compatible = "fsl,ls1021a-qdma";40reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */41<0x0 0x8389000 0x0 0x1000>, /* Status regs */42<0x0 0x838a000 0x0 0x2000>; /* Block regs */43interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,44<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,45<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;46interrupt-names = "qdma-error",47"qdma-queue0", "qdma-queue1";48dma-channels = <8>;49block-number = <2>;50block-offset = <0x1000>;51fsl,dma-queues = <2>;52status-sizes = <64>;53queue-sizes = <64 64>;54big-endian;55};5657DMA clients must use the format described in dma/dma.txt file.585960