Path: blob/main/sys/contrib/device-tree/Bindings/firmware/fsl,scu.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: NXP i.MX System Controller Firmware (SCFW)78maintainers:9- Dong Aisheng <aisheng.dong@nxp.com>1011description:12The System Controller Firmware (SCFW) is a low-level system function13which runs on a dedicated Cortex-M core to provide power, clock, and14resource management. It exists on some i.MX8 processors. e.g. i.MX8QM15(QM, QP), and i.MX8QX (QXP, DX).16The AP communicates with the SC using a multi-ported MU module found17in the LSIO subsystem. The current definition of this MU module provides185 remote AP connections to the SC to support up to 5 execution environments19(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces20with the LSIO DSC IP bus. The SC firmware will communicate with this MU21using the MSI bus.2223properties:24compatible:25const: fsl,imx-scu2627clock-controller:28description:29Clock controller node that provides the clocks controlled by the SCU30$ref: /schemas/clock/fsl,scu-clk.yaml3132gpio:33description:34Control the GPIO PINs on SCU domain over the firmware APIs35$ref: /schemas/gpio/fsl,imx8qxp-sc-gpio.yaml3637ocotp:38description:39OCOTP controller node provided by the SCU40$ref: /schemas/nvmem/fsl,scu-ocotp.yaml4142keys:43description:44Keys provided by the SCU45$ref: /schemas/input/fsl,scu-key.yaml4647mboxes:48description:49A list of phandles of TX MU channels followed by a list of phandles of50RX MU channels. The list may include at the end one more optional MU51channel for general interrupt. The number of expected tx and rx52channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu"53compatible, 4 TX and 4 RX channels otherwise. All MU channels must be54within the same MU instance. Cross instances are not allowed. The MU55instance can only be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users56need to ensure that one is used that does not conflict with other57execution environments such as ATF.58oneOf:59- items:60- description: TX0 MU channel61- description: RX0 MU channel62- items:63- description: TX0 MU channel64- description: RX0 MU channel65- description: optional MU channel for general interrupt66- items:67- description: TX0 MU channel68- description: TX1 MU channel69- description: TX2 MU channel70- description: TX3 MU channel71- description: RX0 MU channel72- description: RX1 MU channel73- description: RX2 MU channel74- description: RX3 MU channel75- items:76- description: TX0 MU channel77- description: TX1 MU channel78- description: TX2 MU channel79- description: TX3 MU channel80- description: RX0 MU channel81- description: RX1 MU channel82- description: RX2 MU channel83- description: RX3 MU channel84- description: optional MU channel for general interrupt8586mbox-names:87oneOf:88- items:89- const: tx090- const: rx091- items:92- const: tx093- const: rx094- const: gip395- items:96- const: tx097- const: tx198- const: tx299- const: tx3100- const: rx0101- const: rx1102- const: rx2103- const: rx3104- items:105- const: tx0106- const: tx1107- const: tx2108- const: tx3109- const: rx0110- const: rx1111- const: rx2112- const: rx3113- const: gip3114115pinctrl:116description:117Pin controller provided by the SCU118$ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml119120power-controller:121description:122Power domains controller node that provides the power domains123controlled by the SCU124$ref: /schemas/power/fsl,scu-pd.yaml125126rtc:127description:128RTC controller provided by the SCU129$ref: /schemas/rtc/fsl,scu-rtc.yaml130131thermal-sensor:132description:133Thermal sensor provided by the SCU134$ref: /schemas/thermal/fsl,scu-thermal.yaml135136watchdog:137description:138Watchdog controller provided by the SCU139$ref: /schemas/watchdog/fsl,scu-wdt.yaml140141required:142- compatible143- mbox-names144- mboxes145146additionalProperties: false147148examples:149- |150#include <dt-bindings/firmware/imx/rsrc.h>151#include <dt-bindings/input/input.h>152#include <dt-bindings/pinctrl/pads-imx8qxp.h>153154firmware {155system-controller {156compatible = "fsl,imx-scu";157mbox-names = "tx0", "tx1", "tx2", "tx3",158"rx0", "rx1", "rx2", "rx3",159"gip3";160mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3161&lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3162&lsio_mu1 3 3>;163164clock-controller {165compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";166#clock-cells = <2>;167};168169pinctrl {170compatible = "fsl,imx8qxp-iomuxc";171172pinctrl_lpuart0: lpuart0grp {173fsl,pins = <174IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020175IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020176>;177};178};179180ocotp {181compatible = "fsl,imx8qxp-scu-ocotp";182#address-cells = <1>;183#size-cells = <1>;184185fec_mac0: mac@2c4 {186reg = <0x2c4 6>;187};188};189190power-controller {191compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";192#power-domain-cells = <1>;193};194195rtc {196compatible = "fsl,imx8qxp-sc-rtc";197};198199keys {200compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";201linux,keycodes = <KEY_POWER>;202};203204watchdog {205compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";206timeout-sec = <60>;207};208209thermal-sensor {210compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";211#thermal-sensor-cells = <1>;212};213};214};215216217