Path: blob/main/sys/contrib/device-tree/Bindings/firmware/intel,stratix10-svc.txt
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Intel Service Layer Driver for Stratix10 SoC1============================================2Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard3processor system (HPS) and Secure Device Manager (SDM). When the FPGA is4configured from HPS, there needs to be a way for HPS to notify SDM the5location and size of the configuration data. Then SDM will get the6configuration data from that location and perform the FPGA configuration.78To meet the whole system security needs and support virtual machine requesting9communication with SDM, only the secure world of software (EL3, Exception10Layer 3) can interface with SDM. All software entities running on other11exception layers must channel through the EL3 software whenever it needs12service from SDM.1314Intel Stratix10 service layer driver, running at privileged exception level15(EL1, Exception Layer 1), interfaces with the service providers and provides16the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer17driver also manages secure monitor call (SMC) to communicate with secure monitor18code running in EL3.1920Required properties:21-------------------22The svc node has the following mandatory properties, must be located under23the firmware node.2425- compatible: "intel,stratix10-svc" or "intel,agilex-svc"26- method: smc or hvc27smc - Secure Monitor Call28hvc - Hypervisor Call29- memory-region:30phandle to the reserved memory node. See31Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt32for details3334Example:35-------3637reserved-memory {38#address-cells = <2>;39#size-cells = <2>;40ranges;4142service_reserved: svcbuffer@0 {43compatible = "shared-dma-pool";44reg = <0x0 0x0 0x0 0x1000000>;45alignment = <0x1000>;46no-map;47};48};4950firmware {51svc {52compatible = "intel,stratix10-svc";53method = "smc";54memory-region = <&service_reserved>;55};56};575859