Path: blob/main/sys/contrib/device-tree/Bindings/fpga/xilinx-pr-decoupler.txt
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Xilinx LogiCORE Partial Reconfig Decoupler Softcore12The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more3decouplers / fpga bridges.4The controller can decouple/disable the bridges which prevents signal5changes from passing through the bridge. The controller can also6couple / enable the bridges which allows traffic to pass through the7bridge normally.89Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager10Softcore is compatible with the Xilinx LogiCORE pr-decoupler.1112The Dynamic Function eXchange AXI shutdown manager prevents AXI traffic13from passing through the bridge. The controller safely handles AXI4MM14and AXI4-Lite interfaces on a Reconfigurable Partition when it is15undergoing dynamic reconfiguration, preventing the system deadlock16that can occur if AXI transactions are interrupted by DFX1718The Driver supports only MMIO handling. A PR region can have multiple19PR Decouplers which can be handled independently or chained via decouple/20decouple_status signals.2122Required properties:23- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by24"xlnx,pr-decoupler" or25"xlnx,dfx-axi-shutdown-manager-1.00" followed by26"xlnx,dfx-axi-shutdown-manager"27- regs : base address and size for decoupler module28- clocks : input clock to IP29- clock-names : should contain "aclk"3031See Documentation/devicetree/bindings/fpga/fpga-region.txt and32Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.3334Example:35Partial Reconfig Decoupler:36fpga-bridge@100000450 {37compatible = "xlnx,pr-decoupler-1.00",38"xlnx-pr-decoupler";39regs = <0x10000045 0x10>;40clocks = <&clkc 15>;41clock-names = "aclk";42bridge-enable = <0>;43};4445Dynamic Function eXchange AXI shutdown manager:46fpga-bridge@100000450 {47compatible = "xlnx,dfx-axi-shutdown-manager-1.00",48"xlnx,dfx-axi-shutdown-manager";49regs = <0x10000045 0x10>;50clocks = <&clkc 15>;51clock-names = "aclk";52bridge-enable = <0>;53};545556