Path: blob/main/sys/contrib/device-tree/Bindings/gpio/fsl,qoriq-gpio.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)1%YAML 1.22---3$id: http://devicetree.org/schemas/gpio/fsl,qoriq-gpio.yaml#4$schema: http://devicetree.org/meta-schemas/core.yaml#56title: Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller78maintainers:9- Frank Li <Frank.Li@nxp.com>1011properties:12compatible:13oneOf:14- enum:15- fsl,mpc5121-gpio16- fsl,mpc5125-gpio17- fsl,mpc8349-gpio18- fsl,mpc8572-gpio19- fsl,mpc8610-gpio20- fsl,pq3-gpio21- items:22- enum:23- fsl,ls1021a-gpio24- fsl,ls1028a-gpio25- fsl,ls1043a-gpio26- fsl,ls1046a-gpio27- fsl,ls1088a-gpio28- fsl,ls2080a-gpio29- const: fsl,qoriq-gpio3031reg:32maxItems: 13334interrupts:35maxItems: 13637"#gpio-cells":38const: 23940gpio-controller: true4142interrupt-controller: true4344"#interrupt-cells":45const: 24647gpio-line-names:48minItems: 149maxItems: 325051little-endian:52$ref: /schemas/types.yaml#/definitions/flag53description:54GPIO registers are used as little endian. If not55present registers are used as big endian by default.5657required:58- compatible59- reg60- interrupts61- "#gpio-cells"6263additionalProperties: false6465examples:66- |67gpio@1100 {68compatible = "fsl,mpc5125-gpio";69reg = <0x1100 0x080>;70interrupts = <78 0x8>;71gpio-controller;72#gpio-cells = <2>;73};7475- |76#include <dt-bindings/interrupt-controller/arm-gic.h>77gpio@2300000 {78compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";79reg = <0x2300000 0x10000>;80interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;81little-endian;82gpio-controller;83#gpio-cells = <2>;84interrupt-controller;85#interrupt-cells = <2>;86};878889