CoCalc -- axg-clkc.h

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/contrib/device-tree/include/dt-bindings/clock/axg-clkc.h
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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 * Meson-AXG clock tree IDs
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 *
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 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
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 */
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#ifndef __AXG_CLKC_H
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#define __AXG_CLKC_H
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#define CLKID_SYS_PLL				0
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#define CLKID_FIXED_PLL				1
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#define CLKID_FCLK_DIV2				2
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#define CLKID_FCLK_DIV3				3
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#define CLKID_FCLK_DIV4				4
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#define CLKID_FCLK_DIV5				5
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#define CLKID_FCLK_DIV7				6
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#define CLKID_GP0_PLL				7
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#define CLKID_MPEG_SEL				8
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#define CLKID_MPEG_DIV				9
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#define CLKID_CLK81				10
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#define CLKID_MPLL0				11
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#define CLKID_MPLL1				12
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#define CLKID_MPLL2				13
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#define CLKID_MPLL3				14
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#define CLKID_DDR				15
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#define CLKID_AUDIO_LOCKER			16
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#define CLKID_MIPI_DSI_HOST			17
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#define CLKID_ISA				18
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#define CLKID_PL301				19
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#define CLKID_PERIPHS				20
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#define CLKID_SPICC0				21
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#define CLKID_I2C				22
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#define CLKID_RNG0				23
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#define CLKID_UART0				24
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#define CLKID_MIPI_DSI_PHY			25
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#define CLKID_SPICC1				26
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#define CLKID_PCIE_A				27
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#define CLKID_PCIE_B				28
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#define CLKID_HIU_IFACE				29
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#define CLKID_ASSIST_MISC			30
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#define CLKID_SD_EMMC_B				31
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#define CLKID_SD_EMMC_C				32
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#define CLKID_DMA				33
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#define CLKID_SPI				34
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#define CLKID_AUDIO				35
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#define CLKID_ETH				36
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#define CLKID_UART1				37
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#define CLKID_G2D				38
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#define CLKID_USB0				39
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#define CLKID_USB1				40
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#define CLKID_RESET				41
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#define CLKID_USB				42
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#define CLKID_AHB_ARB0				43
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#define CLKID_EFUSE				44
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#define CLKID_BOOT_ROM				45
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#define CLKID_AHB_DATA_BUS			46
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#define CLKID_AHB_CTRL_BUS			47
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#define CLKID_USB1_DDR_BRIDGE			48
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#define CLKID_USB0_DDR_BRIDGE			49
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#define CLKID_MMC_PCLK				50
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#define CLKID_VPU_INTR				51
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#define CLKID_SEC_AHB_AHB3_BRIDGE		52
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#define CLKID_GIC				53
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#define CLKID_AO_MEDIA_CPU			54
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#define CLKID_AO_AHB_SRAM			55
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#define CLKID_AO_AHB_BUS			56
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#define CLKID_AO_IFACE				57
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#define CLKID_AO_I2C				58
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#define CLKID_SD_EMMC_B_CLK0			59
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#define CLKID_SD_EMMC_C_CLK0			60
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#define CLKID_SD_EMMC_B_CLK0_SEL		61
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#define CLKID_SD_EMMC_B_CLK0_DIV		62
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#define CLKID_SD_EMMC_C_CLK0_SEL		63
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#define CLKID_SD_EMMC_C_CLK0_DIV		64
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#define CLKID_MPLL0_DIV				65
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#define CLKID_MPLL1_DIV				66
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#define CLKID_MPLL2_DIV				67
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#define CLKID_MPLL3_DIV				68
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#define CLKID_HIFI_PLL				69
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#define CLKID_MPLL_PREDIV			70
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#define CLKID_FCLK_DIV2_DIV			71
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#define CLKID_FCLK_DIV3_DIV			72
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#define CLKID_FCLK_DIV4_DIV			73
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#define CLKID_FCLK_DIV5_DIV			74
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#define CLKID_FCLK_DIV7_DIV			75
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#define CLKID_PCIE_PLL				76
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#define CLKID_PCIE_MUX				77
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#define CLKID_PCIE_REF				78
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#define CLKID_PCIE_CML_EN0			79
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#define CLKID_PCIE_CML_EN1			80
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#define CLKID_GEN_CLK_SEL			82
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#define CLKID_GEN_CLK_DIV			83
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#define CLKID_GEN_CLK				84
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#define CLKID_SYS_PLL_DCO			85
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#define CLKID_FIXED_PLL_DCO			86
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#define CLKID_GP0_PLL_DCO			87
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#define CLKID_HIFI_PLL_DCO			88
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#define CLKID_PCIE_PLL_DCO			89
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#define CLKID_PCIE_PLL_OD			90
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#define CLKID_VPU_0_DIV				91
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#define CLKID_VPU_0_SEL				92
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#define CLKID_VPU_0				93
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#define CLKID_VPU_1_DIV				94
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#define CLKID_VPU_1_SEL				95
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#define CLKID_VPU_1				96
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#define CLKID_VPU				97
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#define CLKID_VAPB_0_DIV			98
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#define CLKID_VAPB_0_SEL			99
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#define CLKID_VAPB_0				100
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#define CLKID_VAPB_1_DIV			101
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#define CLKID_VAPB_1_SEL			102
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#define CLKID_VAPB_1				103
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#define CLKID_VAPB_SEL				104
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#define CLKID_VAPB				105
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#define CLKID_VCLK				106
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#define CLKID_VCLK2				107
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#define CLKID_VCLK_SEL				108
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#define CLKID_VCLK2_SEL				109
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#define CLKID_VCLK_INPUT			110
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#define CLKID_VCLK2_INPUT			111
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#define CLKID_VCLK_DIV				112
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#define CLKID_VCLK2_DIV				113
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#define CLKID_VCLK_DIV2_EN			114
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#define CLKID_VCLK_DIV4_EN			115
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#define CLKID_VCLK_DIV6_EN			116
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#define CLKID_VCLK_DIV12_EN			117
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#define CLKID_VCLK2_DIV2_EN			118
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#define CLKID_VCLK2_DIV4_EN			119
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#define CLKID_VCLK2_DIV6_EN			120
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#define CLKID_VCLK2_DIV12_EN			121
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#define CLKID_VCLK_DIV1				122
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#define CLKID_VCLK_DIV2				123
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#define CLKID_VCLK_DIV4				124
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#define CLKID_VCLK_DIV6				125
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#define CLKID_VCLK_DIV12			126
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#define CLKID_VCLK2_DIV1			127
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#define CLKID_VCLK2_DIV2			128
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#define CLKID_VCLK2_DIV4			129
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#define CLKID_VCLK2_DIV6			130
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#define CLKID_VCLK2_DIV12			131
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#define CLKID_CTS_ENCL_SEL			132
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#define CLKID_CTS_ENCL				133
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#define CLKID_VDIN_MEAS_SEL			134
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#define CLKID_VDIN_MEAS_DIV			135
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#define CLKID_VDIN_MEAS				136
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#endif /* __AXG_CLKC_H */
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