CoCalc -- cix,sky1.h

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/contrib/device-tree/include/dt-bindings/clock/cix,sky1.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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 * Copyright 2024-2025 Cix Technology Group Co., Ltd.
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 */
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#ifndef _DT_BINDINGS_CLK_CIX_SKY1_H
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#define _DT_BINDINGS_CLK_CIX_SKY1_H
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#define CLK_TREE_CPU_GICxCLK			0
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#define CLK_TREE_CPU_PPUCLK			1
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#define CLK_TREE_CPU_PERIPHCLK			2
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#define CLK_TREE_DSU_CLK			3
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#define CLK_TREE_DSU_PCLK			4
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#define CLK_TREE_CPU_CLK_BC0			5
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#define CLK_TREE_CPU_CLK_BC1			6
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#define CLK_TREE_CPU_CLK_BC2			7
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#define CLK_TREE_CPU_CLK_BC3			8
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#define CLK_TREE_CPU_CLK_MC0			9
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#define CLK_TREE_CPU_CLK_MC1			10
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#define CLK_TREE_CPU_CLK_MC2			11
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#define CLK_TREE_CPU_CLK_MC3			12
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#define CLK_TREE_CPU_CLK_LC0			13
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#define CLK_TREE_CPU_CLK_LC1			14
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#define CLK_TREE_CPU_CLK_LC2			15
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#define CLK_TREE_CPU_CLK_LC3			16
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#define CLK_TREE_CSI_CTRL0_PCLK			17
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#define CLK_TREE_CSI_CTRL1_PCLK			18
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#define CLK_TREE_CSI_CTRL2_PCLK			19
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#define CLK_TREE_CSI_CTRL3_PCLK			20
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#define CLK_TREE_CSI_DMA0_PCLK			21
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#define CLK_TREE_CSI_DMA1_PCLK			22
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#define CLK_TREE_CSI_DMA2_PCLK			23
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#define CLK_TREE_CSI_DMA3_PCLK			24
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#define CLK_TREE_CSI_PHY0_PSM			25
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#define CLK_TREE_CSI_PHY1_PSM			26
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#define CLK_TREE_CSI_PHY0_APBCLK		27
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#define CLK_TREE_CSI_PHY1_APBCLK		28
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#define CLK_TREE_FCH_APB_CLK			29
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#define CLK_TREE_GPU_CLK_400M			30
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#define CLK_TREE_GPU_CLK_CORE			31
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#define CLK_TREE_GPU_CLK_STACKS			32
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#define CLK_TREE_DP0_PIXEL0			33
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#define CLK_TREE_DP0_PIXEL1			34
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#define CLK_TREE_DP1_PIXEL0			35
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#define CLK_TREE_DP1_PIXEL1			36
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#define CLK_TREE_DP2_PIXEL0			37
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#define CLK_TREE_DP2_PIXEL1			38
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#define CLK_TREE_DP3_PIXEL0			39
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#define CLK_TREE_DP3_PIXEL1			40
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#define CLK_TREE_DP4_PIXEL0			41
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#define CLK_TREE_DP4_PIXEL1			42
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#define CLK_TREE_DPU_CLK			43
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#define CLK_TREE_DPU0_ACLK			44
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#define CLK_TREE_DPU1_ACLK			45
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#define CLK_TREE_DPU2_ACLK			46
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#define CLK_TREE_DPU3_ACLK			47
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#define CLK_TREE_DPU4_ACLK			48
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#define CLK_TREE_DPC0_VIDCLK0			49
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#define CLK_TREE_DPC0_VIDCLK1			50
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#define CLK_TREE_DPC1_VIDCLK0			51
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#define CLK_TREE_DPC1_VIDCLK1			52
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#define CLK_TREE_DPC2_VIDCLK0			53
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#define CLK_TREE_DPC2_VIDCLK1			54
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#define CLK_TREE_DPC3_VIDCLK0			55
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#define CLK_TREE_DPC3_VIDCLK1			56
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#define CLK_TREE_DPC4_VIDCLK0			57
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#define CLK_TREE_DPC4_VIDCLK1			58
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#define CLK_TREE_DPC0_APBCLK			59
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#define CLK_TREE_DPC1_APBCLK			60
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#define CLK_TREE_DPC2_APBCLK			61
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#define CLK_TREE_DPC3_APBCLK			62
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#define CLK_TREE_DPC4_APBCLK			63
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#define CLK_TREE_NPU_MEMCLK			64
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#define CLK_TREE_NPU_SYSCLK			65
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#define CLK_TREE_NPU_DBGCLK			66
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#define CLK_TREE_VPU_APBCLK			67
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#define CLK_TREE_ISP_ACLK			68
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#define CLK_TREE_ISP_SCLK			69
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#define CLK_TREE_AUDIO_CLK4			70
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#define CLK_TREE_AUDIO_CLK5			71
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#define CLK_TREE_CAMERA_MCLK0			72
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#define CLK_TREE_CAMERA_MCLK1			73
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#define CLK_TREE_CAMERA_MCLK2			74
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#define CLK_TREE_CAMERA_MCLK3			75
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#define CLK_TREE_AUDIO_CLK0			76
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#define CLK_TREE_AUDIO_CLK1			77
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#define CLK_TREE_AUDIO_CLK2			78
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#define CLK_TREE_AUDIO_CLK3			79
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#define CLK_TREE_MM_NI700_CLK			80
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#define CLK_TREE_SYS_NI700_CLK			81
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#define CLK_TREE_GMAC0_ACLK			82
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#define CLK_TREE_GMAC1_ACLK			83
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#define CLK_TREE_GMAC0_DIV_ACLK			84
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#define CLK_TREE_GMAC0_DIV_TXCLK		85
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#define CLK_TREE_GMAC0_RGMII0_TXCLK		86
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#define CLK_TREE_GMAC1_DIV_ACLK			87
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#define CLK_TREE_GMAC1_DIV_TXCLK		88
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#define CLK_TREE_GMAC1_RGMII0_TXCLK		89
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#define CLK_TREE_GMAC0_PCLK			90
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#define CLK_TREE_GMAC1_PCLK			91
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#define CLK_TREE_USB2_0_AXI_GATE		92
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#define CLK_TREE_USB2_0_APB_GATE		93
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#define CLK_TREE_USB2_1_AXI_GATE		94
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#define CLK_TREE_USB2_1_APB_GATE		95
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#define CLK_TREE_USB2_2_AXI_GATE		96
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#define CLK_TREE_USB2_2_APB_GATE		97
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#define CLK_TREE_USB2_3_AXI_GATE		98
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#define CLK_TREE_USB2_3_APB_GATE		99
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#define CLK_TREE_USB2_0_PHY_GATE		100
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#define CLK_TREE_USB2_1_PHY_GATE		101
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#define CLK_TREE_USB2_2_PHY_GATE		102
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#define CLK_TREE_USB2_3_PHY_GATE		103
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#define CLK_TREE_USB3C_DRD_AXI_GATE		104
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#define CLK_TREE_USB3C_DRD_APB_GATE		105
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#define CLK_TREE_USB3C_DRD_PHY2_GATE		106
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#define CLK_TREE_USB3C_DRD_PHY3_GATE		107
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#define CLK_TREE_USB3C_0_AXI_GATE		108
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#define CLK_TREE_USB3C_0_APB_GATE		109
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#define CLK_TREE_USB3C_0_PHY2_GATE		110
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#define CLK_TREE_USB3C_0_PHY3_GATE		111
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#define CLK_TREE_USB3C_1_AXI_GATE		112
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#define CLK_TREE_USB3C_1_APB_GATE		113
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#define CLK_TREE_USB3C_1_PHY2_GATE		114
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#define CLK_TREE_USB3C_1_PHY3_GATE		115
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#define CLK_TREE_USB3C_2_AXI_GATE		116
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#define CLK_TREE_USB3C_2_APB_GATE		117
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#define CLK_TREE_USB3C_2_PHY2_GATE		118
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#define CLK_TREE_USB3C_2_PHY3_GATE		119
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#define CLK_TREE_USB3A_0_AXI_GATE		120
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#define CLK_TREE_USB3A_0_APB_GATE		121
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#define CLK_TREE_USB3A_0_PHY2_GATE		122
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#define CLK_TREE_USB3A_1_AXI_GATE		123
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#define CLK_TREE_USB3A_1_APB_GATE		124
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#define CLK_TREE_USB3A_1_PHY2_GATE		125
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#define CLK_TREE_USB3A_PHY3_GATE		126
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#define CLK_TREE_USB2_0_CLK_SOF			127
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#define CLK_TREE_USB2_1_CLK_SOF			128
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#define CLK_TREE_USB2_2_CLK_SOF			129
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#define CLK_TREE_USB2_3_CLK_SOF			130
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#define CLK_TREE_USB3C_DRD_CLK_SOF		131
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#define CLK_TREE_USB3C_H0_CLK_SOF		132
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#define CLK_TREE_USB3C_H1_CLK_SOF		133
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#define CLK_TREE_USB3C_H2_CLK_SOF		134
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#define CLK_TREE_USB3A_H0_CLK_SOF		135
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#define CLK_TREE_USB3A_H1_CLK_SOF		136
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#define CLK_TREE_USB2_0_CLK_LPM			137
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#define CLK_TREE_USB2_1_CLK_LPM			138
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#define CLK_TREE_USB2_2_CLK_LPM			139
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#define CLK_TREE_USB2_3_CLK_LPM			140
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#define CLK_TREE_USB3C_DRD_CLK_LPM		141
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#define CLK_TREE_USB3C_H0_CLK_LPM		142
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#define CLK_TREE_USB3C_H1_CLK_LPM		143
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#define CLK_TREE_USB3C_H2_CLK_LPM		144
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#define CLK_TREE_USB3A_H0_CLK_LPM		145
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#define CLK_TREE_USB3A_H1_CLK_LPM		146
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#define CLK_TREE_USB2_0_PHY_REF			147
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#define CLK_TREE_USB2_1_PHY_REF			148
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#define CLK_TREE_USB2_2_PHY_REF			149
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#define CLK_TREE_USB2_3_PHY_REF			150
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#define CLK_TREE_USB3C_DRD_PHY_REF		151
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#define CLK_TREE_USB3C_H0_PHY_REF		152
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#define CLK_TREE_USB3C_H1_PHY_REF		153
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#define CLK_TREE_USB3C_H2_PHY_REF		154
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#define CLK_TREE_USB3A_H0_PHY_REF		155
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#define CLK_TREE_USB3A_H1_PHY_REF		156
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#define CLK_TREE_USB3C_DRD_PHY_x4_REF		157
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#define CLK_TREE_USB3C_H0_PHY_x4_REF		158
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#define CLK_TREE_USB3C_H1_PHY_x4_REF		159
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#define CLK_TREE_USB3C_H2_PHY_x4_REF		160
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#define CLK_TREE_USB3A_PHY_x2_REF		161
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#define CLK_TREE_PCIE_X8CTRL_APB		162
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#define CLK_TREE_PCIE_X4CTRL_APB		163
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#define CLK_TREE_PCIE_X2CTRL_APB		164
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#define CLK_TREE_PCIE_X1_0CTRL_APB		165
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#define CLK_TREE_PCIE_X1_1CTRL_APB		166
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#define CLK_TREE_PCIE_X8_PHY_APB		167
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#define CLK_TREE_PCIE_X4_PHY_APB		168
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#define CLK_TREE_PCIE_X211_PHY_APB		169
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#define CLK_TREE_PCIE_NI700_CLK			170
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#define CLK_TREE_PCIE_CTRL0_CLK			171
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#define CLK_TREE_PCIE_CTRL1_CLK			172
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#define CLK_TREE_PCIE_CTRL2_CLK			173
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#define CLK_TREE_PCIE_CTRL3_CLK			174
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#define CLK_TREE_PCIE_CTRL4_CLK			175
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#define CLK_TREE_CSI_CTRL0_SYSCLK		176
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#define CLK_TREE_CSI_CTRL1_SYSCLK		177
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#define CLK_TREE_CSI_CTRL2_SYSCLK		178
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#define CLK_TREE_CSI_CTRL3_SYSCLK		179
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#define CLK_TREE_CSI_CTRL0_PIXEL0_CLK		180
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#define CLK_TREE_CSI_CTRL0_PIXEL1_CLK		181
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#define CLK_TREE_CSI_CTRL0_PIXEL2_CLK		182
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#define CLK_TREE_CSI_CTRL0_PIXEL3_CLK		183
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#define CLK_TREE_CSI_CTRL1_PIXEL0_CLK		184
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#define CLK_TREE_CSI_CTRL2_PIXEL0_CLK		185
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#define CLK_TREE_CSI_CTRL2_PIXEL1_CLK		186
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#define CLK_TREE_CSI_CTRL2_PIXEL2_CLK		187
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#define CLK_TREE_CSI_CTRL2_PIXEL3_CLK		188
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#define CLK_TREE_CSI_CTRL3_PIXEL0_CLK		189
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#define CLK_TREE_CI700_GCLK0			190
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#define CLK_TREE_DDRC0_ACLK_CLK			191
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#define CLK_TREE_DDRC1_ACLK_CLK			192
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#define CLK_TREE_DDRC2_ACLK_CLK			193
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#define CLK_TREE_DDRC3_ACLK_CLK			194
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#define CLK_TREE_DDRC0_DFICLK_CLK		195
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#define CLK_TREE_DDRC1_DFICLK_CLK		196
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#define CLK_TREE_DDRC2_DFICLK_CLK		197
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#define CLK_TREE_DDRC3_DFICLK_CLK		198
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#define CLK_TREE_PHY0_SYNC_CLK			199
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#define CLK_TREE_PHY1_SYNC_CLK			200
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#define CLK_TREE_PHY2_SYNC_CLK			201
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#define CLK_TREE_PHY3_SYNC_CLK			202
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#define CLK_TREE_PHY0_BYPASS_CLK		203
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#define CLK_TREE_PHY1_BYPASS_CLK		204
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#define CLK_TREE_PHY2_BYPASS_CLK		205
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#define CLK_TREE_PHY3_BYPASS_CLK		206
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#define CLK_TREE_DDRC_0_APB			207
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#define CLK_TREE_DDRC_1_APB			208
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#define CLK_TREE_DDRC_2_APB			209
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#define CLK_TREE_DDRC_3_APB			210
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#define CLK_TREE_TZC400_0_APB			211
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#define CLK_TREE_TZC400_1_APB			212
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#define CLK_TREE_TZC400_2_APB			213
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#define CLK_TREE_TZC400_3_APB			214
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#define CLK_TREE_S5_SENSOR_HUB_25M		215
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#define CLK_TREE_S5_SENSOR_HUB_400M		216
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#define CLK_TREE_S5_CSS600_100M			217
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#define CLK_TREE_S5_DFD_800M			218
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#define CLK_TREE_S5_CSU_SE_800M			219
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#define CLK_TREE_S5_CSU_PM_800M			220
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#define CLK_TREE_PCIE_REF_B0			221
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#define CLK_TREE_PCIE_REF_B1			222
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#define CLK_TREE_PCIE_REF_B2			223
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#define CLK_TREE_PCIE_REF_B3			224
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#define CLK_TREE_PCIE_REF_B4			225
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#define CLK_TREE_PCIE_REF_PHY_X8		226
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#define CLK_TREE_PCIE_REF_PHY_X4		227
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#define CLK_TREE_PCIE_REF_PHY_X211		228
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#define CLK_TREE_GMAC_REC_CLK			229
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#define CLK_TREE_GPUTOP_PLL			230
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#define CLK_TREE_GPUCORE_PLL			231
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#define CLK_TREE_CPU_PLL_LIT			232
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#define CLK_TREE_CPU_PLL0			233
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#define CLK_TREE_CPU_PLL1			234
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#define CLK_TREE_CPU_PLL2			235
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#define CLK_TREE_CPU_PLL3			236
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#define CLK_TREE_FCH_I3C0_FUNC			237
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#define CLK_TREE_FCH_I3C1_FUNC			238
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#define CLK_TREE_FCH_DMA_ACLK			239
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#define CLK_TREE_FCH_XSPI_FUNC			240
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#define CLK_TREE_FCH_XSPI_MACLK			241
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#define CLK_TREE_FCH_TIMER_FUN			242
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#define CLK_TREE_FCH_APB_IO_S0			243
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#define CLK_TREE_FCH_I3C0_APB			244
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#define CLK_TREE_FCH_I3C1_APB			245
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#define CLK_TREE_FCH_UART0_APB			246
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#define CLK_TREE_FCH_UART1_APB			247
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#define CLK_TREE_FCH_UART2_APB			248
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#define CLK_TREE_FCH_UART3_APB			249
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#define CLK_TREE_FCH_SPI0_APB			250
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#define CLK_TREE_FCH_SPI1_APB			251
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#define CLK_TREE_FCH_XSPI_APB			252
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#define CLK_TREE_FCH_I2C0_APB			253
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#define CLK_TREE_FCH_I2C1_APB			254
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#define CLK_TREE_FCH_I2C2_APB			255
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#define CLK_TREE_FCH_I2C3_APB			256
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#define CLK_TREE_FCH_I2C4_APB			257
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#define CLK_TREE_FCH_I2C5_APB			258
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#define CLK_TREE_FCH_I2C6_APB			259
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#define CLK_TREE_FCH_I2C7_APB			260
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#define CLK_TREE_FCH_TIMER_APB			261
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#define CLK_TREE_FCH_GPIO_APB			262
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#define CLK_TREE_FCH_UART0_FUNC			263
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#define CLK_TREE_FCH_UART1_FUNC			264
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#define CLK_TREE_FCH_UART2_FUNC			265
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#define CLK_TREE_FCH_UART3_FUNC			266
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/* 267~271 not used by AP, skip */
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#define CLK_TREE_GPU_CLK_200M			272
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#endif
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