Path: blob/main/sys/contrib/device-tree/include/dt-bindings/dma/jz4775-dma.h
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/* SPDX-License-Identifier: GPL-2.0-only */1/*2* This header provides macros for JZ4775 DMA bindings.3*4* Copyright (c) 2020 周琰杰 (Zhou Yanjie) <[email protected]>5*/67#ifndef __DT_BINDINGS_DMA_JZ4775_DMA_H__8#define __DT_BINDINGS_DMA_JZ4775_DMA_H__910/*11* Request type numbers for the JZ4775 DMA controller (written to the DRTn12* register for the channel).13*/14#define JZ4775_DMA_I2S0_TX 0x615#define JZ4775_DMA_I2S0_RX 0x716#define JZ4775_DMA_AUTO 0x817#define JZ4775_DMA_SADC_RX 0x918#define JZ4775_DMA_UART3_TX 0x0e19#define JZ4775_DMA_UART3_RX 0x0f20#define JZ4775_DMA_UART2_TX 0x1021#define JZ4775_DMA_UART2_RX 0x1122#define JZ4775_DMA_UART1_TX 0x1223#define JZ4775_DMA_UART1_RX 0x1324#define JZ4775_DMA_UART0_TX 0x1425#define JZ4775_DMA_UART0_RX 0x1526#define JZ4775_DMA_SSI0_TX 0x1627#define JZ4775_DMA_SSI0_RX 0x1728#define JZ4775_DMA_MSC0_TX 0x1a29#define JZ4775_DMA_MSC0_RX 0x1b30#define JZ4775_DMA_MSC1_TX 0x1c31#define JZ4775_DMA_MSC1_RX 0x1d32#define JZ4775_DMA_MSC2_TX 0x1e33#define JZ4775_DMA_MSC2_RX 0x1f34#define JZ4775_DMA_PCM0_TX 0x2035#define JZ4775_DMA_PCM0_RX 0x2136#define JZ4775_DMA_SMB0_TX 0x2437#define JZ4775_DMA_SMB0_RX 0x2538#define JZ4775_DMA_SMB1_TX 0x2639#define JZ4775_DMA_SMB1_RX 0x2740#define JZ4775_DMA_SMB2_TX 0x2841#define JZ4775_DMA_SMB2_RX 0x294243#endif /* __DT_BINDINGS_DMA_JZ4775_DMA_H__ */444546