CoCalc -- mt6779-gce.h

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/contrib/device-tree/include/dt-bindings/gce/mt6779-gce.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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 * Copyright (c) 2019 MediaTek Inc.
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 * Author: Dennis-YC Hsieh <[email protected]>
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 */
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#ifndef _DT_BINDINGS_GCE_MT6779_H
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#define _DT_BINDINGS_GCE_MT6779_H
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#define CMDQ_NO_TIMEOUT		0xffffffff
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/* GCE HW thread priority */
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#define CMDQ_THR_PRIO_LOWEST	0
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#define CMDQ_THR_PRIO_1		1
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#define CMDQ_THR_PRIO_2		2
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#define CMDQ_THR_PRIO_3		3
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#define CMDQ_THR_PRIO_4		4
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#define CMDQ_THR_PRIO_5		5
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#define CMDQ_THR_PRIO_6		6
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#define CMDQ_THR_PRIO_HIGHEST	7
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/* GCE subsys table */
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#define SUBSYS_1300XXXX		0
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#define SUBSYS_1400XXXX		1
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#define SUBSYS_1401XXXX		2
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#define SUBSYS_1402XXXX		3
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#define SUBSYS_1502XXXX		4
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#define SUBSYS_1880XXXX		5
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#define SUBSYS_1881XXXX		6
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#define SUBSYS_1882XXXX		7
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#define SUBSYS_1883XXXX		8
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#define SUBSYS_1884XXXX		9
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#define SUBSYS_1000XXXX		10
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#define SUBSYS_1001XXXX		11
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#define SUBSYS_1002XXXX		12
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#define SUBSYS_1003XXXX		13
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#define SUBSYS_1004XXXX		14
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#define SUBSYS_1005XXXX		15
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#define SUBSYS_1020XXXX		16
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#define SUBSYS_1028XXXX		17
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#define SUBSYS_1700XXXX		18
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#define SUBSYS_1701XXXX		19
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#define SUBSYS_1702XXXX		20
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#define SUBSYS_1703XXXX		21
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#define SUBSYS_1800XXXX		22
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#define SUBSYS_1801XXXX		23
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#define SUBSYS_1802XXXX		24
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#define SUBSYS_1804XXXX		25
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#define SUBSYS_1805XXXX		26
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#define SUBSYS_1808XXXX		27
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#define SUBSYS_180aXXXX		28
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#define SUBSYS_180bXXXX		29
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#define CMDQ_SUBSYS_OFF		32
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/* GCE hardware events */
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#define CMDQ_EVENT_DISP_RDMA0_SOF		0
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#define CMDQ_EVENT_DISP_RDMA1_SOF		1
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#define CMDQ_EVENT_MDP_RDMA0_SOF		2
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#define CMDQ_EVENT_MDP_RDMA1_SOF		3
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#define CMDQ_EVENT_MDP_RSZ0_SOF			4
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#define CMDQ_EVENT_MDP_RSZ1_SOF			5
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#define CMDQ_EVENT_MDP_TDSHP_SOF		6
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#define CMDQ_EVENT_MDP_WROT0_SOF		7
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#define CMDQ_EVENT_MDP_WROT1_SOF		8
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#define CMDQ_EVENT_DISP_OVL0_SOF		9
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#define CMDQ_EVENT_DISP_2L_OVL0_SOF		10
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#define CMDQ_EVENT_DISP_2L_OVL1_SOF		11
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#define CMDQ_EVENT_DISP_WDMA0_SOF		12
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#define CMDQ_EVENT_DISP_COLOR0_SOF		13
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#define CMDQ_EVENT_DISP_CCORR0_SOF		14
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#define CMDQ_EVENT_DISP_AAL0_SOF		15
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#define CMDQ_EVENT_DISP_GAMMA0_SOF		16
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#define CMDQ_EVENT_DISP_DITHER0_SOF		17
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#define CMDQ_EVENT_DISP_PWM0_SOF		18
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#define CMDQ_EVENT_DISP_DSI0_SOF		19
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#define CMDQ_EVENT_DISP_DPI0_SOF		20
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#define CMDQ_EVENT_DISP_POSTMASK0_SOF		21
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#define CMDQ_EVENT_DISP_RSZ0_SOF		22
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#define CMDQ_EVENT_MDP_AAL_SOF			23
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#define CMDQ_EVENT_MDP_CCORR_SOF		24
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#define CMDQ_EVENT_DISP_DBI0_SOF		25
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#define CMDQ_EVENT_ISP_RELAY_SOF		26
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#define CMDQ_EVENT_IPU_RELAY_SOF		27
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#define CMDQ_EVENT_DISP_RDMA0_EOF		28
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#define CMDQ_EVENT_DISP_RDMA1_EOF		29
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#define CMDQ_EVENT_MDP_RDMA0_EOF		30
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#define CMDQ_EVENT_MDP_RDMA1_EOF		31
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#define CMDQ_EVENT_MDP_RSZ0_EOF			32
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#define CMDQ_EVENT_MDP_RSZ1_EOF			33
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#define CMDQ_EVENT_MDP_TDSHP_EOF		34
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#define CMDQ_EVENT_MDP_WROT0_W_EOF		35
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#define CMDQ_EVENT_MDP_WROT1_W_EOF		36
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#define CMDQ_EVENT_DISP_OVL0_EOF		37
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#define CMDQ_EVENT_DISP_2L_OVL0_EOF		38
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#define CMDQ_EVENT_DISP_2L_OVL1_EOF		39
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#define CMDQ_EVENT_DISP_WDMA0_EOF		40
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#define CMDQ_EVENT_DISP_COLOR0_EOF		41
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#define CMDQ_EVENT_DISP_CCORR0_EOF		42
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#define CMDQ_EVENT_DISP_AAL0_EOF		43
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#define CMDQ_EVENT_DISP_GAMMA0_EOF		44
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#define CMDQ_EVENT_DISP_DITHER0_EOF		45
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#define CMDQ_EVENT_DISP_DSI0_EOF		46
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#define CMDQ_EVENT_DISP_DPI0_EOF		47
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#define CMDQ_EVENT_DISP_RSZ0_EOF		49
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#define CMDQ_EVENT_MDP_AAL_FRAME_DONE		50
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#define CMDQ_EVENT_MDP_CCORR_FRAME_DONE		51
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#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE	52
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#define CMDQ_EVENT_MUTEX0_STREAM_EOF		130
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#define CMDQ_EVENT_MUTEX1_STREAM_EOF		131
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#define CMDQ_EVENT_MUTEX2_STREAM_EOF		132
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#define CMDQ_EVENT_MUTEX3_STREAM_EOF		133
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#define CMDQ_EVENT_MUTEX4_STREAM_EOF		134
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#define CMDQ_EVENT_MUTEX5_STREAM_EOF		135
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#define CMDQ_EVENT_MUTEX6_STREAM_EOF		136
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#define CMDQ_EVENT_MUTEX7_STREAM_EOF		137
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#define CMDQ_EVENT_MUTEX8_STREAM_EOF		138
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#define CMDQ_EVENT_MUTEX9_STREAM_EOF		139
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#define CMDQ_EVENT_MUTEX10_STREAM_EOF		140
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#define CMDQ_EVENT_MUTEX11_STREAM_EOF		141
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#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN		142
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#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN		143
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#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN		144
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#define CMDQ_EVENT_DISP_RDMA3_UNDERRUN		145
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#define CMDQ_EVENT_DSI0_TE			146
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#define CMDQ_EVENT_DSI0_IRQ_EVENT		147
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#define CMDQ_EVENT_DSI0_DONE_EVENT		148
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#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE	150
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#define CMDQ_EVENT_DISP_WDMA0_RST_DONE		151
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#define CMDQ_EVENT_MDP_WROT0_RST_DONE		153
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#define CMDQ_EVENT_MDP_RDMA0_RST_DONE		154
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#define CMDQ_EVENT_DISP_OVL0_RST_DONE		155
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#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE	156
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#define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE	157
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#define CMDQ_EVENT_DIP_CQ_THREAD0_EOF		257
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#define CMDQ_EVENT_DIP_CQ_THREAD1_EOF		258
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#define CMDQ_EVENT_DIP_CQ_THREAD2_EOF		259
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#define CMDQ_EVENT_DIP_CQ_THREAD3_EOF		260
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#define CMDQ_EVENT_DIP_CQ_THREAD4_EOF		261
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#define CMDQ_EVENT_DIP_CQ_THREAD5_EOF		262
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#define CMDQ_EVENT_DIP_CQ_THREAD6_EOF		263
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#define CMDQ_EVENT_DIP_CQ_THREAD7_EOF		264
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#define CMDQ_EVENT_DIP_CQ_THREAD8_EOF		265
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#define CMDQ_EVENT_DIP_CQ_THREAD9_EOF		266
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#define CMDQ_EVENT_DIP_CQ_THREAD10_EOF		267
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#define CMDQ_EVENT_DIP_CQ_THREAD11_EOF		268
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#define CMDQ_EVENT_DIP_CQ_THREAD12_EOF		269
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#define CMDQ_EVENT_DIP_CQ_THREAD13_EOF		270
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#define CMDQ_EVENT_DIP_CQ_THREAD14_EOF		271
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#define CMDQ_EVENT_DIP_CQ_THREAD15_EOF		272
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#define CMDQ_EVENT_DIP_CQ_THREAD16_EOF		273
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#define CMDQ_EVENT_DIP_CQ_THREAD17_EOF		274
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#define CMDQ_EVENT_DIP_CQ_THREAD18_EOF		275
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#define CMDQ_EVENT_DIP_DMA_ERR_EVENT		276
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#define CMDQ_EVENT_AMD_FRAME_DONE		277
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#define CMDQ_EVENT_MFB_DONE			278
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#define CMDQ_EVENT_WPE_A_EOF			279
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#define CMDQ_EVENT_VENC_EOF			289
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#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE		290
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#define CMDQ_EVENT_JPEG_ENC_EOF			291
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#define CMDQ_EVENT_VENC_MB_DONE			292
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#define CMDQ_EVENT_VENC_128BYTE_CNT_DONE	293
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#define CMDQ_EVENT_ISP_FRAME_DONE_A		321
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#define CMDQ_EVENT_ISP_FRAME_DONE_B		322
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#define CMDQ_EVENT_ISP_FRAME_DONE_C		323
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#define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE	324
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#define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE	325
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#define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE	326
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#define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE	327
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#define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE	328
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#define CMDQ_EVENT_ISP_TSF_DONE			329
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#define CMDQ_EVENT_SENINF_0_FIFO_FULL		330
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#define CMDQ_EVENT_SENINF_1_FIFO_FULL		331
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#define CMDQ_EVENT_SENINF_2_FIFO_FULL		332
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#define CMDQ_EVENT_SENINF_3_FIFO_FULL		333
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#define CMDQ_EVENT_SENINF_4_FIFO_FULL		334
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#define CMDQ_EVENT_SENINF_5_FIFO_FULL		335
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#define CMDQ_EVENT_SENINF_6_FIFO_FULL		336
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#define CMDQ_EVENT_SENINF_7_FIFO_FULL		337
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#define CMDQ_EVENT_TG_OVRUN_A_INT_DLY		338
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#define CMDQ_EVENT_TG_OVRUN_B_INT_DLY		339
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#define CMDQ_EVENT_TG_OVRUN_C_INT		340
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#define CMDQ_EVENT_TG_GRABERR_A_INT_DLY		341
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#define CMDQ_EVENT_TG_GRABERR_B_INT_DLY		342
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#define CMDQ_EVENT_TG_GRABERR_C_INT		343
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#define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY		344
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#define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY		345
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#define CMDQ_EVENT_CQ_VR_SNAP_C_INT		346
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#define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY	347
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#define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY	348
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#define CMDQ_EVENT_DMA_R1_ERROR_C_INT		349
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#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0	353
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#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1	354
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#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2	355
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#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3	356
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#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0	385
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#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1	386
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#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2	387
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#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3	388
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#define CMDQ_EVENT_VDEC_EVENT_0			416
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#define CMDQ_EVENT_VDEC_EVENT_1			417
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#define CMDQ_EVENT_VDEC_EVENT_2			418
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#define CMDQ_EVENT_VDEC_EVENT_3			419
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#define CMDQ_EVENT_VDEC_EVENT_4			420
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#define CMDQ_EVENT_VDEC_EVENT_5			421
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#define CMDQ_EVENT_VDEC_EVENT_6			422
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#define CMDQ_EVENT_VDEC_EVENT_7			423
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#define CMDQ_EVENT_VDEC_EVENT_8			424
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#define CMDQ_EVENT_VDEC_EVENT_9			425
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#define CMDQ_EVENT_VDEC_EVENT_10		426
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#define CMDQ_EVENT_VDEC_EVENT_11		427
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#define CMDQ_EVENT_VDEC_EVENT_12		428
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#define CMDQ_EVENT_VDEC_EVENT_13		429
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#define CMDQ_EVENT_VDEC_EVENT_14		430
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#define CMDQ_EVENT_VDEC_EVENT_15		431
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#define CMDQ_EVENT_FDVT_DONE			449
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#define CMDQ_EVENT_FE_DONE			450
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#define CMDQ_EVENT_RSC_EOF			451
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#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT		452
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#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT		453
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#define CMDQ_EVENT_DSI0_TE_INFRA		898
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#endif
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