Path: blob/main/sys/contrib/device-tree/include/dt-bindings/net/ti-dp83869.h
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */1/*2* Device Tree constants for the Texas Instruments DP83869 PHY3*4* Author: Dan Murphy <[email protected]>5*6* Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/7*/89#ifndef _DT_BINDINGS_TI_DP83869_H10#define _DT_BINDINGS_TI_DP83869_H1112/* PHY CTRL bits */13#define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x0014#define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x0115#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x0216#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x031718/* IO_MUX_CFG - Clock output selection */19#define DP83869_CLK_O_SEL_CHN_A_RCLK 0x020#define DP83869_CLK_O_SEL_CHN_B_RCLK 0x121#define DP83869_CLK_O_SEL_CHN_C_RCLK 0x222#define DP83869_CLK_O_SEL_CHN_D_RCLK 0x323#define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x424#define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x525#define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x626#define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x727#define DP83869_CLK_O_SEL_CHN_A_TCLK 0x828#define DP83869_CLK_O_SEL_CHN_B_TCLK 0x929#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa30#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb31#define DP83869_CLK_O_SEL_REF_CLK 0xc3233#define DP83869_RGMII_COPPER_ETHERNET 0x0034#define DP83869_RGMII_1000_BASE 0x0135#define DP83869_RGMII_100_BASE 0x0236#define DP83869_RGMII_SGMII_BRIDGE 0x0337#define DP83869_1000M_MEDIA_CONVERT 0x0438#define DP83869_100M_MEDIA_CONVERT 0x0539#define DP83869_SGMII_COPPER_ETHERNET 0x064041#endif424344