Path: blob/main/sys/contrib/device-tree/include/dt-bindings/pinctrl/am33xx.h
48400 views
/* SPDX-License-Identifier: GPL-2.0 */1/*2* This header provides constants specific to AM33XX pinctrl bindings.3*/45#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H6#define _DT_BINDINGS_PINCTRL_AM33XX_H78#include <dt-bindings/pinctrl/omap.h>910/* am33xx specific mux bit defines */11#undef PULL_ENA12#undef INPUT_EN1314#define PULL_DISABLE (1 << 3)15#define INPUT_EN (1 << 5)16#define SLEWCTRL_SLOW (1 << 6)17#define SLEWCTRL_FAST 01819/* update macro depending on INPUT_EN and PULL_ENA */20#undef PIN_OUTPUT21#undef PIN_OUTPUT_PULLUP22#undef PIN_OUTPUT_PULLDOWN23#undef PIN_INPUT24#undef PIN_INPUT_PULLUP25#undef PIN_INPUT_PULLDOWN2627#define PIN_OUTPUT (PULL_DISABLE)28#define PIN_OUTPUT_PULLUP (PULL_UP)29#define PIN_OUTPUT_PULLDOWN 030#define PIN_INPUT (INPUT_EN | PULL_DISABLE)31#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)32#define PIN_INPUT_PULLDOWN (INPUT_EN)3334/* undef non-existing modes */35#undef PIN_OFF_NONE36#undef PIN_OFF_OUTPUT_HIGH37#undef PIN_OFF_OUTPUT_LOW38#undef PIN_OFF_INPUT_PULLUP39#undef PIN_OFF_INPUT_PULLDOWN40#undef PIN_OFF_WAKEUPENABLE4142#define AM335X_PIN_OFFSET_MIN 0x0800U4344#define AM335X_PIN_GPMC_AD0 0x80045#define AM335X_PIN_GPMC_AD1 0x80446#define AM335X_PIN_GPMC_AD2 0x80847#define AM335X_PIN_GPMC_AD3 0x80c48#define AM335X_PIN_GPMC_AD4 0x81049#define AM335X_PIN_GPMC_AD5 0x81450#define AM335X_PIN_GPMC_AD6 0x81851#define AM335X_PIN_GPMC_AD7 0x81c52#define AM335X_PIN_GPMC_AD8 0x82053#define AM335X_PIN_GPMC_AD9 0x82454#define AM335X_PIN_GPMC_AD10 0x82855#define AM335X_PIN_GPMC_AD11 0x82c56#define AM335X_PIN_GPMC_AD12 0x83057#define AM335X_PIN_GPMC_AD13 0x83458#define AM335X_PIN_GPMC_AD14 0x83859#define AM335X_PIN_GPMC_AD15 0x83c60#define AM335X_PIN_GPMC_A0 0x84061#define AM335X_PIN_GPMC_A1 0x84462#define AM335X_PIN_GPMC_A2 0x84863#define AM335X_PIN_GPMC_A3 0x84c64#define AM335X_PIN_GPMC_A4 0x85065#define AM335X_PIN_GPMC_A5 0x85466#define AM335X_PIN_GPMC_A6 0x85867#define AM335X_PIN_GPMC_A7 0x85c68#define AM335X_PIN_GPMC_A8 0x86069#define AM335X_PIN_GPMC_A9 0x86470#define AM335X_PIN_GPMC_A10 0x86871#define AM335X_PIN_GPMC_A11 0x86c72#define AM335X_PIN_GPMC_WAIT0 0x87073#define AM335X_PIN_GPMC_WPN 0x87474#define AM335X_PIN_GPMC_BEN1 0x87875#define AM335X_PIN_GPMC_CSN0 0x87c76#define AM335X_PIN_GPMC_CSN1 0x88077#define AM335X_PIN_GPMC_CSN2 0x88478#define AM335X_PIN_GPMC_CSN3 0x88879#define AM335X_PIN_GPMC_CLK 0x88c80#define AM335X_PIN_GPMC_ADVN_ALE 0x89081#define AM335X_PIN_GPMC_OEN_REN 0x89482#define AM335X_PIN_GPMC_WEN 0x89883#define AM335X_PIN_GPMC_BEN0_CLE 0x89c84#define AM335X_PIN_LCD_DATA0 0x8a085#define AM335X_PIN_LCD_DATA1 0x8a486#define AM335X_PIN_LCD_DATA2 0x8a887#define AM335X_PIN_LCD_DATA3 0x8ac88#define AM335X_PIN_LCD_DATA4 0x8b089#define AM335X_PIN_LCD_DATA5 0x8b490#define AM335X_PIN_LCD_DATA6 0x8b891#define AM335X_PIN_LCD_DATA7 0x8bc92#define AM335X_PIN_LCD_DATA8 0x8c093#define AM335X_PIN_LCD_DATA9 0x8c494#define AM335X_PIN_LCD_DATA10 0x8c895#define AM335X_PIN_LCD_DATA11 0x8cc96#define AM335X_PIN_LCD_DATA12 0x8d097#define AM335X_PIN_LCD_DATA13 0x8d498#define AM335X_PIN_LCD_DATA14 0x8d899#define AM335X_PIN_LCD_DATA15 0x8dc100#define AM335X_PIN_LCD_VSYNC 0x8e0101#define AM335X_PIN_LCD_HSYNC 0x8e4102#define AM335X_PIN_LCD_PCLK 0x8e8103#define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec104#define AM335X_PIN_MMC0_DAT3 0x8f0105#define AM335X_PIN_MMC0_DAT2 0x8f4106#define AM335X_PIN_MMC0_DAT1 0x8f8107#define AM335X_PIN_MMC0_DAT0 0x8fc108#define AM335X_PIN_MMC0_CLK 0x900109#define AM335X_PIN_MMC0_CMD 0x904110#define AM335X_PIN_MII1_COL 0x908111#define AM335X_PIN_MII1_CRS 0x90c112#define AM335X_PIN_MII1_RX_ER 0x910113#define AM335X_PIN_MII1_TX_EN 0x914114#define AM335X_PIN_MII1_RX_DV 0x918115#define AM335X_PIN_MII1_TXD3 0x91c116#define AM335X_PIN_MII1_TXD2 0x920117#define AM335X_PIN_MII1_TXD1 0x924118#define AM335X_PIN_MII1_TXD0 0x928119#define AM335X_PIN_MII1_TX_CLK 0x92c120#define AM335X_PIN_MII1_RX_CLK 0x930121#define AM335X_PIN_MII1_RXD3 0x934122#define AM335X_PIN_MII1_RXD2 0x938123#define AM335X_PIN_MII1_RXD1 0x93c124#define AM335X_PIN_MII1_RXD0 0x940125#define AM335X_PIN_RMII1_REF_CLK 0x944126#define AM335X_PIN_MDIO 0x948127#define AM335X_PIN_MDC 0x94c128#define AM335X_PIN_SPI0_SCLK 0x950129#define AM335X_PIN_SPI0_D0 0x954130#define AM335X_PIN_SPI0_D1 0x958131#define AM335X_PIN_SPI0_CS0 0x95c132#define AM335X_PIN_SPI0_CS1 0x960133#define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964134#define AM335X_PIN_UART0_CTSN 0x968135#define AM335X_PIN_UART0_RTSN 0x96c136#define AM335X_PIN_UART0_RXD 0x970137#define AM335X_PIN_UART0_TXD 0x974138#define AM335X_PIN_UART1_CTSN 0x978139#define AM335X_PIN_UART1_RTSN 0x97c140#define AM335X_PIN_UART1_RXD 0x980141#define AM335X_PIN_UART1_TXD 0x984142#define AM335X_PIN_I2C0_SDA 0x988143#define AM335X_PIN_I2C0_SCL 0x98c144#define AM335X_PIN_MCASP0_ACLKX 0x990145#define AM335X_PIN_MCASP0_FSX 0x994146#define AM335X_PIN_MCASP0_AXR0 0x998147#define AM335X_PIN_MCASP0_AHCLKR 0x99c148#define AM335X_PIN_MCASP0_ACLKR 0x9a0149#define AM335X_PIN_MCASP0_FSR 0x9a4150#define AM335X_PIN_MCASP0_AXR1 0x9a8151#define AM335X_PIN_MCASP0_AHCLKX 0x9ac152#define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0153#define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4154#define AM335X_PIN_WARMRSTN 0x9b8155#define AM335X_PIN_NNMI 0x9c0156#define AM335X_PIN_TMS 0x9d0157#define AM335X_PIN_TDI 0x9d4158#define AM335X_PIN_TDO 0x9d8159#define AM335X_PIN_TCK 0x9dc160#define AM335X_PIN_TRSTN 0x9e0161#define AM335X_PIN_EMU0 0x9e4162#define AM335X_PIN_EMU1 0x9e8163#define AM335X_PIN_RTC_PWRONRSTN 0x9f8164#define AM335X_PIN_PMIC_POWER_EN 0x9fc165#define AM335X_PIN_EXT_WAKEUP 0xa00166#define AM335X_PIN_USB0_DRVVBUS 0xa1c167#define AM335X_PIN_USB1_DRVVBUS 0xa34168169#define AM335X_PIN_OFFSET_MAX 0x0a34U170171#endif172173174