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freebsd
GitHub Repository: freebsd/freebsd-src
 Path: blob/main/sys/contrib/device-tree/include/dt-bindings/reset/mt7622-reset.h
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/* SPDX-License-Identifier: GPL-2.0-only */

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/*

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 * Copyright (c) 2017 MediaTek Inc.

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 * Author: Sean Wang <[email protected]>

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 */

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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622

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#define _DT_BINDINGS_RESET_CONTROLLER_MT7622

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/* INFRACFG resets */

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#define MT7622_INFRA_EMI_REG_RST		0

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#define MT7622_INFRA_DRAMC0_A0_RST		1

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#define MT7622_INFRA_APCIRQ_EINT_RST		3

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#define MT7622_INFRA_APXGPT_RST			4

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#define MT7622_INFRA_SCPSYS_RST			5

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#define MT7622_INFRA_PMIC_WRAP_RST		7

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#define MT7622_INFRA_IRRX_RST			9

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#define MT7622_INFRA_EMI_RST			16

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#define MT7622_INFRA_WED0_RST			17

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#define MT7622_INFRA_DRAMC_RST			18

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#define MT7622_INFRA_CCI_INTF_RST		19

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#define MT7622_INFRA_TRNG_RST			21

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#define MT7622_INFRA_SYSIRQ_RST			22

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#define MT7622_INFRA_WED1_RST			25

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/* PERICFG Subsystem resets */

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#define MT7622_PERI_UART0_SW_RST		0

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#define MT7622_PERI_UART1_SW_RST		1

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#define MT7622_PERI_UART2_SW_RST		2

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#define MT7622_PERI_UART3_SW_RST		3

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#define MT7622_PERI_UART4_SW_RST		4

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#define MT7622_PERI_BTIF_SW_RST			6

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#define MT7622_PERI_PWM_SW_RST			8

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#define MT7622_PERI_AUXADC_SW_RST		10

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#define MT7622_PERI_DMA_SW_RST			11

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#define MT7622_PERI_IRTX_SW_RST			13

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#define MT7622_PERI_NFI_SW_RST			14

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#define MT7622_PERI_THERM_SW_RST		16

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#define MT7622_PERI_MSDC0_SW_RST		19

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#define MT7622_PERI_MSDC1_SW_RST		20

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#define MT7622_PERI_I2C0_SW_RST			22

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#define MT7622_PERI_I2C1_SW_RST			23

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#define MT7622_PERI_I2C2_SW_RST			24

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#define MT7622_PERI_SPI0_SW_RST			33

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#define MT7622_PERI_SPI1_SW_RST			34

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#define MT7622_PERI_FLASHIF_SW_RST		36

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/* TOPRGU resets */

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#define MT7622_TOPRGU_INFRA_RST			0

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#define MT7622_TOPRGU_ETHDMA_RST		1

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#define MT7622_TOPRGU_DDRPHY_RST		6

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#define MT7622_TOPRGU_INFRA_AO_RST		8

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#define MT7622_TOPRGU_CONN_RST			9

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#define MT7622_TOPRGU_APMIXED_RST		10

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#define MT7622_TOPRGU_CONN_MCU_RST		12

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/* PCIe/SATA Subsystem resets */

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#define MT7622_SATA_PHY_REG_RST			12

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#define MT7622_SATA_PHY_SW_RST			13

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#define MT7622_SATA_AXI_BUS_RST			15

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#define MT7622_PCIE1_CORE_RST			19

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#define MT7622_PCIE1_MMIO_RST			20

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#define MT7622_PCIE1_HRST			21

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#define MT7622_PCIE1_USER_RST			22

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#define MT7622_PCIE1_PIPE_RST			23

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#define MT7622_PCIE0_CORE_RST			27

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#define MT7622_PCIE0_MMIO_RST			28

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#define MT7622_PCIE0_HRST			29

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#define MT7622_PCIE0_USER_RST			30

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#define MT7622_PCIE0_PIPE_RST			31

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/* SSUSB Subsystem resets */

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#define MT7622_SSUSB_PHY_PWR_RST		3

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#define MT7622_SSUSB_MAC_PWR_RST		4

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/* ETHSYS Subsystem resets */

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#define MT7622_ETHSYS_SYS_RST			0

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#define MT7622_ETHSYS_MCM_RST			2

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#define MT7622_ETHSYS_HSDMA_RST			5

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#define MT7622_ETHSYS_FE_RST			6

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#define MT7622_ETHSYS_GMAC_RST			23

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#define MT7622_ETHSYS_EPHY_RST			24

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#define MT7622_ETHSYS_CRYPTO_RST		29

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#define MT7622_ETHSYS_PPE_RST			31

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#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */

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