Path: blob/main/sys/contrib/device-tree/include/dt-bindings/reset/mt7986-resets.h
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */1/*2* Copyright (c) 2022 MediaTek Inc.3* Author: Sam Shih <[email protected]>4*/56#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT79867#define _DT_BINDINGS_RESET_CONTROLLER_MT798689/* INFRACFG resets */10#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 611#define MT7986_INFRACFG_SSUSB_SW_RST 712#define MT7986_INFRACFG_EIP97_SW_RST 813#define MT7986_INFRACFG_AUDIO_SW_RST 1314#define MT7986_INFRACFG_CQ_DMA_SW_RST 141516#define MT7986_INFRACFG_TRNG_SW_RST 1717#define MT7986_INFRACFG_AP_DMA_SW_RST 3218#define MT7986_INFRACFG_I2C_SW_RST 3319#define MT7986_INFRACFG_NFI_SW_RST 3420#define MT7986_INFRACFG_SPI0_SW_RST 3521#define MT7986_INFRACFG_SPI1_SW_RST 3622#define MT7986_INFRACFG_UART0_SW_RST 3723#define MT7986_INFRACFG_UART1_SW_RST 3824#define MT7986_INFRACFG_UART2_SW_RST 3925#define MT7986_INFRACFG_AUXADC_SW_RST 432627#define MT7986_INFRACFG_APXGPT_SW_RST 6628#define MT7986_INFRACFG_PWM_SW_RST 682930#define MT7986_INFRACFG_SW_RST_NUM 693132/* TOPRGU resets */33#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 034#define MT7986_TOPRGU_SGMII0_SW_RST 135#define MT7986_TOPRGU_SGMII1_SW_RST 236#define MT7986_TOPRGU_INFRA_SW_RST 337#define MT7986_TOPRGU_U2PHY_SW_RST 538#define MT7986_TOPRGU_PCIE_SW_RST 639#define MT7986_TOPRGU_SSUSB_SW_RST 740#define MT7986_TOPRGU_ETHDMA_SW_RST 2041#define MT7986_TOPRGU_CONSYS_SW_RST 234243#define MT7986_TOPRGU_SW_RST_NUM 244445/* ETHSYS Subsystem resets */46#define MT7986_ETHSYS_FE_SW_RST 647#define MT7986_ETHSYS_PMTR_SW_RST 848#define MT7986_ETHSYS_GMAC_SW_RST 2349#define MT7986_ETHSYS_PPE0_SW_RST 3050#define MT7986_ETHSYS_PPE1_SW_RST 315152#define MT7986_ETHSYS_SW_RST_NUM 325354#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */555657