Path: blob/main/sys/contrib/device-tree/include/dt-bindings/reset/mt8135-resets.h
48524 views
/* SPDX-License-Identifier: GPL-2.0-only */1/*2* Copyright (c) 2014 MediaTek Inc.3* Author: Flora Fu, MediaTek4*/56#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT81357#define _DT_BINDINGS_RESET_CONTROLLER_MT813589/* INFRACFG resets */10#define MT8135_INFRA_EMI_REG_RST 011#define MT8135_INFRA_DRAMC0_A0_RST 112#define MT8135_INFRA_CCIF0_RST 213#define MT8135_INFRA_APCIRQ_EINT_RST 314#define MT8135_INFRA_APXGPT_RST 415#define MT8135_INFRA_SCPSYS_RST 516#define MT8135_INFRA_CCIF1_RST 617#define MT8135_INFRA_PMIC_WRAP_RST 718#define MT8135_INFRA_KP_RST 819#define MT8135_INFRA_EMI_RST 3220#define MT8135_INFRA_DRAMC0_RST 3421#define MT8135_INFRA_SMI_RST 3522#define MT8135_INFRA_M4U_RST 362324/* PERICFG resets */25#define MT8135_PERI_UART0_SW_RST 026#define MT8135_PERI_UART1_SW_RST 127#define MT8135_PERI_UART2_SW_RST 228#define MT8135_PERI_UART3_SW_RST 329#define MT8135_PERI_IRDA_SW_RST 430#define MT8135_PERI_PTP_SW_RST 531#define MT8135_PERI_AP_HIF_SW_RST 632#define MT8135_PERI_GPCU_SW_RST 733#define MT8135_PERI_MD_HIF_SW_RST 834#define MT8135_PERI_NLI_SW_RST 935#define MT8135_PERI_AUXADC_SW_RST 1036#define MT8135_PERI_DMA_SW_RST 1137#define MT8135_PERI_NFI_SW_RST 1438#define MT8135_PERI_PWM_SW_RST 1539#define MT8135_PERI_THERM_SW_RST 1640#define MT8135_PERI_MSDC0_SW_RST 1741#define MT8135_PERI_MSDC1_SW_RST 1842#define MT8135_PERI_MSDC2_SW_RST 1943#define MT8135_PERI_MSDC3_SW_RST 2044#define MT8135_PERI_I2C0_SW_RST 2245#define MT8135_PERI_I2C1_SW_RST 2346#define MT8135_PERI_I2C2_SW_RST 2447#define MT8135_PERI_I2C3_SW_RST 2548#define MT8135_PERI_I2C4_SW_RST 2649#define MT8135_PERI_I2C5_SW_RST 2750#define MT8135_PERI_I2C6_SW_RST 2851#define MT8135_PERI_USB_SW_RST 2952#define MT8135_PERI_SPI1_SW_RST 3353#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 345455#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */565758