Path: blob/main/sys/contrib/device-tree/include/dt-bindings/reset/mt8186-resets.h
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */1/*2* Copyright (c) 2022 MediaTek Inc.3* Author: Runyang Chen <[email protected]>4*/56#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT81867#define _DT_BINDINGS_RESET_CONTROLLER_MT818689/* TOPRGU resets */10#define MT8186_TOPRGU_INFRA_SW_RST 011#define MT8186_TOPRGU_MM_SW_RST 112#define MT8186_TOPRGU_MFG_SW_RST 213#define MT8186_TOPRGU_VENC_SW_RST 314#define MT8186_TOPRGU_VDEC_SW_RST 415#define MT8186_TOPRGU_IMG_SW_RST 516#define MT8186_TOPRGU_DDR_SW_RST 617#define MT8186_TOPRGU_INFRA_AO_SW_RST 818#define MT8186_TOPRGU_CONNSYS_SW_RST 919#define MT8186_TOPRGU_APMIXED_SW_RST 1020#define MT8186_TOPRGU_PWRAP_SW_RST 1121#define MT8186_TOPRGU_CONN_MCU_SW_RST 1222#define MT8186_TOPRGU_IPNNA_SW_RST 1323#define MT8186_TOPRGU_WPE_SW_RST 1424#define MT8186_TOPRGU_ADSP_SW_RST 1525#define MT8186_TOPRGU_AUDIO_SW_RST 1726#define MT8186_TOPRGU_CAM_MAIN_SW_RST 1827#define MT8186_TOPRGU_CAM_RAWA_SW_RST 1928#define MT8186_TOPRGU_CAM_RAWB_SW_RST 2029#define MT8186_TOPRGU_IPE_SW_RST 2130#define MT8186_TOPRGU_IMG2_SW_RST 2231#define MT8186_TOPRGU_SW_RST_NUM 233233/* MMSYS resets */34#define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 193536/* INFRA resets */37#define MT8186_INFRA_THERMAL_CTRL_RST 038#define MT8186_INFRA_PTP_CTRL_RST 13940#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */414243