Path: blob/main/sys/contrib/edk2/Include/Protocol/CpuIo2.h
96339 views
/** @file1This files describes the CPU I/O 2 Protocol.23This protocol provides an I/O abstraction for a system processor. This protocol4is used by a PCI root bridge I/O driver to perform memory-mapped I/O and I/O transactions.5The I/O or memory primitives can be used by the consumer of the protocol to materialize6bus-specific configuration cycles, such as the transitional configuration address and data7ports for PCI. Only drivers that require direct access to the entire system should use this8protocol.910Note: This is a boot-services only protocol and it may not be used by runtime drivers after11ExitBootServices(). It is different from the Framework CPU I/O Protocol, which is a runtime12protocol and can be used by runtime drivers after ExitBootServices().1314Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>15SPDX-License-Identifier: BSD-2-Clause-Patent1617@par Revision Reference:18This Protocol is defined in UEFI Platform Initialization Specification 1.219Volume 5: Standards2021**/2223#ifndef __CPU_IO2_H__24#define __CPU_IO2_H__2526#define EFI_CPU_IO2_PROTOCOL_GUID \27{ \280xad61f191, 0xae5f, 0x4c0e, {0xb9, 0xfa, 0xe8, 0x69, 0xd2, 0x88, 0xc6, 0x4f} \29}3031typedef struct _EFI_CPU_IO2_PROTOCOL EFI_CPU_IO2_PROTOCOL;3233///34/// Enumeration that defines the width of the I/O operation.35///36typedef enum {37EfiCpuIoWidthUint8,38EfiCpuIoWidthUint16,39EfiCpuIoWidthUint32,40EfiCpuIoWidthUint64,41EfiCpuIoWidthFifoUint8,42EfiCpuIoWidthFifoUint16,43EfiCpuIoWidthFifoUint32,44EfiCpuIoWidthFifoUint64,45EfiCpuIoWidthFillUint8,46EfiCpuIoWidthFillUint16,47EfiCpuIoWidthFillUint32,48EfiCpuIoWidthFillUint64,49EfiCpuIoWidthMaximum50} EFI_CPU_IO_PROTOCOL_WIDTH;5152/**53Enables a driver to access registers in the PI CPU I/O space.5455The Io.Read() and Io.Write() functions enable a driver to access PCI controller56registers in the PI CPU I/O space.5758The I/O operations are carried out exactly as requested. The caller is responsible59for satisfying any alignment and I/O width restrictions that a PI System on a60platform might require. For example on some platforms, width requests of61EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will62be handled by the driver.6364If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,65or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for66each of the Count operations that is performed.6768If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,69EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is70incremented for each of the Count operations that is performed. The read or71write operation is performed Count times on the same Address.7273If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,74EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is75incremented for each of the Count operations that is performed. The read or76write operation is performed Count times from the first element of Buffer.7778@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.79@param[in] Width Signifies the width of the I/O or Memory operation.80@param[in] Address The base address of the I/O operation.81@param[in] Count The number of I/O operations to perform. The number82of bytes moved is Width size * Count, starting at Address.83@param[in, out] Buffer For read operations, the destination buffer to store the results.84For write operations, the source buffer from which to write data.8586@retval EFI_SUCCESS The data was read from or written to the PI system.87@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.88@retval EFI_INVALID_PARAMETER Buffer is NULL.89@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.90@retval EFI_UNSUPPORTED The address range specified by Address, Width,91and Count is not valid for this PI system.9293**/94typedef95EFI_STATUS96(EFIAPI *EFI_CPU_IO_PROTOCOL_IO_MEM)(97IN EFI_CPU_IO2_PROTOCOL *This,98IN EFI_CPU_IO_PROTOCOL_WIDTH Width,99IN UINT64 Address,100IN UINTN Count,101IN OUT VOID *Buffer102);103104///105/// Service for read and write accesses.106///107typedef struct {108///109/// This service provides the various modalities of memory and I/O read.110///111EFI_CPU_IO_PROTOCOL_IO_MEM Read;112///113/// This service provides the various modalities of memory and I/O write.114///115EFI_CPU_IO_PROTOCOL_IO_MEM Write;116} EFI_CPU_IO_PROTOCOL_ACCESS;117118///119/// Provides the basic memory and I/O interfaces that are used to abstract120/// accesses to devices in a system.121///122struct _EFI_CPU_IO2_PROTOCOL {123///124/// Enables a driver to access memory-mapped registers in the EFI system memory space.125///126EFI_CPU_IO_PROTOCOL_ACCESS Mem;127///128/// Enables a driver to access registers in the EFI CPU I/O space.129///130EFI_CPU_IO_PROTOCOL_ACCESS Io;131};132133extern EFI_GUID gEfiCpuIo2ProtocolGuid;134135#endif136137138