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freebsd
GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/contrib/ncsw/Peripherals/FM/fm.h
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/*
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* Copyright 2008-2012 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/******************************************************************************
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@File fm.h
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@Description FM internal structures and definitions.
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*//***************************************************************************/
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#ifndef __FM_H
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#define __FM_H
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#include "error_ext.h"
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#include "std_ext.h"
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#include "fm_ext.h"
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#include "fm_ipc.h"
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#include "fsl_fman.h"
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#define __ERR_MODULE__ MODULE_FM
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#define FM_MAX_NUM_OF_HW_PORT_IDS 64
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#define FM_MAX_NUM_OF_GUESTS 100
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/**************************************************************************//**
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@Description Exceptions
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*//***************************************************************************/
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#define FM_EX_DMA_BUS_ERROR 0x80000000 /**< DMA bus error. */
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#define FM_EX_DMA_READ_ECC 0x40000000
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#define FM_EX_DMA_SYSTEM_WRITE_ECC 0x20000000
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#define FM_EX_DMA_FM_WRITE_ECC 0x10000000
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#define FM_EX_FPM_STALL_ON_TASKS 0x08000000 /**< Stall of tasks on FPM */
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#define FM_EX_FPM_SINGLE_ECC 0x04000000 /**< Single ECC on FPM */
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#define FM_EX_FPM_DOUBLE_ECC 0x02000000
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#define FM_EX_QMI_SINGLE_ECC 0x01000000 /**< Single ECC on FPM */
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#define FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000 /**< Dequeu from default queue id */
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#define FM_EX_QMI_DOUBLE_ECC 0x00400000
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#define FM_EX_BMI_LIST_RAM_ECC 0x00200000
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#define FM_EX_BMI_STORAGE_PROFILE_ECC 0x00100000
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#define FM_EX_BMI_STATISTICS_RAM_ECC 0x00080000
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#define FM_EX_IRAM_ECC 0x00040000
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#define FM_EX_MURAM_ECC 0x00020000
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#define FM_EX_BMI_DISPATCH_RAM_ECC 0x00010000
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#define FM_EX_DMA_SINGLE_PORT_ECC 0x00008000
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#define DMA_EMSR_EMSTR_MASK 0x0000FFFF
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#define DMA_THRESH_COMMQ_MASK 0xFF000000
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#define DMA_THRESH_READ_INT_BUF_MASK 0x007F0000
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#define DMA_THRESH_WRITE_INT_BUF_MASK 0x0000007F
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#define GET_EXCEPTION_FLAG(bitMask, exception) \
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switch (exception){ \
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case e_FM_EX_DMA_BUS_ERROR: \
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bitMask = FM_EX_DMA_BUS_ERROR; break; \
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case e_FM_EX_DMA_SINGLE_PORT_ECC: \
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bitMask = FM_EX_DMA_SINGLE_PORT_ECC; break; \
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case e_FM_EX_DMA_READ_ECC: \
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bitMask = FM_EX_DMA_READ_ECC; break; \
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case e_FM_EX_DMA_SYSTEM_WRITE_ECC: \
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bitMask = FM_EX_DMA_SYSTEM_WRITE_ECC; break; \
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case e_FM_EX_DMA_FM_WRITE_ECC: \
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bitMask = FM_EX_DMA_FM_WRITE_ECC; break; \
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case e_FM_EX_FPM_STALL_ON_TASKS: \
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bitMask = FM_EX_FPM_STALL_ON_TASKS; break; \
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case e_FM_EX_FPM_SINGLE_ECC: \
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bitMask = FM_EX_FPM_SINGLE_ECC; break; \
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case e_FM_EX_FPM_DOUBLE_ECC: \
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bitMask = FM_EX_FPM_DOUBLE_ECC; break; \
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case e_FM_EX_QMI_SINGLE_ECC: \
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bitMask = FM_EX_QMI_SINGLE_ECC; break; \
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case e_FM_EX_QMI_DOUBLE_ECC: \
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bitMask = FM_EX_QMI_DOUBLE_ECC; break; \
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case e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: \
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bitMask = FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID; break; \
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case e_FM_EX_BMI_LIST_RAM_ECC: \
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bitMask = FM_EX_BMI_LIST_RAM_ECC; break; \
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case e_FM_EX_BMI_STORAGE_PROFILE_ECC: \
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bitMask = FM_EX_BMI_STORAGE_PROFILE_ECC; break; \
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case e_FM_EX_BMI_STATISTICS_RAM_ECC: \
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bitMask = FM_EX_BMI_STATISTICS_RAM_ECC; break; \
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case e_FM_EX_BMI_DISPATCH_RAM_ECC: \
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bitMask = FM_EX_BMI_DISPATCH_RAM_ECC; break; \
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case e_FM_EX_IRAM_ECC: \
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bitMask = FM_EX_IRAM_ECC; break; \
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case e_FM_EX_MURAM_ECC: \
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bitMask = FM_EX_MURAM_ECC; break; \
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default: bitMask = 0;break; \
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}
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#define GET_FM_MODULE_EVENT(_mod, _id, _intrType, _event) \
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switch (_mod) { \
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case e_FM_MOD_PRS: \
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if (_id) _event = e_FM_EV_DUMMY_LAST; \
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else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PRS : e_FM_EV_PRS; \
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break; \
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case e_FM_MOD_KG: \
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if (_id) _event = e_FM_EV_DUMMY_LAST; \
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else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_KG : e_FM_EV_DUMMY_LAST; \
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break; \
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case e_FM_MOD_PLCR: \
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if (_id) _event = e_FM_EV_DUMMY_LAST; \
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else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PLCR : e_FM_EV_PLCR; \
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break; \
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case e_FM_MOD_TMR: \
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if (_id) _event = e_FM_EV_DUMMY_LAST; \
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else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_TMR; \
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break; \
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case e_FM_MOD_10G_MAC: \
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if (_id >= FM_MAX_NUM_OF_10G_MACS) _event = e_FM_EV_DUMMY_LAST; \
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else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? (e_FM_EV_ERR_10G_MAC0 + _id) : (e_FM_EV_10G_MAC0 + _id); \
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break; \
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case e_FM_MOD_1G_MAC: \
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if (_id >= FM_MAX_NUM_OF_1G_MACS) _event = e_FM_EV_DUMMY_LAST; \
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else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? (e_FM_EV_ERR_1G_MAC0 + _id) : (e_FM_EV_1G_MAC0 + _id); \
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break; \
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case e_FM_MOD_MACSEC: \
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switch (_id){ \
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case (0): _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_MACSEC_MAC0:e_FM_EV_MACSEC_MAC0; \
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break; \
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} \
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break; \
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case e_FM_MOD_FMAN_CTRL: \
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if (_intrType == e_FM_INTR_TYPE_ERR) _event = e_FM_EV_DUMMY_LAST; \
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else _event = (e_FM_EV_FMAN_CTRL_0 + _id); \
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break; \
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default: _event = e_FM_EV_DUMMY_LAST; \
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break; \
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}
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#define FMAN_CACHE_OVERRIDE_TRANS(fsl_cache_override, _cache_override) \
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switch (_cache_override){ \
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case e_FM_DMA_NO_CACHE_OR: \
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fsl_cache_override = E_FMAN_DMA_NO_CACHE_OR; break; \
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case e_FM_DMA_NO_STASH_DATA: \
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fsl_cache_override = E_FMAN_DMA_NO_STASH_DATA; break; \
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case e_FM_DMA_MAY_STASH_DATA: \
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fsl_cache_override = E_FMAN_DMA_MAY_STASH_DATA; break; \
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case e_FM_DMA_STASH_DATA: \
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fsl_cache_override = E_FMAN_DMA_STASH_DATA; break; \
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default: \
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fsl_cache_override = E_FMAN_DMA_NO_CACHE_OR; break; \
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}
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#define FMAN_AID_MODE_TRANS(fsl_aid_mode, _aid_mode) \
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switch (_aid_mode){ \
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case e_FM_DMA_AID_OUT_PORT_ID: \
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fsl_aid_mode = E_FMAN_DMA_AID_OUT_PORT_ID; break; \
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case e_FM_DMA_AID_OUT_TNUM: \
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fsl_aid_mode = E_FMAN_DMA_AID_OUT_TNUM; break; \
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default: \
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fsl_aid_mode = E_FMAN_DMA_AID_OUT_PORT_ID; break; \
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}
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#define FMAN_DMA_DBG_CNT_TRANS(fsl_dma_dbg_cnt, _dma_dbg_cnt) \
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switch (_dma_dbg_cnt){ \
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case e_FM_DMA_DBG_NO_CNT: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_NO_CNT; break; \
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case e_FM_DMA_DBG_CNT_DONE: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_DONE; break; \
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case e_FM_DMA_DBG_CNT_COMM_Q_EM: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_COMM_Q_EM; break; \
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case e_FM_DMA_DBG_CNT_INT_READ_EM: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_INT_READ_EM; break; \
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case e_FM_DMA_DBG_CNT_INT_WRITE_EM: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_INT_WRITE_EM ; break; \
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case e_FM_DMA_DBG_CNT_FPM_WAIT: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_FPM_WAIT ; break; \
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case e_FM_DMA_DBG_CNT_SIGLE_BIT_ECC: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_SIGLE_BIT_ECC ; break; \
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case e_FM_DMA_DBG_CNT_RAW_WAR_PROT: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_RAW_WAR_PROT ; break; \
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default: \
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fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_NO_CNT; break; \
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}
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#define FMAN_DMA_EMER_TRANS(fsl_dma_emer, _dma_emer) \
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switch (_dma_emer){ \
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case e_FM_DMA_EM_EBS: \
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fsl_dma_emer = E_FMAN_DMA_EM_EBS; break; \
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case e_FM_DMA_EM_SOS: \
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fsl_dma_emer = E_FMAN_DMA_EM_SOS; break; \
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default: \
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fsl_dma_emer = E_FMAN_DMA_EM_EBS; break; \
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}
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#define FMAN_DMA_ERR_TRANS(fsl_dma_err, _dma_err) \
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switch (_dma_err){ \
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case e_FM_DMA_ERR_CATASTROPHIC: \
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fsl_dma_err = E_FMAN_DMA_ERR_CATASTROPHIC; break; \
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case e_FM_DMA_ERR_REPORT: \
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fsl_dma_err = E_FMAN_DMA_ERR_REPORT; break; \
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default: \
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fsl_dma_err = E_FMAN_DMA_ERR_CATASTROPHIC; break; \
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}
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#define FMAN_CATASTROPHIC_ERR_TRANS(fsl_catastrophic_err, _catastrophic_err) \
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switch (_catastrophic_err){ \
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case e_FM_CATASTROPHIC_ERR_STALL_PORT: \
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fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_PORT; break; \
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case e_FM_CATASTROPHIC_ERR_STALL_TASK: \
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fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_TASK; break; \
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default: \
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fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_PORT; break; \
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}
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#define FMAN_COUNTERS_TRANS(fsl_counters, _counters) \
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switch (_counters){ \
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case e_FM_COUNTERS_ENQ_TOTAL_FRAME: \
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fsl_counters = E_FMAN_COUNTERS_ENQ_TOTAL_FRAME; break; \
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case e_FM_COUNTERS_DEQ_TOTAL_FRAME: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_TOTAL_FRAME; break; \
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case e_FM_COUNTERS_DEQ_0: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_0; break; \
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case e_FM_COUNTERS_DEQ_1: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_1; break; \
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case e_FM_COUNTERS_DEQ_2: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_2; break; \
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case e_FM_COUNTERS_DEQ_3: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_3; break; \
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case e_FM_COUNTERS_DEQ_FROM_DEFAULT: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_DEFAULT; break; \
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case e_FM_COUNTERS_DEQ_FROM_CONTEXT: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_CONTEXT; break; \
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case e_FM_COUNTERS_DEQ_FROM_FD: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_FD; break; \
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case e_FM_COUNTERS_DEQ_CONFIRM: \
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fsl_counters = E_FMAN_COUNTERS_DEQ_CONFIRM; break; \
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default: \
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fsl_counters = E_FMAN_COUNTERS_ENQ_TOTAL_FRAME; break; \
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}
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/**************************************************************************//**
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@Description defaults
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*//***************************************************************************/
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#define DEFAULT_exceptions (FM_EX_DMA_BUS_ERROR |\
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FM_EX_DMA_READ_ECC |\
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FM_EX_DMA_SYSTEM_WRITE_ECC |\
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FM_EX_DMA_FM_WRITE_ECC |\
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FM_EX_FPM_STALL_ON_TASKS |\
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FM_EX_FPM_SINGLE_ECC |\
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FM_EX_FPM_DOUBLE_ECC |\
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FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID|\
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FM_EX_BMI_LIST_RAM_ECC |\
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FM_EX_BMI_STORAGE_PROFILE_ECC |\
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FM_EX_BMI_STATISTICS_RAM_ECC |\
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FM_EX_IRAM_ECC |\
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FM_EX_MURAM_ECC |\
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FM_EX_BMI_DISPATCH_RAM_ECC |\
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FM_EX_QMI_DOUBLE_ECC |\
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FM_EX_QMI_SINGLE_ECC)
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#define DEFAULT_eccEnable FALSE
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#ifdef FM_PEDANTIC_DMA
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#define DEFAULT_aidOverride TRUE
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#else
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#define DEFAULT_aidOverride FALSE
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#endif /* FM_PEDANTIC_DMA */
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#define DEFAULT_aidMode e_FM_DMA_AID_OUT_TNUM
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#define DEFAULT_dmaStopOnBusError FALSE
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#define DEFAULT_stopAtBusError FALSE
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#define DEFAULT_axiDbgNumOfBeats 1
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#define DEFAULT_dmaReadIntBufLow ((DMA_THRESH_MAX_BUF+1)/2)
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#define DEFAULT_dmaReadIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4)
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#define DEFAULT_dmaWriteIntBufLow ((DMA_THRESH_MAX_BUF+1)/2)
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#define DEFAULT_dmaWriteIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4)
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#define DEFAULT_catastrophicErr e_FM_CATASTROPHIC_ERR_STALL_PORT
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#define DEFAULT_dmaErr e_FM_DMA_ERR_CATASTROPHIC
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#define DEFAULT_resetOnInit FALSE
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#define DEFAULT_resetOnInitOverrideCallback NULL
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#define DEFAULT_haltOnExternalActivation FALSE /* do not change! if changed, must be disabled for rev1 ! */
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#define DEFAULT_haltOnUnrecoverableEccError FALSE /* do not change! if changed, must be disabled for rev1 ! */
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#define DEFAULT_externalEccRamsEnable FALSE
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#define DEFAULT_VerifyUcode FALSE
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#if (DPAA_VERSION < 11)
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#define DEFAULT_totalFifoSize(major, minor) \
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(((major == 2) || (major == 5)) ? \
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(100*KILOBYTE) : ((major == 4) ? \
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(49*KILOBYTE) : (122*KILOBYTE)))
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#define DEFAULT_totalNumOfTasks(major, minor) \
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BMI_MAX_NUM_OF_TASKS
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#define DEFAULT_dmaCommQLow ((DMA_THRESH_MAX_COMMQ+1)/2)
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#define DEFAULT_dmaCommQHigh ((DMA_THRESH_MAX_COMMQ+1)*3/4)
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#define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR
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#define DEFAULT_dmaCamNumOfEntries 32
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#define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT
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#define DEFAULT_dmaEnEmergency FALSE
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#define DEFAULT_dmaSosEmergency 0
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#define DEFAULT_dmaWatchdog 0 /* disabled */
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#define DEFAULT_dmaEnEmergencySmoother FALSE
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#define DEFAULT_dmaEmergencySwitchCounter 0
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#define DEFAULT_dispLimit 0
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#define DEFAULT_prsDispTh 16
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#define DEFAULT_plcrDispTh 16
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#define DEFAULT_kgDispTh 16
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#define DEFAULT_bmiDispTh 16
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#define DEFAULT_qmiEnqDispTh 16
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#define DEFAULT_qmiDeqDispTh 16
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#define DEFAULT_fmCtl1DispTh 16
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#define DEFAULT_fmCtl2DispTh 16
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#else /* (DPAA_VERSION < 11) */
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/* Defaults are registers' reset values */
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#define DEFAULT_totalFifoSize(major, minor) \
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(((major == 6) && ((minor == 1) || (minor == 4))) ? \
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(156*KILOBYTE) : (295*KILOBYTE))
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/* According to the default value of FMBM_CFG2[TNTSKS] */
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#define DEFAULT_totalNumOfTasks(major, minor) \
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(((major == 6) && ((minor == 1) || (minor == 4))) ? 59 : 124)
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#define DEFAULT_dmaCommQLow 0x2A
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#define DEFAULT_dmaCommQHigh 0x3F
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#define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR
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#define DEFAULT_dmaCamNumOfEntries 64
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#define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT
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#define DEFAULT_dmaEnEmergency FALSE
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#define DEFAULT_dmaSosEmergency 0
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#define DEFAULT_dmaWatchdog 0 /* disabled */
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#define DEFAULT_dmaEnEmergencySmoother FALSE
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#define DEFAULT_dmaEmergencySwitchCounter 0
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#define DEFAULT_dispLimit 0
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#define DEFAULT_prsDispTh 16
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#define DEFAULT_plcrDispTh 16
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#define DEFAULT_kgDispTh 16
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#define DEFAULT_bmiDispTh 16
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#define DEFAULT_qmiEnqDispTh 16
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#define DEFAULT_qmiDeqDispTh 16
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#define DEFAULT_fmCtl1DispTh 16
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#define DEFAULT_fmCtl2DispTh 16
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#endif /* (DPAA_VERSION < 11) */
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#define FM_TIMESTAMP_1_USEC_BIT 8
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/**************************************************************************//**
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@Collection Defines used for enabling/disabling FM interrupts
370
@{
371
*//***************************************************************************/
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#define ERR_INTR_EN_DMA 0x00010000
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#define ERR_INTR_EN_FPM 0x80000000
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#define ERR_INTR_EN_BMI 0x00800000
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#define ERR_INTR_EN_QMI 0x00400000
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#define ERR_INTR_EN_PRS 0x00200000
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#define ERR_INTR_EN_KG 0x00100000
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#define ERR_INTR_EN_PLCR 0x00080000
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#define ERR_INTR_EN_MURAM 0x00040000
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#define ERR_INTR_EN_IRAM 0x00020000
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#define ERR_INTR_EN_10G_MAC0 0x00008000
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#define ERR_INTR_EN_10G_MAC1 0x00000040
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#define ERR_INTR_EN_1G_MAC0 0x00004000
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#define ERR_INTR_EN_1G_MAC1 0x00002000
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#define ERR_INTR_EN_1G_MAC2 0x00001000
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#define ERR_INTR_EN_1G_MAC3 0x00000800
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#define ERR_INTR_EN_1G_MAC4 0x00000400
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#define ERR_INTR_EN_1G_MAC5 0x00000200
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#define ERR_INTR_EN_1G_MAC6 0x00000100
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#define ERR_INTR_EN_1G_MAC7 0x00000080
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#define ERR_INTR_EN_MACSEC_MAC0 0x00000001
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#define INTR_EN_QMI 0x40000000
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#define INTR_EN_PRS 0x20000000
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#define INTR_EN_WAKEUP 0x10000000
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#define INTR_EN_PLCR 0x08000000
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#define INTR_EN_1G_MAC0 0x00080000
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#define INTR_EN_1G_MAC1 0x00040000
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#define INTR_EN_1G_MAC2 0x00020000
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#define INTR_EN_1G_MAC3 0x00010000
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#define INTR_EN_1G_MAC4 0x00000040
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#define INTR_EN_1G_MAC5 0x00000020
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#define INTR_EN_1G_MAC6 0x00000008
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#define INTR_EN_1G_MAC7 0x00000002
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#define INTR_EN_10G_MAC0 0x00200000
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#define INTR_EN_10G_MAC1 0x00100000
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#define INTR_EN_REV0 0x00008000
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#define INTR_EN_REV1 0x00004000
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#define INTR_EN_REV2 0x00002000
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#define INTR_EN_REV3 0x00001000
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#define INTR_EN_BRK 0x00000080
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#define INTR_EN_TMR 0x01000000
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#define INTR_EN_MACSEC_MAC0 0x00000001
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/* @} */
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/**************************************************************************//**
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@Description Memory Mapped Registers
418
*//***************************************************************************/
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420
#if defined(__MWERKS__) && !defined(__GNUC__)
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#pragma pack(push,1)
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#endif /* defined(__MWERKS__) && ... */
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424
typedef struct
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{
426
volatile uint32_t iadd; /**< FM IRAM instruction address register */
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volatile uint32_t idata; /**< FM IRAM instruction data register */
428
volatile uint32_t itcfg; /**< FM IRAM timing config register */
429
volatile uint32_t iready; /**< FM IRAM ready register */
430
volatile uint32_t res[0x1FFFC];
431
} t_FMIramRegs;
432
433
/* Trace buffer registers -
434
each FM Controller has its own trace buffer residing at FM_MM_TRB(fmCtrlIndex) offset */
435
typedef struct t_FmTrbRegs
436
{
437
volatile uint32_t tcrh;
438
volatile uint32_t tcrl;
439
volatile uint32_t tesr;
440
volatile uint32_t tecr0h;
441
volatile uint32_t tecr0l;
442
volatile uint32_t terf0h;
443
volatile uint32_t terf0l;
444
volatile uint32_t tecr1h;
445
volatile uint32_t tecr1l;
446
volatile uint32_t terf1h;
447
volatile uint32_t terf1l;
448
volatile uint32_t tpcch;
449
volatile uint32_t tpccl;
450
volatile uint32_t tpc1h;
451
volatile uint32_t tpc1l;
452
volatile uint32_t tpc2h;
453
volatile uint32_t tpc2l;
454
volatile uint32_t twdimr;
455
volatile uint32_t twicvr;
456
volatile uint32_t tar;
457
volatile uint32_t tdr;
458
volatile uint32_t tsnum1;
459
volatile uint32_t tsnum2;
460
volatile uint32_t tsnum3;
461
volatile uint32_t tsnum4;
462
} t_FmTrbRegs;
463
464
#if defined(__MWERKS__) && !defined(__GNUC__)
465
#pragma pack(pop)
466
#endif /* defined(__MWERKS__) && ... */
467
468
/**************************************************************************//**
469
@Description General defines
470
*//***************************************************************************/
471
#define FM_DEBUG_STATUS_REGISTER_OFFSET 0x000d1084UL
472
#define FM_FW_DEBUG_INSTRUCTION 0x6ffff805UL
473
474
/**************************************************************************//**
475
@Description FPM defines
476
*//***************************************************************************/
477
/* masks */
478
#define FPM_BRKC_RDBG 0x00000200
479
#define FPM_BRKC_SLP 0x00000800
480
/**************************************************************************//**
481
@Description BMI defines
482
*//***************************************************************************/
483
/* masks */
484
#define BMI_INIT_START 0x80000000
485
#define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC 0x80000000
486
#define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000
487
#define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000
488
#define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000
489
/**************************************************************************//**
490
@Description QMI defines
491
*//***************************************************************************/
492
/* masks */
493
#define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000
494
#define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000
495
#define QMI_INTR_EN_SINGLE_ECC 0x80000000
496
497
/**************************************************************************//**
498
@Description IRAM defines
499
*//***************************************************************************/
500
/* masks */
501
#define IRAM_IADD_AIE 0x80000000
502
#define IRAM_READY 0x80000000
503
504
/**************************************************************************//**
505
@Description TRB defines
506
*//***************************************************************************/
507
/* masks */
508
#define TRB_TCRH_RESET 0x04000000
509
#define TRB_TCRH_ENABLE_COUNTERS 0x84008000
510
#define TRB_TCRH_DISABLE_COUNTERS 0x8400C000
511
#define TRB_TCRL_RESET 0x20000000
512
#define TRB_TCRL_UTIL 0x00000460
513
typedef struct {
514
void (*f_Isr) (t_Handle h_Arg, uint32_t event);
515
t_Handle h_SrcHandle;
516
} t_FmanCtrlIntrSrc;
517
518
519
typedef void (t_FmanCtrlIsr)( t_Handle h_Fm, uint32_t event);
520
521
typedef struct
522
{
523
/***************************/
524
/* Master/Guest parameters */
525
/***************************/
526
uint8_t fmId;
527
e_FmPortType portsTypes[FM_MAX_NUM_OF_HW_PORT_IDS];
528
uint16_t fmClkFreq;
529
uint16_t fmMacClkFreq;
530
t_FmRevisionInfo revInfo;
531
/**************************/
532
/* Master Only parameters */
533
/**************************/
534
bool enabledTimeStamp;
535
uint8_t count1MicroBit;
536
uint8_t totalNumOfTasks;
537
uint32_t totalFifoSize;
538
uint8_t maxNumOfOpenDmas;
539
uint8_t accumulatedNumOfTasks;
540
uint32_t accumulatedFifoSize;
541
uint8_t accumulatedNumOfOpenDmas;
542
uint8_t accumulatedNumOfDeqTnums;
543
#ifdef FM_LOW_END_RESTRICTION
544
bool lowEndRestriction;
545
#endif /* FM_LOW_END_RESTRICTION */
546
uint32_t exceptions;
547
uintptr_t irq;
548
uintptr_t errIrq;
549
bool ramsEccEnable;
550
bool explicitEnable;
551
bool internalCall;
552
uint8_t ramsEccOwners;
553
uint32_t extraFifoPoolSize;
554
uint8_t extraTasksPoolSize;
555
uint8_t extraOpenDmasPoolSize;
556
#if defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS)
557
uint16_t portMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS];
558
uint16_t macMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS];
559
#endif /* defined(FM_MAX_NUM_OF_10G_MACS) && ... */
560
uint16_t portMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS];
561
uint16_t macMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS];
562
} t_FmStateStruct;
563
564
#if (DPAA_VERSION >= 11)
565
typedef struct t_FmMapParam {
566
uint16_t profilesBase;
567
uint16_t numOfProfiles;
568
t_Handle h_FmPort;
569
} t_FmMapParam;
570
571
typedef struct t_FmAllocMng {
572
bool allocated;
573
uint8_t ownerId; /* guestId for KG in multi-partition only,
574
portId for PLCR in any environment */
575
} t_FmAllocMng;
576
577
typedef struct t_FmPcdSpEntry {
578
bool valid;
579
t_FmAllocMng profilesMng;
580
} t_FmPcdSpEntry;
581
582
typedef struct t_FmSp {
583
void *p_FmPcdStoragePrflRegs;
584
t_FmPcdSpEntry profiles[FM_VSP_MAX_NUM_OF_ENTRIES];
585
t_FmMapParam portsMapping[FM_MAX_NUM_OF_PORTS];
586
} t_FmSp;
587
#endif /* (DPAA_VERSION >= 11) */
588
589
typedef struct t_Fm
590
{
591
/***************************/
592
/* Master/Guest parameters */
593
/***************************/
594
/* locals for recovery */
595
uintptr_t baseAddr;
596
597
/* un-needed for recovery */
598
t_Handle h_Pcd;
599
char fmModuleName[MODULE_NAME_SIZE];
600
char fmIpcHandlerModuleName[FM_MAX_NUM_OF_GUESTS][MODULE_NAME_SIZE];
601
t_Handle h_IpcSessions[FM_MAX_NUM_OF_GUESTS];
602
t_FmIntrSrc intrMng[e_FM_EV_DUMMY_LAST]; /* FM exceptions user callback */
603
uint8_t guestId;
604
/**************************/
605
/* Master Only parameters */
606
/**************************/
607
/* locals for recovery */
608
struct fman_fpm_regs *p_FmFpmRegs;
609
struct fman_bmi_regs *p_FmBmiRegs;
610
struct fman_qmi_regs *p_FmQmiRegs;
611
struct fman_dma_regs *p_FmDmaRegs;
612
struct fman_regs *p_FmRegs;
613
t_FmExceptionsCallback *f_Exception;
614
t_FmBusErrorCallback *f_BusError;
615
t_Handle h_App; /* Application handle */
616
t_Handle h_Spinlock;
617
bool recoveryMode;
618
t_FmStateStruct *p_FmStateStruct;
619
uint16_t tnumAgingPeriod;
620
#if (DPAA_VERSION >= 11)
621
t_FmSp *p_FmSp;
622
uint8_t partNumOfVSPs;
623
uint8_t partVSPBase;
624
uintptr_t vspBaseAddr;
625
#endif /* (DPAA_VERSION >= 11) */
626
bool portsPreFetchConfigured[FM_MAX_NUM_OF_HW_PORT_IDS]; /* Prefetch configration per Tx-port */
627
bool portsPreFetchValue[FM_MAX_NUM_OF_HW_PORT_IDS]; /* Prefetch configration per Tx-port */
628
629
/* un-needed for recovery */
630
struct fman_cfg *p_FmDriverParam;
631
t_Handle h_FmMuram;
632
uint64_t fmMuramPhysBaseAddr;
633
bool independentMode;
634
bool hcPortInitialized;
635
uintptr_t camBaseAddr; /* save for freeing */
636
uintptr_t resAddr;
637
uintptr_t fifoBaseAddr; /* save for freeing */
638
t_FmanCtrlIntrSrc fmanCtrlIntr[FM_NUM_OF_FMAN_CTRL_EVENT_REGS]; /* FM exceptions user callback */
639
bool usedEventRegs[FM_NUM_OF_FMAN_CTRL_EVENT_REGS];
640
t_FmFirmwareParams firmware;
641
bool fwVerify;
642
bool resetOnInit;
643
t_FmResetOnInitOverrideCallback *f_ResetOnInitOverride;
644
uint32_t userSetExceptions;
645
} t_Fm;
646
647
648
#endif /* __FM_H */
649
650