Path: blob/main/sys/contrib/ncsw/Peripherals/FM/fm.h
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/*1* Copyright 2008-2012 Freescale Semiconductor Inc.2*3* Redistribution and use in source and binary forms, with or without4* modification, are permitted provided that the following conditions are met:5* * Redistributions of source code must retain the above copyright6* notice, this list of conditions and the following disclaimer.7* * Redistributions in binary form must reproduce the above copyright8* notice, this list of conditions and the following disclaimer in the9* documentation and/or other materials provided with the distribution.10* * Neither the name of Freescale Semiconductor nor the11* names of its contributors may be used to endorse or promote products12* derived from this software without specific prior written permission.13*14*15* ALTERNATIVELY, this software may be distributed under the terms of the16* GNU General Public License ("GPL") as published by the Free Software17* Foundation, either version 2 of that License or (at your option) any18* later version.19*20* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY21* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED22* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE23* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY24* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES25* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;26* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND27* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT28* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS29* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.30*/313233/******************************************************************************34@File fm.h3536@Description FM internal structures and definitions.37*//***************************************************************************/38#ifndef __FM_H39#define __FM_H4041#include "error_ext.h"42#include "std_ext.h"43#include "fm_ext.h"44#include "fm_ipc.h"4546#include "fsl_fman.h"4748#define __ERR_MODULE__ MODULE_FM4950#define FM_MAX_NUM_OF_HW_PORT_IDS 6451#define FM_MAX_NUM_OF_GUESTS 1005253/**************************************************************************//**54@Description Exceptions55*//***************************************************************************/56#define FM_EX_DMA_BUS_ERROR 0x80000000 /**< DMA bus error. */57#define FM_EX_DMA_READ_ECC 0x4000000058#define FM_EX_DMA_SYSTEM_WRITE_ECC 0x2000000059#define FM_EX_DMA_FM_WRITE_ECC 0x1000000060#define FM_EX_FPM_STALL_ON_TASKS 0x08000000 /**< Stall of tasks on FPM */61#define FM_EX_FPM_SINGLE_ECC 0x04000000 /**< Single ECC on FPM */62#define FM_EX_FPM_DOUBLE_ECC 0x0200000063#define FM_EX_QMI_SINGLE_ECC 0x01000000 /**< Single ECC on FPM */64#define FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000 /**< Dequeu from default queue id */65#define FM_EX_QMI_DOUBLE_ECC 0x0040000066#define FM_EX_BMI_LIST_RAM_ECC 0x0020000067#define FM_EX_BMI_STORAGE_PROFILE_ECC 0x0010000068#define FM_EX_BMI_STATISTICS_RAM_ECC 0x0008000069#define FM_EX_IRAM_ECC 0x0004000070#define FM_EX_MURAM_ECC 0x0002000071#define FM_EX_BMI_DISPATCH_RAM_ECC 0x0001000072#define FM_EX_DMA_SINGLE_PORT_ECC 0x000080007374#define DMA_EMSR_EMSTR_MASK 0x0000FFFF7576#define DMA_THRESH_COMMQ_MASK 0xFF00000077#define DMA_THRESH_READ_INT_BUF_MASK 0x007F000078#define DMA_THRESH_WRITE_INT_BUF_MASK 0x0000007F7980#define GET_EXCEPTION_FLAG(bitMask, exception) \81switch (exception){ \82case e_FM_EX_DMA_BUS_ERROR: \83bitMask = FM_EX_DMA_BUS_ERROR; break; \84case e_FM_EX_DMA_SINGLE_PORT_ECC: \85bitMask = FM_EX_DMA_SINGLE_PORT_ECC; break; \86case e_FM_EX_DMA_READ_ECC: \87bitMask = FM_EX_DMA_READ_ECC; break; \88case e_FM_EX_DMA_SYSTEM_WRITE_ECC: \89bitMask = FM_EX_DMA_SYSTEM_WRITE_ECC; break; \90case e_FM_EX_DMA_FM_WRITE_ECC: \91bitMask = FM_EX_DMA_FM_WRITE_ECC; break; \92case e_FM_EX_FPM_STALL_ON_TASKS: \93bitMask = FM_EX_FPM_STALL_ON_TASKS; break; \94case e_FM_EX_FPM_SINGLE_ECC: \95bitMask = FM_EX_FPM_SINGLE_ECC; break; \96case e_FM_EX_FPM_DOUBLE_ECC: \97bitMask = FM_EX_FPM_DOUBLE_ECC; break; \98case e_FM_EX_QMI_SINGLE_ECC: \99bitMask = FM_EX_QMI_SINGLE_ECC; break; \100case e_FM_EX_QMI_DOUBLE_ECC: \101bitMask = FM_EX_QMI_DOUBLE_ECC; break; \102case e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: \103bitMask = FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID; break; \104case e_FM_EX_BMI_LIST_RAM_ECC: \105bitMask = FM_EX_BMI_LIST_RAM_ECC; break; \106case e_FM_EX_BMI_STORAGE_PROFILE_ECC: \107bitMask = FM_EX_BMI_STORAGE_PROFILE_ECC; break; \108case e_FM_EX_BMI_STATISTICS_RAM_ECC: \109bitMask = FM_EX_BMI_STATISTICS_RAM_ECC; break; \110case e_FM_EX_BMI_DISPATCH_RAM_ECC: \111bitMask = FM_EX_BMI_DISPATCH_RAM_ECC; break; \112case e_FM_EX_IRAM_ECC: \113bitMask = FM_EX_IRAM_ECC; break; \114case e_FM_EX_MURAM_ECC: \115bitMask = FM_EX_MURAM_ECC; break; \116default: bitMask = 0;break; \117}118119#define GET_FM_MODULE_EVENT(_mod, _id, _intrType, _event) \120switch (_mod) { \121case e_FM_MOD_PRS: \122if (_id) _event = e_FM_EV_DUMMY_LAST; \123else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PRS : e_FM_EV_PRS; \124break; \125case e_FM_MOD_KG: \126if (_id) _event = e_FM_EV_DUMMY_LAST; \127else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_KG : e_FM_EV_DUMMY_LAST; \128break; \129case e_FM_MOD_PLCR: \130if (_id) _event = e_FM_EV_DUMMY_LAST; \131else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PLCR : e_FM_EV_PLCR; \132break; \133case e_FM_MOD_TMR: \134if (_id) _event = e_FM_EV_DUMMY_LAST; \135else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_TMR; \136break; \137case e_FM_MOD_10G_MAC: \138if (_id >= FM_MAX_NUM_OF_10G_MACS) _event = e_FM_EV_DUMMY_LAST; \139else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? (e_FM_EV_ERR_10G_MAC0 + _id) : (e_FM_EV_10G_MAC0 + _id); \140break; \141case e_FM_MOD_1G_MAC: \142if (_id >= FM_MAX_NUM_OF_1G_MACS) _event = e_FM_EV_DUMMY_LAST; \143else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? (e_FM_EV_ERR_1G_MAC0 + _id) : (e_FM_EV_1G_MAC0 + _id); \144break; \145case e_FM_MOD_MACSEC: \146switch (_id){ \147case (0): _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_MACSEC_MAC0:e_FM_EV_MACSEC_MAC0; \148break; \149} \150break; \151case e_FM_MOD_FMAN_CTRL: \152if (_intrType == e_FM_INTR_TYPE_ERR) _event = e_FM_EV_DUMMY_LAST; \153else _event = (e_FM_EV_FMAN_CTRL_0 + _id); \154break; \155default: _event = e_FM_EV_DUMMY_LAST; \156break; \157}158159#define FMAN_CACHE_OVERRIDE_TRANS(fsl_cache_override, _cache_override) \160switch (_cache_override){ \161case e_FM_DMA_NO_CACHE_OR: \162fsl_cache_override = E_FMAN_DMA_NO_CACHE_OR; break; \163case e_FM_DMA_NO_STASH_DATA: \164fsl_cache_override = E_FMAN_DMA_NO_STASH_DATA; break; \165case e_FM_DMA_MAY_STASH_DATA: \166fsl_cache_override = E_FMAN_DMA_MAY_STASH_DATA; break; \167case e_FM_DMA_STASH_DATA: \168fsl_cache_override = E_FMAN_DMA_STASH_DATA; break; \169default: \170fsl_cache_override = E_FMAN_DMA_NO_CACHE_OR; break; \171}172173#define FMAN_AID_MODE_TRANS(fsl_aid_mode, _aid_mode) \174switch (_aid_mode){ \175case e_FM_DMA_AID_OUT_PORT_ID: \176fsl_aid_mode = E_FMAN_DMA_AID_OUT_PORT_ID; break; \177case e_FM_DMA_AID_OUT_TNUM: \178fsl_aid_mode = E_FMAN_DMA_AID_OUT_TNUM; break; \179default: \180fsl_aid_mode = E_FMAN_DMA_AID_OUT_PORT_ID; break; \181}182183#define FMAN_DMA_DBG_CNT_TRANS(fsl_dma_dbg_cnt, _dma_dbg_cnt) \184switch (_dma_dbg_cnt){ \185case e_FM_DMA_DBG_NO_CNT: \186fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_NO_CNT; break; \187case e_FM_DMA_DBG_CNT_DONE: \188fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_DONE; break; \189case e_FM_DMA_DBG_CNT_COMM_Q_EM: \190fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_COMM_Q_EM; break; \191case e_FM_DMA_DBG_CNT_INT_READ_EM: \192fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_INT_READ_EM; break; \193case e_FM_DMA_DBG_CNT_INT_WRITE_EM: \194fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_INT_WRITE_EM ; break; \195case e_FM_DMA_DBG_CNT_FPM_WAIT: \196fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_FPM_WAIT ; break; \197case e_FM_DMA_DBG_CNT_SIGLE_BIT_ECC: \198fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_SIGLE_BIT_ECC ; break; \199case e_FM_DMA_DBG_CNT_RAW_WAR_PROT: \200fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_RAW_WAR_PROT ; break; \201default: \202fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_NO_CNT; break; \203}204205#define FMAN_DMA_EMER_TRANS(fsl_dma_emer, _dma_emer) \206switch (_dma_emer){ \207case e_FM_DMA_EM_EBS: \208fsl_dma_emer = E_FMAN_DMA_EM_EBS; break; \209case e_FM_DMA_EM_SOS: \210fsl_dma_emer = E_FMAN_DMA_EM_SOS; break; \211default: \212fsl_dma_emer = E_FMAN_DMA_EM_EBS; break; \213}214215#define FMAN_DMA_ERR_TRANS(fsl_dma_err, _dma_err) \216switch (_dma_err){ \217case e_FM_DMA_ERR_CATASTROPHIC: \218fsl_dma_err = E_FMAN_DMA_ERR_CATASTROPHIC; break; \219case e_FM_DMA_ERR_REPORT: \220fsl_dma_err = E_FMAN_DMA_ERR_REPORT; break; \221default: \222fsl_dma_err = E_FMAN_DMA_ERR_CATASTROPHIC; break; \223}224225#define FMAN_CATASTROPHIC_ERR_TRANS(fsl_catastrophic_err, _catastrophic_err) \226switch (_catastrophic_err){ \227case e_FM_CATASTROPHIC_ERR_STALL_PORT: \228fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_PORT; break; \229case e_FM_CATASTROPHIC_ERR_STALL_TASK: \230fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_TASK; break; \231default: \232fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_PORT; break; \233}234235#define FMAN_COUNTERS_TRANS(fsl_counters, _counters) \236switch (_counters){ \237case e_FM_COUNTERS_ENQ_TOTAL_FRAME: \238fsl_counters = E_FMAN_COUNTERS_ENQ_TOTAL_FRAME; break; \239case e_FM_COUNTERS_DEQ_TOTAL_FRAME: \240fsl_counters = E_FMAN_COUNTERS_DEQ_TOTAL_FRAME; break; \241case e_FM_COUNTERS_DEQ_0: \242fsl_counters = E_FMAN_COUNTERS_DEQ_0; break; \243case e_FM_COUNTERS_DEQ_1: \244fsl_counters = E_FMAN_COUNTERS_DEQ_1; break; \245case e_FM_COUNTERS_DEQ_2: \246fsl_counters = E_FMAN_COUNTERS_DEQ_2; break; \247case e_FM_COUNTERS_DEQ_3: \248fsl_counters = E_FMAN_COUNTERS_DEQ_3; break; \249case e_FM_COUNTERS_DEQ_FROM_DEFAULT: \250fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_DEFAULT; break; \251case e_FM_COUNTERS_DEQ_FROM_CONTEXT: \252fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_CONTEXT; break; \253case e_FM_COUNTERS_DEQ_FROM_FD: \254fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_FD; break; \255case e_FM_COUNTERS_DEQ_CONFIRM: \256fsl_counters = E_FMAN_COUNTERS_DEQ_CONFIRM; break; \257default: \258fsl_counters = E_FMAN_COUNTERS_ENQ_TOTAL_FRAME; break; \259}260261/**************************************************************************//**262@Description defaults263*//***************************************************************************/264#define DEFAULT_exceptions (FM_EX_DMA_BUS_ERROR |\265FM_EX_DMA_READ_ECC |\266FM_EX_DMA_SYSTEM_WRITE_ECC |\267FM_EX_DMA_FM_WRITE_ECC |\268FM_EX_FPM_STALL_ON_TASKS |\269FM_EX_FPM_SINGLE_ECC |\270FM_EX_FPM_DOUBLE_ECC |\271FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID|\272FM_EX_BMI_LIST_RAM_ECC |\273FM_EX_BMI_STORAGE_PROFILE_ECC |\274FM_EX_BMI_STATISTICS_RAM_ECC |\275FM_EX_IRAM_ECC |\276FM_EX_MURAM_ECC |\277FM_EX_BMI_DISPATCH_RAM_ECC |\278FM_EX_QMI_DOUBLE_ECC |\279FM_EX_QMI_SINGLE_ECC)280281#define DEFAULT_eccEnable FALSE282#ifdef FM_PEDANTIC_DMA283#define DEFAULT_aidOverride TRUE284#else285#define DEFAULT_aidOverride FALSE286#endif /* FM_PEDANTIC_DMA */287#define DEFAULT_aidMode e_FM_DMA_AID_OUT_TNUM288#define DEFAULT_dmaStopOnBusError FALSE289#define DEFAULT_stopAtBusError FALSE290#define DEFAULT_axiDbgNumOfBeats 1291#define DEFAULT_dmaReadIntBufLow ((DMA_THRESH_MAX_BUF+1)/2)292#define DEFAULT_dmaReadIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4)293#define DEFAULT_dmaWriteIntBufLow ((DMA_THRESH_MAX_BUF+1)/2)294#define DEFAULT_dmaWriteIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4)295#define DEFAULT_catastrophicErr e_FM_CATASTROPHIC_ERR_STALL_PORT296#define DEFAULT_dmaErr e_FM_DMA_ERR_CATASTROPHIC297#define DEFAULT_resetOnInit FALSE298#define DEFAULT_resetOnInitOverrideCallback NULL299#define DEFAULT_haltOnExternalActivation FALSE /* do not change! if changed, must be disabled for rev1 ! */300#define DEFAULT_haltOnUnrecoverableEccError FALSE /* do not change! if changed, must be disabled for rev1 ! */301#define DEFAULT_externalEccRamsEnable FALSE302#define DEFAULT_VerifyUcode FALSE303304#if (DPAA_VERSION < 11)305#define DEFAULT_totalFifoSize(major, minor) \306(((major == 2) || (major == 5)) ? \307(100*KILOBYTE) : ((major == 4) ? \308(49*KILOBYTE) : (122*KILOBYTE)))309#define DEFAULT_totalNumOfTasks(major, minor) \310BMI_MAX_NUM_OF_TASKS311312#define DEFAULT_dmaCommQLow ((DMA_THRESH_MAX_COMMQ+1)/2)313#define DEFAULT_dmaCommQHigh ((DMA_THRESH_MAX_COMMQ+1)*3/4)314#define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR315#define DEFAULT_dmaCamNumOfEntries 32316#define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT317#define DEFAULT_dmaEnEmergency FALSE318#define DEFAULT_dmaSosEmergency 0319#define DEFAULT_dmaWatchdog 0 /* disabled */320#define DEFAULT_dmaEnEmergencySmoother FALSE321#define DEFAULT_dmaEmergencySwitchCounter 0322323#define DEFAULT_dispLimit 0324#define DEFAULT_prsDispTh 16325#define DEFAULT_plcrDispTh 16326#define DEFAULT_kgDispTh 16327#define DEFAULT_bmiDispTh 16328#define DEFAULT_qmiEnqDispTh 16329#define DEFAULT_qmiDeqDispTh 16330#define DEFAULT_fmCtl1DispTh 16331#define DEFAULT_fmCtl2DispTh 16332333#else /* (DPAA_VERSION < 11) */334/* Defaults are registers' reset values */335#define DEFAULT_totalFifoSize(major, minor) \336(((major == 6) && ((minor == 1) || (minor == 4))) ? \337(156*KILOBYTE) : (295*KILOBYTE))338339/* According to the default value of FMBM_CFG2[TNTSKS] */340#define DEFAULT_totalNumOfTasks(major, minor) \341(((major == 6) && ((minor == 1) || (minor == 4))) ? 59 : 124)342343#define DEFAULT_dmaCommQLow 0x2A344#define DEFAULT_dmaCommQHigh 0x3F345#define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR346#define DEFAULT_dmaCamNumOfEntries 64347#define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT348#define DEFAULT_dmaEnEmergency FALSE349#define DEFAULT_dmaSosEmergency 0350#define DEFAULT_dmaWatchdog 0 /* disabled */351#define DEFAULT_dmaEnEmergencySmoother FALSE352#define DEFAULT_dmaEmergencySwitchCounter 0353354#define DEFAULT_dispLimit 0355#define DEFAULT_prsDispTh 16356#define DEFAULT_plcrDispTh 16357#define DEFAULT_kgDispTh 16358#define DEFAULT_bmiDispTh 16359#define DEFAULT_qmiEnqDispTh 16360#define DEFAULT_qmiDeqDispTh 16361#define DEFAULT_fmCtl1DispTh 16362#define DEFAULT_fmCtl2DispTh 16363#endif /* (DPAA_VERSION < 11) */364365#define FM_TIMESTAMP_1_USEC_BIT 8366367/**************************************************************************//**368@Collection Defines used for enabling/disabling FM interrupts369@{370*//***************************************************************************/371#define ERR_INTR_EN_DMA 0x00010000372#define ERR_INTR_EN_FPM 0x80000000373#define ERR_INTR_EN_BMI 0x00800000374#define ERR_INTR_EN_QMI 0x00400000375#define ERR_INTR_EN_PRS 0x00200000376#define ERR_INTR_EN_KG 0x00100000377#define ERR_INTR_EN_PLCR 0x00080000378#define ERR_INTR_EN_MURAM 0x00040000379#define ERR_INTR_EN_IRAM 0x00020000380#define ERR_INTR_EN_10G_MAC0 0x00008000381#define ERR_INTR_EN_10G_MAC1 0x00000040382#define ERR_INTR_EN_1G_MAC0 0x00004000383#define ERR_INTR_EN_1G_MAC1 0x00002000384#define ERR_INTR_EN_1G_MAC2 0x00001000385#define ERR_INTR_EN_1G_MAC3 0x00000800386#define ERR_INTR_EN_1G_MAC4 0x00000400387#define ERR_INTR_EN_1G_MAC5 0x00000200388#define ERR_INTR_EN_1G_MAC6 0x00000100389#define ERR_INTR_EN_1G_MAC7 0x00000080390#define ERR_INTR_EN_MACSEC_MAC0 0x00000001391392#define INTR_EN_QMI 0x40000000393#define INTR_EN_PRS 0x20000000394#define INTR_EN_WAKEUP 0x10000000395#define INTR_EN_PLCR 0x08000000396#define INTR_EN_1G_MAC0 0x00080000397#define INTR_EN_1G_MAC1 0x00040000398#define INTR_EN_1G_MAC2 0x00020000399#define INTR_EN_1G_MAC3 0x00010000400#define INTR_EN_1G_MAC4 0x00000040401#define INTR_EN_1G_MAC5 0x00000020402#define INTR_EN_1G_MAC6 0x00000008403#define INTR_EN_1G_MAC7 0x00000002404#define INTR_EN_10G_MAC0 0x00200000405#define INTR_EN_10G_MAC1 0x00100000406#define INTR_EN_REV0 0x00008000407#define INTR_EN_REV1 0x00004000408#define INTR_EN_REV2 0x00002000409#define INTR_EN_REV3 0x00001000410#define INTR_EN_BRK 0x00000080411#define INTR_EN_TMR 0x01000000412#define INTR_EN_MACSEC_MAC0 0x00000001413/* @} */414415/**************************************************************************//**416@Description Memory Mapped Registers417*//***************************************************************************/418419#if defined(__MWERKS__) && !defined(__GNUC__)420#pragma pack(push,1)421#endif /* defined(__MWERKS__) && ... */422423typedef struct424{425volatile uint32_t iadd; /**< FM IRAM instruction address register */426volatile uint32_t idata; /**< FM IRAM instruction data register */427volatile uint32_t itcfg; /**< FM IRAM timing config register */428volatile uint32_t iready; /**< FM IRAM ready register */429volatile uint32_t res[0x1FFFC];430} t_FMIramRegs;431432/* Trace buffer registers -433each FM Controller has its own trace buffer residing at FM_MM_TRB(fmCtrlIndex) offset */434typedef struct t_FmTrbRegs435{436volatile uint32_t tcrh;437volatile uint32_t tcrl;438volatile uint32_t tesr;439volatile uint32_t tecr0h;440volatile uint32_t tecr0l;441volatile uint32_t terf0h;442volatile uint32_t terf0l;443volatile uint32_t tecr1h;444volatile uint32_t tecr1l;445volatile uint32_t terf1h;446volatile uint32_t terf1l;447volatile uint32_t tpcch;448volatile uint32_t tpccl;449volatile uint32_t tpc1h;450volatile uint32_t tpc1l;451volatile uint32_t tpc2h;452volatile uint32_t tpc2l;453volatile uint32_t twdimr;454volatile uint32_t twicvr;455volatile uint32_t tar;456volatile uint32_t tdr;457volatile uint32_t tsnum1;458volatile uint32_t tsnum2;459volatile uint32_t tsnum3;460volatile uint32_t tsnum4;461} t_FmTrbRegs;462463#if defined(__MWERKS__) && !defined(__GNUC__)464#pragma pack(pop)465#endif /* defined(__MWERKS__) && ... */466467/**************************************************************************//**468@Description General defines469*//***************************************************************************/470#define FM_DEBUG_STATUS_REGISTER_OFFSET 0x000d1084UL471#define FM_FW_DEBUG_INSTRUCTION 0x6ffff805UL472473/**************************************************************************//**474@Description FPM defines475*//***************************************************************************/476/* masks */477#define FPM_BRKC_RDBG 0x00000200478#define FPM_BRKC_SLP 0x00000800479/**************************************************************************//**480@Description BMI defines481*//***************************************************************************/482/* masks */483#define BMI_INIT_START 0x80000000484#define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC 0x80000000485#define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000486#define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000487#define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000488/**************************************************************************//**489@Description QMI defines490*//***************************************************************************/491/* masks */492#define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000493#define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000494#define QMI_INTR_EN_SINGLE_ECC 0x80000000495496/**************************************************************************//**497@Description IRAM defines498*//***************************************************************************/499/* masks */500#define IRAM_IADD_AIE 0x80000000501#define IRAM_READY 0x80000000502503/**************************************************************************//**504@Description TRB defines505*//***************************************************************************/506/* masks */507#define TRB_TCRH_RESET 0x04000000508#define TRB_TCRH_ENABLE_COUNTERS 0x84008000509#define TRB_TCRH_DISABLE_COUNTERS 0x8400C000510#define TRB_TCRL_RESET 0x20000000511#define TRB_TCRL_UTIL 0x00000460512typedef struct {513void (*f_Isr) (t_Handle h_Arg, uint32_t event);514t_Handle h_SrcHandle;515} t_FmanCtrlIntrSrc;516517518typedef void (t_FmanCtrlIsr)( t_Handle h_Fm, uint32_t event);519520typedef struct521{522/***************************/523/* Master/Guest parameters */524/***************************/525uint8_t fmId;526e_FmPortType portsTypes[FM_MAX_NUM_OF_HW_PORT_IDS];527uint16_t fmClkFreq;528uint16_t fmMacClkFreq;529t_FmRevisionInfo revInfo;530/**************************/531/* Master Only parameters */532/**************************/533bool enabledTimeStamp;534uint8_t count1MicroBit;535uint8_t totalNumOfTasks;536uint32_t totalFifoSize;537uint8_t maxNumOfOpenDmas;538uint8_t accumulatedNumOfTasks;539uint32_t accumulatedFifoSize;540uint8_t accumulatedNumOfOpenDmas;541uint8_t accumulatedNumOfDeqTnums;542#ifdef FM_LOW_END_RESTRICTION543bool lowEndRestriction;544#endif /* FM_LOW_END_RESTRICTION */545uint32_t exceptions;546uintptr_t irq;547uintptr_t errIrq;548bool ramsEccEnable;549bool explicitEnable;550bool internalCall;551uint8_t ramsEccOwners;552uint32_t extraFifoPoolSize;553uint8_t extraTasksPoolSize;554uint8_t extraOpenDmasPoolSize;555#if defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS)556uint16_t portMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS];557uint16_t macMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS];558#endif /* defined(FM_MAX_NUM_OF_10G_MACS) && ... */559uint16_t portMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS];560uint16_t macMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS];561} t_FmStateStruct;562563#if (DPAA_VERSION >= 11)564typedef struct t_FmMapParam {565uint16_t profilesBase;566uint16_t numOfProfiles;567t_Handle h_FmPort;568} t_FmMapParam;569570typedef struct t_FmAllocMng {571bool allocated;572uint8_t ownerId; /* guestId for KG in multi-partition only,573portId for PLCR in any environment */574} t_FmAllocMng;575576typedef struct t_FmPcdSpEntry {577bool valid;578t_FmAllocMng profilesMng;579} t_FmPcdSpEntry;580581typedef struct t_FmSp {582void *p_FmPcdStoragePrflRegs;583t_FmPcdSpEntry profiles[FM_VSP_MAX_NUM_OF_ENTRIES];584t_FmMapParam portsMapping[FM_MAX_NUM_OF_PORTS];585} t_FmSp;586#endif /* (DPAA_VERSION >= 11) */587588typedef struct t_Fm589{590/***************************/591/* Master/Guest parameters */592/***************************/593/* locals for recovery */594uintptr_t baseAddr;595596/* un-needed for recovery */597t_Handle h_Pcd;598char fmModuleName[MODULE_NAME_SIZE];599char fmIpcHandlerModuleName[FM_MAX_NUM_OF_GUESTS][MODULE_NAME_SIZE];600t_Handle h_IpcSessions[FM_MAX_NUM_OF_GUESTS];601t_FmIntrSrc intrMng[e_FM_EV_DUMMY_LAST]; /* FM exceptions user callback */602uint8_t guestId;603/**************************/604/* Master Only parameters */605/**************************/606/* locals for recovery */607struct fman_fpm_regs *p_FmFpmRegs;608struct fman_bmi_regs *p_FmBmiRegs;609struct fman_qmi_regs *p_FmQmiRegs;610struct fman_dma_regs *p_FmDmaRegs;611struct fman_regs *p_FmRegs;612t_FmExceptionsCallback *f_Exception;613t_FmBusErrorCallback *f_BusError;614t_Handle h_App; /* Application handle */615t_Handle h_Spinlock;616bool recoveryMode;617t_FmStateStruct *p_FmStateStruct;618uint16_t tnumAgingPeriod;619#if (DPAA_VERSION >= 11)620t_FmSp *p_FmSp;621uint8_t partNumOfVSPs;622uint8_t partVSPBase;623uintptr_t vspBaseAddr;624#endif /* (DPAA_VERSION >= 11) */625bool portsPreFetchConfigured[FM_MAX_NUM_OF_HW_PORT_IDS]; /* Prefetch configration per Tx-port */626bool portsPreFetchValue[FM_MAX_NUM_OF_HW_PORT_IDS]; /* Prefetch configration per Tx-port */627628/* un-needed for recovery */629struct fman_cfg *p_FmDriverParam;630t_Handle h_FmMuram;631uint64_t fmMuramPhysBaseAddr;632bool independentMode;633bool hcPortInitialized;634uintptr_t camBaseAddr; /* save for freeing */635uintptr_t resAddr;636uintptr_t fifoBaseAddr; /* save for freeing */637t_FmanCtrlIntrSrc fmanCtrlIntr[FM_NUM_OF_FMAN_CTRL_EVENT_REGS]; /* FM exceptions user callback */638bool usedEventRegs[FM_NUM_OF_FMAN_CTRL_EVENT_REGS];639t_FmFirmwareParams firmware;640bool fwVerify;641bool resetOnInit;642t_FmResetOnInitOverrideCallback *f_ResetOnInitOverride;643uint32_t userSetExceptions;644} t_Fm;645646647#endif /* __FM_H */648649650