Path: blob/main/sys/contrib/ncsw/Peripherals/QM/qman_private.h
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/******************************************************************************12� 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.3All rights reserved.45This is proprietary source code of Freescale Semiconductor Inc.,6and its use is subject to the NetComm Device Drivers EULA.7The copyright notice above does not evidence any actual or intended8publication of such source code.910ALTERNATIVELY, redistribution and use in source and binary forms, with11or without modification, are permitted provided that the following12conditions are met:13* Redistributions of source code must retain the above copyright14notice, this list of conditions and the following disclaimer.15* Redistributions in binary form must reproduce the above copyright16notice, this list of conditions and the following disclaimer in the17documentation and/or other materials provided with the distribution.18* Neither the name of Freescale Semiconductor nor the19names of its contributors may be used to endorse or promote products20derived from this software without specific prior written permission.2122THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY23EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED24WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE25DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY26DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES27(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;28LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND29ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT30(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS31SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.32*3334**************************************************************************/35/******************************************************************************36@File qman_private.h3738@Description QM private header39*//***************************************************************************/40#ifndef __QMAN_PRIVATE_H41#define __QMAN_PRIVATE_H4243#include "fsl_qman.h"444546#define __ERR_MODULE__ MODULE_QM4748#if defined(DEBUG) || !defined(DISABLE_ASSERTIONS)49/* Optionally compile-in assertion-checking */50#define QM_CHECKING51#endif /* defined(DEBUG) || ... */5253/* TODO: NB, we currently assume that CORE_MemoryBarier() and lwsync() imply compiler barriers54* and that dcbzl(), dcbfl(), and dcbi() won't fall victim to compiler or55* execution reordering with respect to other code/instructions that manipulate56* the same cacheline. */5758#define dcbf(addr) \59do { \60__asm__ __volatile__ ("dcbf 0, %0" : : "r" (addr)); \61} while(0)6263#ifdef CORE_E500MC64#define dcbt_ro(addr) \65do { \66__asm__ __volatile__ ("dcbt 0, %0" : : "r" (addr)); \67} while(0)6869#define dcbt_rw(addr) \70do { \71__asm__ __volatile__ ("dcbtst 0, %0" : : "r" (addr)); \72} while(0)7374#define dcbzl(p) \75do { \76__asm__ __volatile__ ("dcbzl 0,%0" : : "r" (p)); \77} while(0)7879#define dcbz_64(p) \80do { \81dcbzl(p); \82} while (0)8384#define dcbf_64(p) \85do { \86dcbf(p); \87} while (0)8889/* Commonly used combo */90#define dcbit_ro(p) \91do { \92dcbi(p); \93dcbt_ro(p); \94} while (0)9596#else9798#define dcbt_ro(p) \99do { \100__asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)); \101lwsync(); \102} while(0)103#define dcbt_rw(p) \104do { \105__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (p)); \106} while(0)107#define dcbz(p) \108do { \109__asm__ __volatile__ ("dcbz 0,%0" : : "r" (p)); \110} while (0)111#define dcbz_64(p) \112do { \113dcbz((char *)p + 32); \114dcbz(p); \115} while (0)116#define dcbf_64(p) \117do { \118dcbf((char *)p + 32); \119dcbf(p); \120} while (0)121/* Commonly used combo */122#define dcbit_ro(p) \123do { \124dcbi(p); \125dcbi((char *)p + 32); \126dcbt_ro(p); \127dcbt_ro((char *)p + 32); \128} while (0)129130#endif /* CORE_E500MC */131132#define dcbi(p) dcbf(p)133134struct qm_addr {135void *addr_ce; /* cache-enabled */136void *addr_ci; /* cache-inhibited */137};138139/* EQCR state */140struct qm_eqcr {141struct qm_eqcr_entry *ring, *cursor;142uint8_t ci, available, ithresh, vbit;143144#ifdef QM_CHECKING145uint32_t busy;146e_QmPortalProduceMode pmode;147e_QmPortalEqcrConsumeMode cmode;148#endif /* QM_CHECKING */149};150151/* DQRR state */152struct qm_dqrr {153struct qm_dqrr_entry *ring, *cursor;154uint8_t pi, ci, fill, ithresh, vbit, flags;155156#ifdef QM_CHECKING157e_QmPortalDequeueMode dmode;158e_QmPortalProduceMode pmode;159e_QmPortalDqrrConsumeMode cmode;160#endif /* QM_CHECKING */161};162#define QM_DQRR_FLAG_RE 0x01 /* Stash ring entries */163#define QM_DQRR_FLAG_SE 0x02 /* Stash data */164165/* MR state */166struct qm_mr {167struct qm_mr_entry *ring, *cursor;168uint8_t pi, ci, fill, ithresh, vbit;169170#ifdef QM_CHECKING171e_QmPortalProduceMode pmode;172e_QmPortalMrConsumeMode cmode;173#endif /* QM_CHECKING */174};175176/* MC state */177struct qm_mc {178struct qm_mc_command *cr;179struct qm_mc_result *rr;180uint8_t rridx, vbit;181#ifdef QM_CHECKING182enum {183/* Can be _mc_start()ed */184mc_idle,185/* Can be _mc_commit()ed or _mc_abort()ed */186mc_user,187/* Can only be _mc_retry()ed */188mc_hw189} state;190#endif /* QM_CHECKING */191};192193/********************/194/* Portal structure */195/********************/196197struct qm_portal {198/* In the non-QM_CHECKING case, everything up to and199* including 'mc' fits in a cacheline (yay!). The 'config' part is setup-only, so isn't a200* cause for a concern. In other words, don't rearrange this structure201* on a whim, there be dragons ... */202struct qm_addr addr;203struct qm_eqcr eqcr;204struct qm_dqrr dqrr;205struct qm_mr mr;206struct qm_mc mc;207struct qm_portal_config config;208t_Handle bind_lock;209/* Logical index (not cell-index) */210int index;211};212213#endif /* __QMAN_PRIVATE_H */214215216