/*1* Copyright 2008-2012 Freescale Semiconductor Inc.2*3* Redistribution and use in source and binary forms, with or without4* modification, are permitted provided that the following conditions are met:5* * Redistributions of source code must retain the above copyright6* notice, this list of conditions and the following disclaimer.7* * Redistributions in binary form must reproduce the above copyright8* notice, this list of conditions and the following disclaimer in the9* documentation and/or other materials provided with the distribution.10* * Neither the name of Freescale Semiconductor nor the11* names of its contributors may be used to endorse or promote products12* derived from this software without specific prior written permission.13*14*15* ALTERNATIVELY, this software may be distributed under the terms of the16* GNU General Public License ("GPL") as published by the Free Software17* Foundation, either version 2 of that License or (at your option) any18* later version.19*20* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY21* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED22* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE23* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY24* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES25* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;26* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND27* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT28* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS29* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.30*/313233/**************************************************************************//**34@File core_ext.h3536@Description Generic interface to basic core operations.3738The system integrator must ensure that this interface is39mapped to a specific core implementation, by including the40appropriate header file.41*//***************************************************************************/42#ifndef __CORE_EXT_H43#define __CORE_EXT_H4445#ifdef CONFIG_FMAN_ARM46#include "arm_ext.h"47#include <linux/smp.h>48#else49#ifdef NCSW_PPC_CORE50#include "ppc_ext.h"51#elif defined(NCSW_VXWORKS)52#include "core_vxw_ext.h"53#else54#error "Core is not defined!"55#endif /* NCSW_CORE */5657#if (!defined(CORE_IS_LITTLE_ENDIAN) && !defined(CORE_IS_BIG_ENDIAN))58#error "Must define core as little-endian or big-endian!"59#endif /* (!defined(CORE_IS_LITTLE_ENDIAN) && ... */6061#ifndef CORE_CACHELINE_SIZE62#error "Must define the core cache-line size!"63#endif /* !CORE_CACHELINE_SIZE */6465#endif /* CONFIG_FMAN_ARM */666768/**************************************************************************//**69@Function CORE_GetId7071@Description Returns the core ID in the system.7273@Return Core ID.74*//***************************************************************************/75uint32_t CORE_GetId(void);7677/**************************************************************************//**78@Function CORE_MemoryBarrier7980@Description This routine will cause the core to stop executing any commands81until all previous memory read/write commands are completely out82of the core's pipeline.8384@Return None.85*//***************************************************************************/86void CORE_MemoryBarrier(void);87#define fsl_mem_core_barrier() CORE_MemoryBarrier()8889#endif /* __CORE_EXT_H */909192