CoCalc -- ghash-armv4.S

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/crypto/openssl/arm/ghash-armv4.S
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/* Do not modify. This file is auto-generated from ghash-armv4.pl. */
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#include "arm_arch.h"
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#if defined(__thumb2__) || defined(__clang__)
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.syntax	unified
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#define ldrplb  ldrbpl
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#define ldrneb  ldrbne
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#endif
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#if defined(__thumb2__)
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.thumb
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#else
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.code	32
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#endif
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.text
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.type	rem_4bit,%object
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.align	5
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rem_4bit:
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.short	0x0000,0x1C20,0x3840,0x2460
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.short	0x7080,0x6CA0,0x48C0,0x54E0
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.short	0xE100,0xFD20,0xD940,0xC560
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.short	0x9180,0x8DA0,0xA9C0,0xB5E0
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.size	rem_4bit,.-rem_4bit
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.type	rem_4bit_get,%function
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rem_4bit_get:
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#if defined(__thumb2__)
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	adr	r2,rem_4bit
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#else
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	sub	r2,pc,#8+32	@ &rem_4bit
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#endif
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	b	.Lrem_4bit_got
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	nop
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	nop
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.size	rem_4bit_get,.-rem_4bit_get
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.globl	gcm_ghash_4bit
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.type	gcm_ghash_4bit,%function
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.align	4
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gcm_ghash_4bit:
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#if defined(__thumb2__)
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	adr	r12,rem_4bit
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#else
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	sub	r12,pc,#8+48		@ &rem_4bit
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#endif
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	add	r3,r2,r3		@ r3 to point at the end
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	stmdb	sp!,{r3,r4,r5,r6,r7,r8,r9,r10,r11,lr}		@ save r3/end too
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	ldmia	r12,{r4,r5,r6,r7,r8,r9,r10,r11}		@ copy rem_4bit ...
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	stmdb	sp!,{r4,r5,r6,r7,r8,r9,r10,r11}		@ ... to stack
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	ldrb	r12,[r2,#15]
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	ldrb	r14,[r0,#15]
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.Louter:
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	eor	r12,r12,r14
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	and	r14,r12,#0xf0
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	and	r12,r12,#0x0f
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	mov	r3,#14
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	add	r7,r1,r12,lsl#4
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	ldmia	r7,{r4,r5,r6,r7}	@ load Htbl[nlo]
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	add	r11,r1,r14
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	ldrb	r12,[r2,#14]
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	and	r14,r4,#0xf		@ rem
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	ldmia	r11,{r8,r9,r10,r11}	@ load Htbl[nhi]
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	add	r14,r14,r14
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	eor	r4,r8,r4,lsr#4
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	ldrh	r8,[sp,r14]		@ rem_4bit[rem]
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	eor	r4,r4,r5,lsl#28
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	ldrb	r14,[r0,#14]
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	eor	r5,r9,r5,lsr#4
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	eor	r5,r5,r6,lsl#28
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	eor	r6,r10,r6,lsr#4
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	eor	r6,r6,r7,lsl#28
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	eor	r7,r11,r7,lsr#4
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	eor	r12,r12,r14
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	and	r14,r12,#0xf0
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	and	r12,r12,#0x0f
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	eor	r7,r7,r8,lsl#16
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.Linner:
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	add	r11,r1,r12,lsl#4
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	and	r12,r4,#0xf		@ rem
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	subs	r3,r3,#1
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	add	r12,r12,r12
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	ldmia	r11,{r8,r9,r10,r11}	@ load Htbl[nlo]
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	eor	r4,r8,r4,lsr#4
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	eor	r4,r4,r5,lsl#28
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	eor	r5,r9,r5,lsr#4
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	eor	r5,r5,r6,lsl#28
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	ldrh	r8,[sp,r12]		@ rem_4bit[rem]
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	eor	r6,r10,r6,lsr#4
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#ifdef	__thumb2__
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	it	pl
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#endif
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	ldrplb	r12,[r2,r3]
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	eor	r6,r6,r7,lsl#28
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	eor	r7,r11,r7,lsr#4
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	add	r11,r1,r14
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	and	r14,r4,#0xf		@ rem
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	eor	r7,r7,r8,lsl#16	@ ^= rem_4bit[rem]
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	add	r14,r14,r14
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	ldmia	r11,{r8,r9,r10,r11}	@ load Htbl[nhi]
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	eor	r4,r8,r4,lsr#4
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#ifdef	__thumb2__
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	it	pl
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#endif
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	ldrplb	r8,[r0,r3]
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	eor	r4,r4,r5,lsl#28
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	eor	r5,r9,r5,lsr#4
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	ldrh	r9,[sp,r14]
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	eor	r5,r5,r6,lsl#28
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	eor	r6,r10,r6,lsr#4
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	eor	r6,r6,r7,lsl#28
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#ifdef	__thumb2__
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	it	pl
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#endif
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	eorpl	r12,r12,r8
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	eor	r7,r11,r7,lsr#4
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#ifdef	__thumb2__
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	itt	pl
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#endif
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	andpl	r14,r12,#0xf0
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	andpl	r12,r12,#0x0f
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	eor	r7,r7,r9,lsl#16	@ ^= rem_4bit[rem]
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	bpl	.Linner
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	ldr	r3,[sp,#32]		@ re-load r3/end
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	add	r2,r2,#16
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	mov	r14,r4
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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	rev	r4,r4
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	str	r4,[r0,#12]
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#elif defined(__ARMEB__)
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	str	r4,[r0,#12]
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#else
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	mov	r9,r4,lsr#8
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	strb	r4,[r0,#12+3]
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	mov	r10,r4,lsr#16
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	strb	r9,[r0,#12+2]
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	mov	r11,r4,lsr#24
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	strb	r10,[r0,#12+1]
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	strb	r11,[r0,#12]
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#endif
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	cmp	r2,r3
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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	rev	r5,r5
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	str	r5,[r0,#8]
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#elif defined(__ARMEB__)
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	str	r5,[r0,#8]
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#else
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	mov	r9,r5,lsr#8
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	strb	r5,[r0,#8+3]
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	mov	r10,r5,lsr#16
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	strb	r9,[r0,#8+2]
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	mov	r11,r5,lsr#24
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	strb	r10,[r0,#8+1]
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	strb	r11,[r0,#8]
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#endif
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#ifdef __thumb2__
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	it	ne
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#endif
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	ldrneb	r12,[r2,#15]
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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	rev	r6,r6
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	str	r6,[r0,#4]
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#elif defined(__ARMEB__)
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	str	r6,[r0,#4]
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#else
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	mov	r9,r6,lsr#8
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	strb	r6,[r0,#4+3]
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	mov	r10,r6,lsr#16
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	strb	r9,[r0,#4+2]
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	mov	r11,r6,lsr#24
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	strb	r10,[r0,#4+1]
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	strb	r11,[r0,#4]
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#endif
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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	rev	r7,r7
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	str	r7,[r0,#0]
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#elif defined(__ARMEB__)
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	str	r7,[r0,#0]
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#else
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	mov	r9,r7,lsr#8
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	strb	r7,[r0,#0+3]
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	mov	r10,r7,lsr#16
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	strb	r9,[r0,#0+2]
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	mov	r11,r7,lsr#24
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	strb	r10,[r0,#0+1]
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	strb	r11,[r0,#0]
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#endif
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	bne	.Louter
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	add	sp,sp,#36
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#if __ARM_ARCH__>=5
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	ldmia	sp!,{r4,r5,r6,r7,r8,r9,r10,r11,pc}
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#else
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	ldmia	sp!,{r4,r5,r6,r7,r8,r9,r10,r11,lr}
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	tst	lr,#1
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	moveq	pc,lr			@ be binary compatible with V4, yet
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.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
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#endif
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.size	gcm_ghash_4bit,.-gcm_ghash_4bit
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.globl	gcm_gmult_4bit
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.type	gcm_gmult_4bit,%function
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gcm_gmult_4bit:
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	stmdb	sp!,{r4,r5,r6,r7,r8,r9,r10,r11,lr}
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	ldrb	r12,[r0,#15]
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	b	rem_4bit_get
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.Lrem_4bit_got:
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	and	r14,r12,#0xf0
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	and	r12,r12,#0x0f
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	mov	r3,#14
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	add	r7,r1,r12,lsl#4
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	ldmia	r7,{r4,r5,r6,r7}	@ load Htbl[nlo]
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	ldrb	r12,[r0,#14]
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	add	r11,r1,r14
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	and	r14,r4,#0xf		@ rem
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	ldmia	r11,{r8,r9,r10,r11}	@ load Htbl[nhi]
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	add	r14,r14,r14
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	eor	r4,r8,r4,lsr#4
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	ldrh	r8,[r2,r14]	@ rem_4bit[rem]
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	eor	r4,r4,r5,lsl#28
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	eor	r5,r9,r5,lsr#4
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	eor	r5,r5,r6,lsl#28
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	eor	r6,r10,r6,lsr#4
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	eor	r6,r6,r7,lsl#28
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	eor	r7,r11,r7,lsr#4
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	and	r14,r12,#0xf0
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	eor	r7,r7,r8,lsl#16
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	and	r12,r12,#0x0f
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.Loop:
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	add	r11,r1,r12,lsl#4
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	and	r12,r4,#0xf		@ rem
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	subs	r3,r3,#1
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	add	r12,r12,r12
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	ldmia	r11,{r8,r9,r10,r11}	@ load Htbl[nlo]
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	eor	r4,r8,r4,lsr#4
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	eor	r4,r4,r5,lsl#28
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	eor	r5,r9,r5,lsr#4
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	eor	r5,r5,r6,lsl#28
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	ldrh	r8,[r2,r12]	@ rem_4bit[rem]
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	eor	r6,r10,r6,lsr#4
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#ifdef	__thumb2__
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	it	pl
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#endif
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	ldrplb	r12,[r0,r3]
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	eor	r6,r6,r7,lsl#28
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	eor	r7,r11,r7,lsr#4
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	add	r11,r1,r14
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	and	r14,r4,#0xf		@ rem
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	eor	r7,r7,r8,lsl#16	@ ^= rem_4bit[rem]
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	add	r14,r14,r14
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	ldmia	r11,{r8,r9,r10,r11}	@ load Htbl[nhi]
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	eor	r4,r8,r4,lsr#4
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	eor	r4,r4,r5,lsl#28
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	eor	r5,r9,r5,lsr#4
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	ldrh	r8,[r2,r14]	@ rem_4bit[rem]
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	eor	r5,r5,r6,lsl#28
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	eor	r6,r10,r6,lsr#4
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	eor	r6,r6,r7,lsl#28
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	eor	r7,r11,r7,lsr#4
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#ifdef	__thumb2__
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	itt	pl
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#endif
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	andpl	r14,r12,#0xf0
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	andpl	r12,r12,#0x0f
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	eor	r7,r7,r8,lsl#16	@ ^= rem_4bit[rem]
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	bpl	.Loop
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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	rev	r4,r4
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	str	r4,[r0,#12]
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#elif defined(__ARMEB__)
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	str	r4,[r0,#12]
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#else
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	mov	r9,r4,lsr#8
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	strb	r4,[r0,#12+3]
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	mov	r10,r4,lsr#16
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	strb	r9,[r0,#12+2]
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	mov	r11,r4,lsr#24
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	strb	r10,[r0,#12+1]
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	strb	r11,[r0,#12]
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#endif
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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	rev	r5,r5
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	str	r5,[r0,#8]
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#elif defined(__ARMEB__)
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	str	r5,[r0,#8]
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#else
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	mov	r9,r5,lsr#8
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	strb	r5,[r0,#8+3]
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	mov	r10,r5,lsr#16
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	strb	r9,[r0,#8+2]
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	mov	r11,r5,lsr#24
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	strb	r10,[r0,#8+1]
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	strb	r11,[r0,#8]
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#endif
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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	rev	r6,r6
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	str	r6,[r0,#4]
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#elif defined(__ARMEB__)
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	str	r6,[r0,#4]
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#else
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	mov	r9,r6,lsr#8
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	strb	r6,[r0,#4+3]
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	mov	r10,r6,lsr#16
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	strb	r9,[r0,#4+2]
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	mov	r11,r6,lsr#24
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	strb	r10,[r0,#4+1]
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	strb	r11,[r0,#4]
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#endif
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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	rev	r7,r7
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	str	r7,[r0,#0]
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#elif defined(__ARMEB__)
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	str	r7,[r0,#0]
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#else
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	mov	r9,r7,lsr#8
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	strb	r7,[r0,#0+3]
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	mov	r10,r7,lsr#16
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	strb	r9,[r0,#0+2]
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	mov	r11,r7,lsr#24
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	strb	r10,[r0,#0+1]
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	strb	r11,[r0,#0]
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#endif
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#if __ARM_ARCH__>=5
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	ldmia	sp!,{r4,r5,r6,r7,r8,r9,r10,r11,pc}
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#else
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	ldmia	sp!,{r4,r5,r6,r7,r8,r9,r10,r11,lr}
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	tst	lr,#1
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	moveq	pc,lr			@ be binary compatible with V4, yet
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.word	0xe12fff1e			@ interoperable with Thumb ISA:-)
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#endif
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.size	gcm_gmult_4bit,.-gcm_gmult_4bit
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#if __ARM_MAX_ARCH__>=7
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.arch	armv7-a
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.fpu	neon
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.globl	gcm_init_neon
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.type	gcm_init_neon,%function
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.align	4
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gcm_init_neon:
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	vld1.64	d7,[r1]!		@ load H
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	vmov.i8	q8,#0xe1
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	vld1.64	d6,[r1]
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	vshl.i64	d17,#57
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	vshr.u64	d16,#63		@ t0=0xc2....01
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	vdup.8	q9,d7[7]
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	vshr.u64	d26,d6,#63
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	vshr.s8	q9,#7			@ broadcast carry bit
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	vshl.i64	q3,q3,#1
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	vand	q8,q8,q9
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	vorr	d7,d26		@ H<<<=1
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	veor	q3,q3,q8		@ twisted H
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	vstmia	r0,{q3}
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	bx	lr					@ bx lr
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.size	gcm_init_neon,.-gcm_init_neon
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.globl	gcm_gmult_neon
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.type	gcm_gmult_neon,%function
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.align	4
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gcm_gmult_neon:
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	vld1.64	d7,[r0]!		@ load Xi
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	vld1.64	d6,[r0]!
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	vmov.i64	d29,#0x0000ffffffffffff
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	vldmia	r1,{d26,d27}	@ load twisted H
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	vmov.i64	d30,#0x00000000ffffffff
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#ifdef __ARMEL__
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	vrev64.8	q3,q3
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#endif
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	vmov.i64	d31,#0x000000000000ffff
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	veor	d28,d26,d27		@ Karatsuba pre-processing
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	mov	r3,#16
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	b	.Lgmult_neon
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.size	gcm_gmult_neon,.-gcm_gmult_neon
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.globl	gcm_ghash_neon
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.type	gcm_ghash_neon,%function
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.align	4
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gcm_ghash_neon:
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	vld1.64	d1,[r0]!		@ load Xi
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	vld1.64	d0,[r0]!
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	vmov.i64	d29,#0x0000ffffffffffff
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	vldmia	r1,{d26,d27}	@ load twisted H
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	vmov.i64	d30,#0x00000000ffffffff
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#ifdef __ARMEL__
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	vrev64.8	q0,q0
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#endif
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	vmov.i64	d31,#0x000000000000ffff
406
	veor	d28,d26,d27		@ Karatsuba pre-processing
407

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.Loop_neon:
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	vld1.64	d7,[r2]!		@ load inp
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	vld1.64	d6,[r2]!
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#ifdef __ARMEL__
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	vrev64.8	q3,q3
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#endif
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	veor	q3,q0			@ inp^=Xi
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.Lgmult_neon:
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	vext.8	d16, d26, d26, #1	@ A1
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	vmull.p8	q8, d16, d6		@ F = A1*B
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	vext.8	d0, d6, d6, #1	@ B1
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	vmull.p8	q0, d26, d0		@ E = A*B1
420
	vext.8	d18, d26, d26, #2	@ A2
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	vmull.p8	q9, d18, d6		@ H = A2*B
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	vext.8	d22, d6, d6, #2	@ B2
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	vmull.p8	q11, d26, d22		@ G = A*B2
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	vext.8	d20, d26, d26, #3	@ A3
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	veor	q8, q8, q0		@ L = E + F
426
	vmull.p8	q10, d20, d6		@ J = A3*B
427
	vext.8	d0, d6, d6, #3	@ B3
428
	veor	q9, q9, q11		@ M = G + H
429
	vmull.p8	q0, d26, d0		@ I = A*B3
430
	veor	d16, d16, d17	@ t0 = (L) (P0 + P1) << 8
431
	vand	d17, d17, d29
432
	vext.8	d22, d6, d6, #4	@ B4
433
	veor	d18, d18, d19	@ t1 = (M) (P2 + P3) << 16
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	vand	d19, d19, d30
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	vmull.p8	q11, d26, d22		@ K = A*B4
436
	veor	q10, q10, q0		@ N = I + J
437
	veor	d16, d16, d17
438
	veor	d18, d18, d19
439
	veor	d20, d20, d21	@ t2 = (N) (P4 + P5) << 24
440
	vand	d21, d21, d31
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	vext.8	q8, q8, q8, #15
442
	veor	d22, d22, d23	@ t3 = (K) (P6 + P7) << 32
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	vmov.i64	d23, #0
444
	vext.8	q9, q9, q9, #14
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	veor	d20, d20, d21
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	vmull.p8	q0, d26, d6		@ D = A*B
447
	vext.8	q11, q11, q11, #12
448
	vext.8	q10, q10, q10, #13
449
	veor	q8, q8, q9
450
	veor	q10, q10, q11
451
	veor	q0, q0, q8
452
	veor	q0, q0, q10
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	veor	d6,d6,d7	@ Karatsuba pre-processing
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	vext.8	d16, d28, d28, #1	@ A1
455
	vmull.p8	q8, d16, d6		@ F = A1*B
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	vext.8	d2, d6, d6, #1	@ B1
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	vmull.p8	q1, d28, d2		@ E = A*B1
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	vext.8	d18, d28, d28, #2	@ A2
459
	vmull.p8	q9, d18, d6		@ H = A2*B
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	vext.8	d22, d6, d6, #2	@ B2
461
	vmull.p8	q11, d28, d22		@ G = A*B2
462
	vext.8	d20, d28, d28, #3	@ A3
463
	veor	q8, q8, q1		@ L = E + F
464
	vmull.p8	q10, d20, d6		@ J = A3*B
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	vext.8	d2, d6, d6, #3	@ B3
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	veor	q9, q9, q11		@ M = G + H
467
	vmull.p8	q1, d28, d2		@ I = A*B3
468
	veor	d16, d16, d17	@ t0 = (L) (P0 + P1) << 8
469
	vand	d17, d17, d29
470
	vext.8	d22, d6, d6, #4	@ B4
471
	veor	d18, d18, d19	@ t1 = (M) (P2 + P3) << 16
472
	vand	d19, d19, d30
473
	vmull.p8	q11, d28, d22		@ K = A*B4
474
	veor	q10, q10, q1		@ N = I + J
475
	veor	d16, d16, d17
476
	veor	d18, d18, d19
477
	veor	d20, d20, d21	@ t2 = (N) (P4 + P5) << 24
478
	vand	d21, d21, d31
479
	vext.8	q8, q8, q8, #15
480
	veor	d22, d22, d23	@ t3 = (K) (P6 + P7) << 32
481
	vmov.i64	d23, #0
482
	vext.8	q9, q9, q9, #14
483
	veor	d20, d20, d21
484
	vmull.p8	q1, d28, d6		@ D = A*B
485
	vext.8	q11, q11, q11, #12
486
	vext.8	q10, q10, q10, #13
487
	veor	q8, q8, q9
488
	veor	q10, q10, q11
489
	veor	q1, q1, q8
490
	veor	q1, q1, q10
491
	vext.8	d16, d27, d27, #1	@ A1
492
	vmull.p8	q8, d16, d7		@ F = A1*B
493
	vext.8	d4, d7, d7, #1	@ B1
494
	vmull.p8	q2, d27, d4		@ E = A*B1
495
	vext.8	d18, d27, d27, #2	@ A2
496
	vmull.p8	q9, d18, d7		@ H = A2*B
497
	vext.8	d22, d7, d7, #2	@ B2
498
	vmull.p8	q11, d27, d22		@ G = A*B2
499
	vext.8	d20, d27, d27, #3	@ A3
500
	veor	q8, q8, q2		@ L = E + F
501
	vmull.p8	q10, d20, d7		@ J = A3*B
502
	vext.8	d4, d7, d7, #3	@ B3
503
	veor	q9, q9, q11		@ M = G + H
504
	vmull.p8	q2, d27, d4		@ I = A*B3
505
	veor	d16, d16, d17	@ t0 = (L) (P0 + P1) << 8
506
	vand	d17, d17, d29
507
	vext.8	d22, d7, d7, #4	@ B4
508
	veor	d18, d18, d19	@ t1 = (M) (P2 + P3) << 16
509
	vand	d19, d19, d30
510
	vmull.p8	q11, d27, d22		@ K = A*B4
511
	veor	q10, q10, q2		@ N = I + J
512
	veor	d16, d16, d17
513
	veor	d18, d18, d19
514
	veor	d20, d20, d21	@ t2 = (N) (P4 + P5) << 24
515
	vand	d21, d21, d31
516
	vext.8	q8, q8, q8, #15
517
	veor	d22, d22, d23	@ t3 = (K) (P6 + P7) << 32
518
	vmov.i64	d23, #0
519
	vext.8	q9, q9, q9, #14
520
	veor	d20, d20, d21
521
	vmull.p8	q2, d27, d7		@ D = A*B
522
	vext.8	q11, q11, q11, #12
523
	vext.8	q10, q10, q10, #13
524
	veor	q8, q8, q9
525
	veor	q10, q10, q11
526
	veor	q2, q2, q8
527
	veor	q2, q2, q10
528
	veor	q1,q1,q0		@ Karatsuba post-processing
529
	veor	q1,q1,q2
530
	veor	d1,d1,d2
531
	veor	d4,d4,d3	@ Xh|Xl - 256-bit result
532

533
	@ equivalent of reduction_avx from ghash-x86_64.pl
534
	vshl.i64	q9,q0,#57		@ 1st phase
535
	vshl.i64	q10,q0,#62
536
	veor	q10,q10,q9		@
537
	vshl.i64	q9,q0,#63
538
	veor	q10, q10, q9		@
539
	veor	d1,d1,d20	@
540
	veor	d4,d4,d21
541

542
	vshr.u64	q10,q0,#1		@ 2nd phase
543
	veor	q2,q2,q0
544
	veor	q0,q0,q10		@
545
	vshr.u64	q10,q10,#6
546
	vshr.u64	q0,q0,#1		@
547
	veor	q0,q0,q2		@
548
	veor	q0,q0,q10		@
549

550
	subs	r3,#16
551
	bne	.Loop_neon
552

553
#ifdef __ARMEL__
554
	vrev64.8	q0,q0
555
#endif
556
	sub	r0,#16
557
	vst1.64	d1,[r0]!		@ write out Xi
558
	vst1.64	d0,[r0]
559

560
	bx	lr					@ bx lr
561
.size	gcm_ghash_neon,.-gcm_ghash_neon
562
#endif
563
.byte	71,72,65,83,72,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
564
.align	2
565
.align	2
566

567
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