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freebsd
GitHub Repository: freebsd/freebsd-src
 Path: blob/main/sys/crypto/openssl/arm/ghashv8-armx.S
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/* Do not modify. This file is auto-generated from ghashv8-armx.pl. */

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#include "arm_arch.h"

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#if __ARM_MAX_ARCH__>=7

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.fpu	neon

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#ifdef __thumb2__

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.syntax	unified

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.thumb

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# define INST(a,b,c,d) .byte  c,0xef,a,b

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#else

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.code	32

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# define INST(a,b,c,d) .byte  a,b,c,0xf2

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#endif

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.text

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.globl	gcm_init_v8

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.type	gcm_init_v8,%function

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.align	4

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gcm_init_v8:

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	vld1.64	{q9},[r1]		@ load input H

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	vmov.i8	q11,#0xe1

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	vshl.i64	q11,q11,#57		@ 0xc2.0

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	vext.8	q3,q9,q9,#8

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	vshr.u64	q10,q11,#63

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	vdup.32	q9,d18[1]

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	vext.8	q8,q10,q11,#8		@ t0=0xc2....01

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	vshr.u64	q10,q3,#63

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	vshr.s32	q9,q9,#31		@ broadcast carry bit

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	vand	q10,q10,q8

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	vshl.i64	q3,q3,#1

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	vext.8	q10,q10,q10,#8

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	vand	q8,q8,q9

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	vorr	q3,q3,q10		@ H<<<=1

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	veor	q12,q3,q8		@ twisted H

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	vst1.64	{q12},[r0]!		@ store Htable[0]

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	@ calculate H^2

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	vext.8	q8,q12,q12,#8		@ Karatsuba pre-processing

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	INST(0xa8,0x0e,0xa8,0xf2)	@ pmull q0,q12,q12

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	veor	q8,q8,q12

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	INST(0xa9,0x4e,0xa9,0xf2)	@ pmull2 q2,q12,q12

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	INST(0xa0,0x2e,0xa0,0xf2)	@ pmull q1,q8,q8

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	vext.8	q9,q0,q2,#8		@ Karatsuba post-processing

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	veor	q10,q0,q2

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	veor	q1,q1,q9

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	veor	q1,q1,q10

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	INST(0x26,0x4e,0xe0,0xf2)	@ pmull q10,q0,q11		@ 1st phase

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	vmov	d4,d3		@ Xh|Xm - 256-bit result

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	vmov	d3,d0		@ Xm is rotated Xl

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	veor	q0,q1,q10

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	vext.8	q10,q0,q0,#8		@ 2nd phase

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	INST(0x26,0x0e,0xa0,0xf2)	@ pmull q0,q0,q11

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	veor	q10,q10,q2

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	veor	q14,q0,q10

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	vext.8	q9,q14,q14,#8		@ Karatsuba pre-processing

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	veor	q9,q9,q14

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	vext.8	q13,q8,q9,#8		@ pack Karatsuba pre-processed

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	vst1.64	{q13,q14},[r0]!	@ store Htable[1..2]

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	bx	lr

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.size	gcm_init_v8,.-gcm_init_v8

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.globl	gcm_gmult_v8

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.type	gcm_gmult_v8,%function

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.align	4

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gcm_gmult_v8:

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	vld1.64	{q9},[r0]		@ load Xi

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	vmov.i8	q11,#0xe1

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	vld1.64	{q12,q13},[r1]	@ load twisted H, ...

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	vshl.u64	q11,q11,#57

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#ifndef __ARMEB__

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	vrev64.8	q9,q9

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#endif

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	vext.8	q3,q9,q9,#8

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	INST(0x86,0x0e,0xa8,0xf2)	@ pmull q0,q12,q3		@ H.lo·Xi.lo

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	veor	q9,q9,q3		@ Karatsuba pre-processing

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	INST(0x87,0x4e,0xa9,0xf2)	@ pmull2 q2,q12,q3		@ H.hi·Xi.hi

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	INST(0xa2,0x2e,0xaa,0xf2)	@ pmull q1,q13,q9		@ (H.lo+H.hi)·(Xi.lo+Xi.hi)

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	vext.8	q9,q0,q2,#8		@ Karatsuba post-processing

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	veor	q10,q0,q2

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	veor	q1,q1,q9

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	veor	q1,q1,q10

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	INST(0x26,0x4e,0xe0,0xf2)	@ pmull q10,q0,q11		@ 1st phase of reduction

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	vmov	d4,d3		@ Xh|Xm - 256-bit result

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	vmov	d3,d0		@ Xm is rotated Xl

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	veor	q0,q1,q10

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	vext.8	q10,q0,q0,#8		@ 2nd phase of reduction

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	INST(0x26,0x0e,0xa0,0xf2)	@ pmull q0,q0,q11

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	veor	q10,q10,q2

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	veor	q0,q0,q10

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#ifndef __ARMEB__

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	vrev64.8	q0,q0

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#endif

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	vext.8	q0,q0,q0,#8

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	vst1.64	{q0},[r0]		@ write out Xi

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	bx	lr

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.size	gcm_gmult_v8,.-gcm_gmult_v8

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.globl	gcm_ghash_v8

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.type	gcm_ghash_v8,%function

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.align	4

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gcm_ghash_v8:

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	vstmdb	sp!,{d8,d9,d10,d11,d12,d13,d14,d15}		@ 32-bit ABI says so

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	vld1.64	{q0},[r0]		@ load [rotated] Xi

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						@ "[rotated]" means that

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						@ loaded value would have

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						@ to be rotated in order to

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						@ make it appear as in

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						@ algorithm specification

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	subs	r3,r3,#32		@ see if r3 is 32 or larger

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	mov	r12,#16		@ r12 is used as post-

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						@ increment for input pointer;

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						@ as loop is modulo-scheduled

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						@ r12 is zeroed just in time

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						@ to preclude overstepping

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						@ inp[len], which means that

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						@ last block[s] are actually

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						@ loaded twice, but last

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						@ copy is not processed

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	vld1.64	{q12,q13},[r1]!	@ load twisted H, ..., H^2

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	vmov.i8	q11,#0xe1

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	vld1.64	{q14},[r1]

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	it	eq

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	moveq	r12,#0			@ is it time to zero r12?

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	vext.8	q0,q0,q0,#8		@ rotate Xi

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	vld1.64	{q8},[r2]!	@ load [rotated] I[0]

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	vshl.u64	q11,q11,#57		@ compose 0xc2.0 constant

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#ifndef __ARMEB__

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	vrev64.8	q8,q8

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	vrev64.8	q0,q0

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#endif

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	vext.8	q3,q8,q8,#8		@ rotate I[0]

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	blo	.Lodd_tail_v8		@ r3 was less than 32

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	vld1.64	{q9},[r2],r12	@ load [rotated] I[1]

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#ifndef __ARMEB__

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	vrev64.8	q9,q9

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#endif

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	vext.8	q7,q9,q9,#8

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	veor	q3,q3,q0		@ I[i]^=Xi

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	INST(0x8e,0x8e,0xa8,0xf2)	@ pmull q4,q12,q7		@ H·Ii+1

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	veor	q9,q9,q7		@ Karatsuba pre-processing

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	INST(0x8f,0xce,0xa9,0xf2)	@ pmull2 q6,q12,q7

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	b	.Loop_mod2x_v8

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.align	4

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.Loop_mod2x_v8:

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	vext.8	q10,q3,q3,#8

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	subs	r3,r3,#32		@ is there more data?

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	INST(0x86,0x0e,0xac,0xf2)	@ pmull q0,q14,q3		@ H^2.lo·Xi.lo

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	it	lo

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	movlo	r12,#0			@ is it time to zero r12?

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	INST(0xa2,0xae,0xaa,0xf2)	@ pmull q5,q13,q9

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	veor	q10,q10,q3		@ Karatsuba pre-processing

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	INST(0x87,0x4e,0xad,0xf2)	@ pmull2 q2,q14,q3		@ H^2.hi·Xi.hi

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	veor	q0,q0,q4		@ accumulate

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	INST(0xa5,0x2e,0xab,0xf2)	@ pmull2 q1,q13,q10		@ (H^2.lo+H^2.hi)·(Xi.lo+Xi.hi)

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	vld1.64	{q8},[r2],r12	@ load [rotated] I[i+2]

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	veor	q2,q2,q6

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	it	eq

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	moveq	r12,#0			@ is it time to zero r12?

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	veor	q1,q1,q5

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	vext.8	q9,q0,q2,#8		@ Karatsuba post-processing

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	veor	q10,q0,q2

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	veor	q1,q1,q9

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	vld1.64	{q9},[r2],r12	@ load [rotated] I[i+3]

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#ifndef __ARMEB__

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	vrev64.8	q8,q8

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#endif

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	veor	q1,q1,q10

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	INST(0x26,0x4e,0xe0,0xf2)	@ pmull q10,q0,q11		@ 1st phase of reduction

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#ifndef __ARMEB__

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	vrev64.8	q9,q9

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#endif

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	vmov	d4,d3		@ Xh|Xm - 256-bit result

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	vmov	d3,d0		@ Xm is rotated Xl

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	vext.8	q7,q9,q9,#8

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	vext.8	q3,q8,q8,#8

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	veor	q0,q1,q10

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	INST(0x8e,0x8e,0xa8,0xf2)	@ pmull q4,q12,q7		@ H·Ii+1

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	veor	q3,q3,q2		@ accumulate q3 early

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	vext.8	q10,q0,q0,#8		@ 2nd phase of reduction

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	INST(0x26,0x0e,0xa0,0xf2)	@ pmull q0,q0,q11

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	veor	q3,q3,q10

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	veor	q9,q9,q7		@ Karatsuba pre-processing

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	veor	q3,q3,q0

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	INST(0x8f,0xce,0xa9,0xf2)	@ pmull2 q6,q12,q7

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	bhs	.Loop_mod2x_v8		@ there was at least 32 more bytes

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	veor	q2,q2,q10

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	vext.8	q3,q8,q8,#8		@ re-construct q3

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	adds	r3,r3,#32		@ re-construct r3

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	veor	q0,q0,q2		@ re-construct q0

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	beq	.Ldone_v8		@ is r3 zero?

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.Lodd_tail_v8:

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	vext.8	q10,q0,q0,#8

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	veor	q3,q3,q0		@ inp^=Xi

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	veor	q9,q8,q10		@ q9 is rotated inp^Xi

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	INST(0x86,0x0e,0xa8,0xf2)	@ pmull q0,q12,q3		@ H.lo·Xi.lo

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	veor	q9,q9,q3		@ Karatsuba pre-processing

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	INST(0x87,0x4e,0xa9,0xf2)	@ pmull2 q2,q12,q3		@ H.hi·Xi.hi

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	INST(0xa2,0x2e,0xaa,0xf2)	@ pmull q1,q13,q9		@ (H.lo+H.hi)·(Xi.lo+Xi.hi)

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	vext.8	q9,q0,q2,#8		@ Karatsuba post-processing

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	veor	q10,q0,q2

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	veor	q1,q1,q9

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	veor	q1,q1,q10

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	INST(0x26,0x4e,0xe0,0xf2)	@ pmull q10,q0,q11		@ 1st phase of reduction

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	vmov	d4,d3		@ Xh|Xm - 256-bit result

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	vmov	d3,d0		@ Xm is rotated Xl

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	veor	q0,q1,q10

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	vext.8	q10,q0,q0,#8		@ 2nd phase of reduction

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	INST(0x26,0x0e,0xa0,0xf2)	@ pmull q0,q0,q11

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	veor	q10,q10,q2

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	veor	q0,q0,q10

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.Ldone_v8:

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#ifndef __ARMEB__

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	vrev64.8	q0,q0

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#endif

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	vext.8	q0,q0,q0,#8

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	vst1.64	{q0},[r0]		@ write out Xi

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	vldmia	sp!,{d8,d9,d10,d11,d12,d13,d14,d15}		@ 32-bit ABI says so

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	bx	lr

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.size	gcm_ghash_v8,.-gcm_ghash_v8

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.section	.rodata

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.byte	71,72,65,83,72,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0

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.align	2

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.align	2

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#endif

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