/*-1* Copyright (c) 2005 Poul-Henning Kamp2* All rights reserved.3*4* Redistribution and use in source and binary forms, with or without5* modification, are permitted provided that the following conditions6* are met:7* 1. Redistributions of source code must retain the above copyright8* notice, this list of conditions and the following disclaimer.9* 2. Redistributions in binary form must reproduce the above copyright10* notice, this list of conditions and the following disclaimer in the11* documentation and/or other materials provided with the distribution.12*13* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND14* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE15* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE16* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE17* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL18* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS19* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)20* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT21* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY22* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF23* SUCH DAMAGE.24*/2526#ifndef __ACPI_HPET_H__27#define __ACPI_HPET_H__2829#define HPET_MEM_WIDTH 0x400 /* Expected memory region size */30#define HPET_MEM_MIN_WIDTH 0x100 /* Minimum memory region size */3132/* General registers */33#define HPET_CAPABILITIES 0x0 /* General capabilities and ID */34#define HPET_CAP_VENDOR_ID 0xffff000035#define HPET_CAP_LEG_RT 0x0000800036#define HPET_CAP_COUNT_SIZE 0x00002000 /* 1 = 64-bit, 0 = 32-bit */37#define HPET_CAP_NUM_TIM 0x00001f0038#define HPET_CAP_REV_ID 0x000000ff39#define HPET_PERIOD 0x4 /* Period (1/hz) of timer */40#define HPET_CONFIG 0x10 /* General configuration register */41#define HPET_CNF_LEG_RT 0x0000000242#define HPET_CNF_ENABLE 0x0000000143#define HPET_ISR 0x20 /* General interrupt status register */44#define HPET_MAIN_COUNTER 0xf0 /* Main counter register */4546/* Timer registers */47#define HPET_TIMER_CAP_CNF(x) ((x) * 0x20 + 0x100)48#define HPET_TCAP_INT_ROUTE 0xffffffff0000000049#define HPET_TCAP_FSB_INT_DEL 0x0000800050#define HPET_TCNF_FSB_EN 0x0000400051#define HPET_TCNF_INT_ROUTE 0x00003e0052#define HPET_TCNF_32MODE 0x0000010053#define HPET_TCNF_VAL_SET 0x0000004054#define HPET_TCAP_SIZE 0x00000020 /* 1 = 64-bit, 0 = 32-bit */55#define HPET_TCAP_PER_INT 0x00000010 /* Supports periodic interrupts */56#define HPET_TCNF_TYPE 0x00000008 /* 1 = periodic, 0 = one-shot */57#define HPET_TCNF_INT_ENB 0x0000000458#define HPET_TCNF_INT_TYPE 0x00000002 /* 1 = level triggered, 0 = edge */59#define HPET_TIMER_COMPARATOR(x) ((x) * 0x20 + 0x108)60#define HPET_TIMER_FSB_VAL(x) ((x) * 0x20 + 0x110)61#define HPET_TIMER_FSB_ADDR(x) ((x) * 0x20 + 0x114)6263#define HPET_MIN_CYCLES 128 /* Period considered reliable. */6465#ifdef _KERNEL66struct timecounter;67struct vdso_timehands;68struct vdso_timehands32;6970uint32_t hpet_vdso_timehands(struct vdso_timehands *vdso_th,71struct timecounter *tc);72uint32_t hpet_vdso_timehands32(struct vdso_timehands32 *vdso_th32,73struct timecounter *tc);74#endif7576#endif /* !__ACPI_HPET_H__ */777879