CoCalc -- aic7xxx

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/dev/aic7xxx/aic7xxx_reg.h
³⁹⁵⁰⁷ views
1
/*
2
 * DO NOT EDIT - This file is automatically generated
3
 *		 from the following source files:
4
 *
5
 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $
6
 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $
7
 */
8
typedef int (ahc_reg_print_t)(u_int, u_int *, u_int);
9
typedef struct ahc_reg_parse_entry {
10
	char	*name;
11
	uint8_t	 value;
12
	uint8_t	 mask;
13
} ahc_reg_parse_entry_t;
14

15
#if AIC_DEBUG_REGISTERS
16
ahc_reg_print_t ahc_scsiseq_print;
17
#else
18
#define ahc_scsiseq_print(regvalue, cur_col, wrap) \
19
    ahc_print_register(NULL, 0, "SCSISEQ", 0x00, regvalue, cur_col, wrap)
20
#endif
21

22
#if AIC_DEBUG_REGISTERS
23
ahc_reg_print_t ahc_sxfrctl0_print;
24
#else
25
#define ahc_sxfrctl0_print(regvalue, cur_col, wrap) \
26
    ahc_print_register(NULL, 0, "SXFRCTL0", 0x01, regvalue, cur_col, wrap)
27
#endif
28

29
#if AIC_DEBUG_REGISTERS
30
ahc_reg_print_t ahc_sxfrctl1_print;
31
#else
32
#define ahc_sxfrctl1_print(regvalue, cur_col, wrap) \
33
    ahc_print_register(NULL, 0, "SXFRCTL1", 0x02, regvalue, cur_col, wrap)
34
#endif
35

36
#if AIC_DEBUG_REGISTERS
37
ahc_reg_print_t ahc_scsisigi_print;
38
#else
39
#define ahc_scsisigi_print(regvalue, cur_col, wrap) \
40
    ahc_print_register(NULL, 0, "SCSISIGI", 0x03, regvalue, cur_col, wrap)
41
#endif
42

43
#if AIC_DEBUG_REGISTERS
44
ahc_reg_print_t ahc_scsisigo_print;
45
#else
46
#define ahc_scsisigo_print(regvalue, cur_col, wrap) \
47
    ahc_print_register(NULL, 0, "SCSISIGO", 0x03, regvalue, cur_col, wrap)
48
#endif
49

50
#if AIC_DEBUG_REGISTERS
51
ahc_reg_print_t ahc_scsirate_print;
52
#else
53
#define ahc_scsirate_print(regvalue, cur_col, wrap) \
54
    ahc_print_register(NULL, 0, "SCSIRATE", 0x04, regvalue, cur_col, wrap)
55
#endif
56

57
#if AIC_DEBUG_REGISTERS
58
ahc_reg_print_t ahc_scsiid_print;
59
#else
60
#define ahc_scsiid_print(regvalue, cur_col, wrap) \
61
    ahc_print_register(NULL, 0, "SCSIID", 0x05, regvalue, cur_col, wrap)
62
#endif
63

64
#if AIC_DEBUG_REGISTERS
65
ahc_reg_print_t ahc_scsidatl_print;
66
#else
67
#define ahc_scsidatl_print(regvalue, cur_col, wrap) \
68
    ahc_print_register(NULL, 0, "SCSIDATL", 0x06, regvalue, cur_col, wrap)
69
#endif
70

71
#if AIC_DEBUG_REGISTERS
72
ahc_reg_print_t ahc_scsidath_print;
73
#else
74
#define ahc_scsidath_print(regvalue, cur_col, wrap) \
75
    ahc_print_register(NULL, 0, "SCSIDATH", 0x07, regvalue, cur_col, wrap)
76
#endif
77

78
#if AIC_DEBUG_REGISTERS
79
ahc_reg_print_t ahc_optionmode_print;
80
#else
81
#define ahc_optionmode_print(regvalue, cur_col, wrap) \
82
    ahc_print_register(NULL, 0, "OPTIONMODE", 0x08, regvalue, cur_col, wrap)
83
#endif
84

85
#if AIC_DEBUG_REGISTERS
86
ahc_reg_print_t ahc_stcnt_print;
87
#else
88
#define ahc_stcnt_print(regvalue, cur_col, wrap) \
89
    ahc_print_register(NULL, 0, "STCNT", 0x08, regvalue, cur_col, wrap)
90
#endif
91

92
#if AIC_DEBUG_REGISTERS
93
ahc_reg_print_t ahc_targcrccnt_print;
94
#else
95
#define ahc_targcrccnt_print(regvalue, cur_col, wrap) \
96
    ahc_print_register(NULL, 0, "TARGCRCCNT", 0x0a, regvalue, cur_col, wrap)
97
#endif
98

99
#if AIC_DEBUG_REGISTERS
100
ahc_reg_print_t ahc_clrsint0_print;
101
#else
102
#define ahc_clrsint0_print(regvalue, cur_col, wrap) \
103
    ahc_print_register(NULL, 0, "CLRSINT0", 0x0b, regvalue, cur_col, wrap)
104
#endif
105

106
#if AIC_DEBUG_REGISTERS
107
ahc_reg_print_t ahc_sstat0_print;
108
#else
109
#define ahc_sstat0_print(regvalue, cur_col, wrap) \
110
    ahc_print_register(NULL, 0, "SSTAT0", 0x0b, regvalue, cur_col, wrap)
111
#endif
112

113
#if AIC_DEBUG_REGISTERS
114
ahc_reg_print_t ahc_clrsint1_print;
115
#else
116
#define ahc_clrsint1_print(regvalue, cur_col, wrap) \
117
    ahc_print_register(NULL, 0, "CLRSINT1", 0x0c, regvalue, cur_col, wrap)
118
#endif
119

120
#if AIC_DEBUG_REGISTERS
121
ahc_reg_print_t ahc_sstat1_print;
122
#else
123
#define ahc_sstat1_print(regvalue, cur_col, wrap) \
124
    ahc_print_register(NULL, 0, "SSTAT1", 0x0c, regvalue, cur_col, wrap)
125
#endif
126

127
#if AIC_DEBUG_REGISTERS
128
ahc_reg_print_t ahc_sstat2_print;
129
#else
130
#define ahc_sstat2_print(regvalue, cur_col, wrap) \
131
    ahc_print_register(NULL, 0, "SSTAT2", 0x0d, regvalue, cur_col, wrap)
132
#endif
133

134
#if AIC_DEBUG_REGISTERS
135
ahc_reg_print_t ahc_sstat3_print;
136
#else
137
#define ahc_sstat3_print(regvalue, cur_col, wrap) \
138
    ahc_print_register(NULL, 0, "SSTAT3", 0x0e, regvalue, cur_col, wrap)
139
#endif
140

141
#if AIC_DEBUG_REGISTERS
142
ahc_reg_print_t ahc_scsiid_ultra2_print;
143
#else
144
#define ahc_scsiid_ultra2_print(regvalue, cur_col, wrap) \
145
    ahc_print_register(NULL, 0, "SCSIID_ULTRA2", 0x0f, regvalue, cur_col, wrap)
146
#endif
147

148
#if AIC_DEBUG_REGISTERS
149
ahc_reg_print_t ahc_simode0_print;
150
#else
151
#define ahc_simode0_print(regvalue, cur_col, wrap) \
152
    ahc_print_register(NULL, 0, "SIMODE0", 0x10, regvalue, cur_col, wrap)
153
#endif
154

155
#if AIC_DEBUG_REGISTERS
156
ahc_reg_print_t ahc_simode1_print;
157
#else
158
#define ahc_simode1_print(regvalue, cur_col, wrap) \
159
    ahc_print_register(NULL, 0, "SIMODE1", 0x11, regvalue, cur_col, wrap)
160
#endif
161

162
#if AIC_DEBUG_REGISTERS
163
ahc_reg_print_t ahc_scsibusl_print;
164
#else
165
#define ahc_scsibusl_print(regvalue, cur_col, wrap) \
166
    ahc_print_register(NULL, 0, "SCSIBUSL", 0x12, regvalue, cur_col, wrap)
167
#endif
168

169
#if AIC_DEBUG_REGISTERS
170
ahc_reg_print_t ahc_sxfrctl2_print;
171
#else
172
#define ahc_sxfrctl2_print(regvalue, cur_col, wrap) \
173
    ahc_print_register(NULL, 0, "SXFRCTL2", 0x13, regvalue, cur_col, wrap)
174
#endif
175

176
#if AIC_DEBUG_REGISTERS
177
ahc_reg_print_t ahc_scsibush_print;
178
#else
179
#define ahc_scsibush_print(regvalue, cur_col, wrap) \
180
    ahc_print_register(NULL, 0, "SCSIBUSH", 0x13, regvalue, cur_col, wrap)
181
#endif
182

183
#if AIC_DEBUG_REGISTERS
184
ahc_reg_print_t ahc_shaddr_print;
185
#else
186
#define ahc_shaddr_print(regvalue, cur_col, wrap) \
187
    ahc_print_register(NULL, 0, "SHADDR", 0x14, regvalue, cur_col, wrap)
188
#endif
189

190
#if AIC_DEBUG_REGISTERS
191
ahc_reg_print_t ahc_seltimer_print;
192
#else
193
#define ahc_seltimer_print(regvalue, cur_col, wrap) \
194
    ahc_print_register(NULL, 0, "SELTIMER", 0x18, regvalue, cur_col, wrap)
195
#endif
196

197
#if AIC_DEBUG_REGISTERS
198
ahc_reg_print_t ahc_selid_print;
199
#else
200
#define ahc_selid_print(regvalue, cur_col, wrap) \
201
    ahc_print_register(NULL, 0, "SELID", 0x19, regvalue, cur_col, wrap)
202
#endif
203

204
#if AIC_DEBUG_REGISTERS
205
ahc_reg_print_t ahc_scamctl_print;
206
#else
207
#define ahc_scamctl_print(regvalue, cur_col, wrap) \
208
    ahc_print_register(NULL, 0, "SCAMCTL", 0x1a, regvalue, cur_col, wrap)
209
#endif
210

211
#if AIC_DEBUG_REGISTERS
212
ahc_reg_print_t ahc_targid_print;
213
#else
214
#define ahc_targid_print(regvalue, cur_col, wrap) \
215
    ahc_print_register(NULL, 0, "TARGID", 0x1b, regvalue, cur_col, wrap)
216
#endif
217

218
#if AIC_DEBUG_REGISTERS
219
ahc_reg_print_t ahc_spiocap_print;
220
#else
221
#define ahc_spiocap_print(regvalue, cur_col, wrap) \
222
    ahc_print_register(NULL, 0, "SPIOCAP", 0x1b, regvalue, cur_col, wrap)
223
#endif
224

225
#if AIC_DEBUG_REGISTERS
226
ahc_reg_print_t ahc_brdctl_print;
227
#else
228
#define ahc_brdctl_print(regvalue, cur_col, wrap) \
229
    ahc_print_register(NULL, 0, "BRDCTL", 0x1d, regvalue, cur_col, wrap)
230
#endif
231

232
#if AIC_DEBUG_REGISTERS
233
ahc_reg_print_t ahc_seectl_print;
234
#else
235
#define ahc_seectl_print(regvalue, cur_col, wrap) \
236
    ahc_print_register(NULL, 0, "SEECTL", 0x1e, regvalue, cur_col, wrap)
237
#endif
238

239
#if AIC_DEBUG_REGISTERS
240
ahc_reg_print_t ahc_sblkctl_print;
241
#else
242
#define ahc_sblkctl_print(regvalue, cur_col, wrap) \
243
    ahc_print_register(NULL, 0, "SBLKCTL", 0x1f, regvalue, cur_col, wrap)
244
#endif
245

246
#if AIC_DEBUG_REGISTERS
247
ahc_reg_print_t ahc_busy_targets_print;
248
#else
249
#define ahc_busy_targets_print(regvalue, cur_col, wrap) \
250
    ahc_print_register(NULL, 0, "BUSY_TARGETS", 0x20, regvalue, cur_col, wrap)
251
#endif
252

253
#if AIC_DEBUG_REGISTERS
254
ahc_reg_print_t ahc_ultra_enb_print;
255
#else
256
#define ahc_ultra_enb_print(regvalue, cur_col, wrap) \
257
    ahc_print_register(NULL, 0, "ULTRA_ENB", 0x30, regvalue, cur_col, wrap)
258
#endif
259

260
#if AIC_DEBUG_REGISTERS
261
ahc_reg_print_t ahc_disc_dsb_print;
262
#else
263
#define ahc_disc_dsb_print(regvalue, cur_col, wrap) \
264
    ahc_print_register(NULL, 0, "DISC_DSB", 0x32, regvalue, cur_col, wrap)
265
#endif
266

267
#if AIC_DEBUG_REGISTERS
268
ahc_reg_print_t ahc_cmdsize_table_tail_print;
269
#else
270
#define ahc_cmdsize_table_tail_print(regvalue, cur_col, wrap) \
271
    ahc_print_register(NULL, 0, "CMDSIZE_TABLE_TAIL", 0x34, regvalue, cur_col, wrap)
272
#endif
273

274
#if AIC_DEBUG_REGISTERS
275
ahc_reg_print_t ahc_mwi_residual_print;
276
#else
277
#define ahc_mwi_residual_print(regvalue, cur_col, wrap) \
278
    ahc_print_register(NULL, 0, "MWI_RESIDUAL", 0x38, regvalue, cur_col, wrap)
279
#endif
280

281
#if AIC_DEBUG_REGISTERS
282
ahc_reg_print_t ahc_next_queued_scb_print;
283
#else
284
#define ahc_next_queued_scb_print(regvalue, cur_col, wrap) \
285
    ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB", 0x39, regvalue, cur_col, wrap)
286
#endif
287

288
#if AIC_DEBUG_REGISTERS
289
ahc_reg_print_t ahc_msg_out_print;
290
#else
291
#define ahc_msg_out_print(regvalue, cur_col, wrap) \
292
    ahc_print_register(NULL, 0, "MSG_OUT", 0x3a, regvalue, cur_col, wrap)
293
#endif
294

295
#if AIC_DEBUG_REGISTERS
296
ahc_reg_print_t ahc_dmaparams_print;
297
#else
298
#define ahc_dmaparams_print(regvalue, cur_col, wrap) \
299
    ahc_print_register(NULL, 0, "DMAPARAMS", 0x3b, regvalue, cur_col, wrap)
300
#endif
301

302
#if AIC_DEBUG_REGISTERS
303
ahc_reg_print_t ahc_seq_flags_print;
304
#else
305
#define ahc_seq_flags_print(regvalue, cur_col, wrap) \
306
    ahc_print_register(NULL, 0, "SEQ_FLAGS", 0x3c, regvalue, cur_col, wrap)
307
#endif
308

309
#if AIC_DEBUG_REGISTERS
310
ahc_reg_print_t ahc_saved_scsiid_print;
311
#else
312
#define ahc_saved_scsiid_print(regvalue, cur_col, wrap) \
313
    ahc_print_register(NULL, 0, "SAVED_SCSIID", 0x3d, regvalue, cur_col, wrap)
314
#endif
315

316
#if AIC_DEBUG_REGISTERS
317
ahc_reg_print_t ahc_saved_lun_print;
318
#else
319
#define ahc_saved_lun_print(regvalue, cur_col, wrap) \
320
    ahc_print_register(NULL, 0, "SAVED_LUN", 0x3e, regvalue, cur_col, wrap)
321
#endif
322

323
#if AIC_DEBUG_REGISTERS
324
ahc_reg_print_t ahc_lastphase_print;
325
#else
326
#define ahc_lastphase_print(regvalue, cur_col, wrap) \
327
    ahc_print_register(NULL, 0, "LASTPHASE", 0x3f, regvalue, cur_col, wrap)
328
#endif
329

330
#if AIC_DEBUG_REGISTERS
331
ahc_reg_print_t ahc_waiting_scbh_print;
332
#else
333
#define ahc_waiting_scbh_print(regvalue, cur_col, wrap) \
334
    ahc_print_register(NULL, 0, "WAITING_SCBH", 0x40, regvalue, cur_col, wrap)
335
#endif
336

337
#if AIC_DEBUG_REGISTERS
338
ahc_reg_print_t ahc_disconnected_scbh_print;
339
#else
340
#define ahc_disconnected_scbh_print(regvalue, cur_col, wrap) \
341
    ahc_print_register(NULL, 0, "DISCONNECTED_SCBH", 0x41, regvalue, cur_col, wrap)
342
#endif
343

344
#if AIC_DEBUG_REGISTERS
345
ahc_reg_print_t ahc_free_scbh_print;
346
#else
347
#define ahc_free_scbh_print(regvalue, cur_col, wrap) \
348
    ahc_print_register(NULL, 0, "FREE_SCBH", 0x42, regvalue, cur_col, wrap)
349
#endif
350

351
#if AIC_DEBUG_REGISTERS
352
ahc_reg_print_t ahc_complete_scbh_print;
353
#else
354
#define ahc_complete_scbh_print(regvalue, cur_col, wrap) \
355
    ahc_print_register(NULL, 0, "COMPLETE_SCBH", 0x43, regvalue, cur_col, wrap)
356
#endif
357

358
#if AIC_DEBUG_REGISTERS
359
ahc_reg_print_t ahc_hscb_addr_print;
360
#else
361
#define ahc_hscb_addr_print(regvalue, cur_col, wrap) \
362
    ahc_print_register(NULL, 0, "HSCB_ADDR", 0x44, regvalue, cur_col, wrap)
363
#endif
364

365
#if AIC_DEBUG_REGISTERS
366
ahc_reg_print_t ahc_shared_data_addr_print;
367
#else
368
#define ahc_shared_data_addr_print(regvalue, cur_col, wrap) \
369
    ahc_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x48, regvalue, cur_col, wrap)
370
#endif
371

372
#if AIC_DEBUG_REGISTERS
373
ahc_reg_print_t ahc_kernel_qinpos_print;
374
#else
375
#define ahc_kernel_qinpos_print(regvalue, cur_col, wrap) \
376
    ahc_print_register(NULL, 0, "KERNEL_QINPOS", 0x4c, regvalue, cur_col, wrap)
377
#endif
378

379
#if AIC_DEBUG_REGISTERS
380
ahc_reg_print_t ahc_qinpos_print;
381
#else
382
#define ahc_qinpos_print(regvalue, cur_col, wrap) \
383
    ahc_print_register(NULL, 0, "QINPOS", 0x4d, regvalue, cur_col, wrap)
384
#endif
385

386
#if AIC_DEBUG_REGISTERS
387
ahc_reg_print_t ahc_qoutpos_print;
388
#else
389
#define ahc_qoutpos_print(regvalue, cur_col, wrap) \
390
    ahc_print_register(NULL, 0, "QOUTPOS", 0x4e, regvalue, cur_col, wrap)
391
#endif
392

393
#if AIC_DEBUG_REGISTERS
394
ahc_reg_print_t ahc_kernel_tqinpos_print;
395
#else
396
#define ahc_kernel_tqinpos_print(regvalue, cur_col, wrap) \
397
    ahc_print_register(NULL, 0, "KERNEL_TQINPOS", 0x4f, regvalue, cur_col, wrap)
398
#endif
399

400
#if AIC_DEBUG_REGISTERS
401
ahc_reg_print_t ahc_tqinpos_print;
402
#else
403
#define ahc_tqinpos_print(regvalue, cur_col, wrap) \
404
    ahc_print_register(NULL, 0, "TQINPOS", 0x50, regvalue, cur_col, wrap)
405
#endif
406

407
#if AIC_DEBUG_REGISTERS
408
ahc_reg_print_t ahc_arg_1_print;
409
#else
410
#define ahc_arg_1_print(regvalue, cur_col, wrap) \
411
    ahc_print_register(NULL, 0, "ARG_1", 0x51, regvalue, cur_col, wrap)
412
#endif
413

414
#if AIC_DEBUG_REGISTERS
415
ahc_reg_print_t ahc_arg_2_print;
416
#else
417
#define ahc_arg_2_print(regvalue, cur_col, wrap) \
418
    ahc_print_register(NULL, 0, "ARG_2", 0x52, regvalue, cur_col, wrap)
419
#endif
420

421
#if AIC_DEBUG_REGISTERS
422
ahc_reg_print_t ahc_last_msg_print;
423
#else
424
#define ahc_last_msg_print(regvalue, cur_col, wrap) \
425
    ahc_print_register(NULL, 0, "LAST_MSG", 0x53, regvalue, cur_col, wrap)
426
#endif
427

428
#if AIC_DEBUG_REGISTERS
429
ahc_reg_print_t ahc_scsiseq_template_print;
430
#else
431
#define ahc_scsiseq_template_print(regvalue, cur_col, wrap) \
432
    ahc_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x54, regvalue, cur_col, wrap)
433
#endif
434

435
#if AIC_DEBUG_REGISTERS
436
ahc_reg_print_t ahc_ha_274_biosglobal_print;
437
#else
438
#define ahc_ha_274_biosglobal_print(regvalue, cur_col, wrap) \
439
    ahc_print_register(NULL, 0, "HA_274_BIOSGLOBAL", 0x56, regvalue, cur_col, wrap)
440
#endif
441

442
#if AIC_DEBUG_REGISTERS
443
ahc_reg_print_t ahc_seq_flags2_print;
444
#else
445
#define ahc_seq_flags2_print(regvalue, cur_col, wrap) \
446
    ahc_print_register(NULL, 0, "SEQ_FLAGS2", 0x57, regvalue, cur_col, wrap)
447
#endif
448

449
#if AIC_DEBUG_REGISTERS
450
ahc_reg_print_t ahc_scsiconf_print;
451
#else
452
#define ahc_scsiconf_print(regvalue, cur_col, wrap) \
453
    ahc_print_register(NULL, 0, "SCSICONF", 0x5a, regvalue, cur_col, wrap)
454
#endif
455

456
#if AIC_DEBUG_REGISTERS
457
ahc_reg_print_t ahc_intdef_print;
458
#else
459
#define ahc_intdef_print(regvalue, cur_col, wrap) \
460
    ahc_print_register(NULL, 0, "INTDEF", 0x5c, regvalue, cur_col, wrap)
461
#endif
462

463
#if AIC_DEBUG_REGISTERS
464
ahc_reg_print_t ahc_hostconf_print;
465
#else
466
#define ahc_hostconf_print(regvalue, cur_col, wrap) \
467
    ahc_print_register(NULL, 0, "HOSTCONF", 0x5d, regvalue, cur_col, wrap)
468
#endif
469

470
#if AIC_DEBUG_REGISTERS
471
ahc_reg_print_t ahc_ha_274_biosctrl_print;
472
#else
473
#define ahc_ha_274_biosctrl_print(regvalue, cur_col, wrap) \
474
    ahc_print_register(NULL, 0, "HA_274_BIOSCTRL", 0x5f, regvalue, cur_col, wrap)
475
#endif
476

477
#if AIC_DEBUG_REGISTERS
478
ahc_reg_print_t ahc_seqctl_print;
479
#else
480
#define ahc_seqctl_print(regvalue, cur_col, wrap) \
481
    ahc_print_register(NULL, 0, "SEQCTL", 0x60, regvalue, cur_col, wrap)
482
#endif
483

484
#if AIC_DEBUG_REGISTERS
485
ahc_reg_print_t ahc_seqram_print;
486
#else
487
#define ahc_seqram_print(regvalue, cur_col, wrap) \
488
    ahc_print_register(NULL, 0, "SEQRAM", 0x61, regvalue, cur_col, wrap)
489
#endif
490

491
#if AIC_DEBUG_REGISTERS
492
ahc_reg_print_t ahc_seqaddr0_print;
493
#else
494
#define ahc_seqaddr0_print(regvalue, cur_col, wrap) \
495
    ahc_print_register(NULL, 0, "SEQADDR0", 0x62, regvalue, cur_col, wrap)
496
#endif
497

498
#if AIC_DEBUG_REGISTERS
499
ahc_reg_print_t ahc_seqaddr1_print;
500
#else
501
#define ahc_seqaddr1_print(regvalue, cur_col, wrap) \
502
    ahc_print_register(NULL, 0, "SEQADDR1", 0x63, regvalue, cur_col, wrap)
503
#endif
504

505
#if AIC_DEBUG_REGISTERS
506
ahc_reg_print_t ahc_accum_print;
507
#else
508
#define ahc_accum_print(regvalue, cur_col, wrap) \
509
    ahc_print_register(NULL, 0, "ACCUM", 0x64, regvalue, cur_col, wrap)
510
#endif
511

512
#if AIC_DEBUG_REGISTERS
513
ahc_reg_print_t ahc_sindex_print;
514
#else
515
#define ahc_sindex_print(regvalue, cur_col, wrap) \
516
    ahc_print_register(NULL, 0, "SINDEX", 0x65, regvalue, cur_col, wrap)
517
#endif
518

519
#if AIC_DEBUG_REGISTERS
520
ahc_reg_print_t ahc_dindex_print;
521
#else
522
#define ahc_dindex_print(regvalue, cur_col, wrap) \
523
    ahc_print_register(NULL, 0, "DINDEX", 0x66, regvalue, cur_col, wrap)
524
#endif
525

526
#if AIC_DEBUG_REGISTERS
527
ahc_reg_print_t ahc_allones_print;
528
#else
529
#define ahc_allones_print(regvalue, cur_col, wrap) \
530
    ahc_print_register(NULL, 0, "ALLONES", 0x69, regvalue, cur_col, wrap)
531
#endif
532

533
#if AIC_DEBUG_REGISTERS
534
ahc_reg_print_t ahc_none_print;
535
#else
536
#define ahc_none_print(regvalue, cur_col, wrap) \
537
    ahc_print_register(NULL, 0, "NONE", 0x6a, regvalue, cur_col, wrap)
538
#endif
539

540
#if AIC_DEBUG_REGISTERS
541
ahc_reg_print_t ahc_allzeros_print;
542
#else
543
#define ahc_allzeros_print(regvalue, cur_col, wrap) \
544
    ahc_print_register(NULL, 0, "ALLZEROS", 0x6a, regvalue, cur_col, wrap)
545
#endif
546

547
#if AIC_DEBUG_REGISTERS
548
ahc_reg_print_t ahc_flags_print;
549
#else
550
#define ahc_flags_print(regvalue, cur_col, wrap) \
551
    ahc_print_register(NULL, 0, "FLAGS", 0x6b, regvalue, cur_col, wrap)
552
#endif
553

554
#if AIC_DEBUG_REGISTERS
555
ahc_reg_print_t ahc_sindir_print;
556
#else
557
#define ahc_sindir_print(regvalue, cur_col, wrap) \
558
    ahc_print_register(NULL, 0, "SINDIR", 0x6c, regvalue, cur_col, wrap)
559
#endif
560

561
#if AIC_DEBUG_REGISTERS
562
ahc_reg_print_t ahc_dindir_print;
563
#else
564
#define ahc_dindir_print(regvalue, cur_col, wrap) \
565
    ahc_print_register(NULL, 0, "DINDIR", 0x6d, regvalue, cur_col, wrap)
566
#endif
567

568
#if AIC_DEBUG_REGISTERS
569
ahc_reg_print_t ahc_function1_print;
570
#else
571
#define ahc_function1_print(regvalue, cur_col, wrap) \
572
    ahc_print_register(NULL, 0, "FUNCTION1", 0x6e, regvalue, cur_col, wrap)
573
#endif
574

575
#if AIC_DEBUG_REGISTERS
576
ahc_reg_print_t ahc_stack_print;
577
#else
578
#define ahc_stack_print(regvalue, cur_col, wrap) \
579
    ahc_print_register(NULL, 0, "STACK", 0x6f, regvalue, cur_col, wrap)
580
#endif
581

582
#if AIC_DEBUG_REGISTERS
583
ahc_reg_print_t ahc_targ_offset_print;
584
#else
585
#define ahc_targ_offset_print(regvalue, cur_col, wrap) \
586
    ahc_print_register(NULL, 0, "TARG_OFFSET", 0x70, regvalue, cur_col, wrap)
587
#endif
588

589
#if AIC_DEBUG_REGISTERS
590
ahc_reg_print_t ahc_sram_base_print;
591
#else
592
#define ahc_sram_base_print(regvalue, cur_col, wrap) \
593
    ahc_print_register(NULL, 0, "SRAM_BASE", 0x70, regvalue, cur_col, wrap)
594
#endif
595

596
#if AIC_DEBUG_REGISTERS
597
ahc_reg_print_t ahc_dscommand0_print;
598
#else
599
#define ahc_dscommand0_print(regvalue, cur_col, wrap) \
600
    ahc_print_register(NULL, 0, "DSCOMMAND0", 0x84, regvalue, cur_col, wrap)
601
#endif
602

603
#if AIC_DEBUG_REGISTERS
604
ahc_reg_print_t ahc_bctl_print;
605
#else
606
#define ahc_bctl_print(regvalue, cur_col, wrap) \
607
    ahc_print_register(NULL, 0, "BCTL", 0x84, regvalue, cur_col, wrap)
608
#endif
609

610
#if AIC_DEBUG_REGISTERS
611
ahc_reg_print_t ahc_bustime_print;
612
#else
613
#define ahc_bustime_print(regvalue, cur_col, wrap) \
614
    ahc_print_register(NULL, 0, "BUSTIME", 0x85, regvalue, cur_col, wrap)
615
#endif
616

617
#if AIC_DEBUG_REGISTERS
618
ahc_reg_print_t ahc_dscommand1_print;
619
#else
620
#define ahc_dscommand1_print(regvalue, cur_col, wrap) \
621
    ahc_print_register(NULL, 0, "DSCOMMAND1", 0x85, regvalue, cur_col, wrap)
622
#endif
623

624
#if AIC_DEBUG_REGISTERS
625
ahc_reg_print_t ahc_busspd_print;
626
#else
627
#define ahc_busspd_print(regvalue, cur_col, wrap) \
628
    ahc_print_register(NULL, 0, "BUSSPD", 0x86, regvalue, cur_col, wrap)
629
#endif
630

631
#if AIC_DEBUG_REGISTERS
632
ahc_reg_print_t ahc_hs_mailbox_print;
633
#else
634
#define ahc_hs_mailbox_print(regvalue, cur_col, wrap) \
635
    ahc_print_register(NULL, 0, "HS_MAILBOX", 0x86, regvalue, cur_col, wrap)
636
#endif
637

638
#if AIC_DEBUG_REGISTERS
639
ahc_reg_print_t ahc_dspcistatus_print;
640
#else
641
#define ahc_dspcistatus_print(regvalue, cur_col, wrap) \
642
    ahc_print_register(NULL, 0, "DSPCISTATUS", 0x86, regvalue, cur_col, wrap)
643
#endif
644

645
#if AIC_DEBUG_REGISTERS
646
ahc_reg_print_t ahc_hcntrl_print;
647
#else
648
#define ahc_hcntrl_print(regvalue, cur_col, wrap) \
649
    ahc_print_register(NULL, 0, "HCNTRL", 0x87, regvalue, cur_col, wrap)
650
#endif
651

652
#if AIC_DEBUG_REGISTERS
653
ahc_reg_print_t ahc_haddr_print;
654
#else
655
#define ahc_haddr_print(regvalue, cur_col, wrap) \
656
    ahc_print_register(NULL, 0, "HADDR", 0x88, regvalue, cur_col, wrap)
657
#endif
658

659
#if AIC_DEBUG_REGISTERS
660
ahc_reg_print_t ahc_hcnt_print;
661
#else
662
#define ahc_hcnt_print(regvalue, cur_col, wrap) \
663
    ahc_print_register(NULL, 0, "HCNT", 0x8c, regvalue, cur_col, wrap)
664
#endif
665

666
#if AIC_DEBUG_REGISTERS
667
ahc_reg_print_t ahc_scbptr_print;
668
#else
669
#define ahc_scbptr_print(regvalue, cur_col, wrap) \
670
    ahc_print_register(NULL, 0, "SCBPTR", 0x90, regvalue, cur_col, wrap)
671
#endif
672

673
#if AIC_DEBUG_REGISTERS
674
ahc_reg_print_t ahc_intstat_print;
675
#else
676
#define ahc_intstat_print(regvalue, cur_col, wrap) \
677
    ahc_print_register(NULL, 0, "INTSTAT", 0x91, regvalue, cur_col, wrap)
678
#endif
679

680
#if AIC_DEBUG_REGISTERS
681
ahc_reg_print_t ahc_error_print;
682
#else
683
#define ahc_error_print(regvalue, cur_col, wrap) \
684
    ahc_print_register(NULL, 0, "ERROR", 0x92, regvalue, cur_col, wrap)
685
#endif
686

687
#if AIC_DEBUG_REGISTERS
688
ahc_reg_print_t ahc_clrint_print;
689
#else
690
#define ahc_clrint_print(regvalue, cur_col, wrap) \
691
    ahc_print_register(NULL, 0, "CLRINT", 0x92, regvalue, cur_col, wrap)
692
#endif
693

694
#if AIC_DEBUG_REGISTERS
695
ahc_reg_print_t ahc_dfcntrl_print;
696
#else
697
#define ahc_dfcntrl_print(regvalue, cur_col, wrap) \
698
    ahc_print_register(NULL, 0, "DFCNTRL", 0x93, regvalue, cur_col, wrap)
699
#endif
700

701
#if AIC_DEBUG_REGISTERS
702
ahc_reg_print_t ahc_dfstatus_print;
703
#else
704
#define ahc_dfstatus_print(regvalue, cur_col, wrap) \
705
    ahc_print_register(NULL, 0, "DFSTATUS", 0x94, regvalue, cur_col, wrap)
706
#endif
707

708
#if AIC_DEBUG_REGISTERS
709
ahc_reg_print_t ahc_dfwaddr_print;
710
#else
711
#define ahc_dfwaddr_print(regvalue, cur_col, wrap) \
712
    ahc_print_register(NULL, 0, "DFWADDR", 0x95, regvalue, cur_col, wrap)
713
#endif
714

715
#if AIC_DEBUG_REGISTERS
716
ahc_reg_print_t ahc_dfraddr_print;
717
#else
718
#define ahc_dfraddr_print(regvalue, cur_col, wrap) \
719
    ahc_print_register(NULL, 0, "DFRADDR", 0x97, regvalue, cur_col, wrap)
720
#endif
721

722
#if AIC_DEBUG_REGISTERS
723
ahc_reg_print_t ahc_dfdat_print;
724
#else
725
#define ahc_dfdat_print(regvalue, cur_col, wrap) \
726
    ahc_print_register(NULL, 0, "DFDAT", 0x99, regvalue, cur_col, wrap)
727
#endif
728

729
#if AIC_DEBUG_REGISTERS
730
ahc_reg_print_t ahc_scbcnt_print;
731
#else
732
#define ahc_scbcnt_print(regvalue, cur_col, wrap) \
733
    ahc_print_register(NULL, 0, "SCBCNT", 0x9a, regvalue, cur_col, wrap)
734
#endif
735

736
#if AIC_DEBUG_REGISTERS
737
ahc_reg_print_t ahc_qinfifo_print;
738
#else
739
#define ahc_qinfifo_print(regvalue, cur_col, wrap) \
740
    ahc_print_register(NULL, 0, "QINFIFO", 0x9b, regvalue, cur_col, wrap)
741
#endif
742

743
#if AIC_DEBUG_REGISTERS
744
ahc_reg_print_t ahc_qincnt_print;
745
#else
746
#define ahc_qincnt_print(regvalue, cur_col, wrap) \
747
    ahc_print_register(NULL, 0, "QINCNT", 0x9c, regvalue, cur_col, wrap)
748
#endif
749

750
#if AIC_DEBUG_REGISTERS
751
ahc_reg_print_t ahc_crccontrol1_print;
752
#else
753
#define ahc_crccontrol1_print(regvalue, cur_col, wrap) \
754
    ahc_print_register(NULL, 0, "CRCCONTROL1", 0x9d, regvalue, cur_col, wrap)
755
#endif
756

757
#if AIC_DEBUG_REGISTERS
758
ahc_reg_print_t ahc_qoutfifo_print;
759
#else
760
#define ahc_qoutfifo_print(regvalue, cur_col, wrap) \
761
    ahc_print_register(NULL, 0, "QOUTFIFO", 0x9d, regvalue, cur_col, wrap)
762
#endif
763

764
#if AIC_DEBUG_REGISTERS
765
ahc_reg_print_t ahc_qoutcnt_print;
766
#else
767
#define ahc_qoutcnt_print(regvalue, cur_col, wrap) \
768
    ahc_print_register(NULL, 0, "QOUTCNT", 0x9e, regvalue, cur_col, wrap)
769
#endif
770

771
#if AIC_DEBUG_REGISTERS
772
ahc_reg_print_t ahc_scsiphase_print;
773
#else
774
#define ahc_scsiphase_print(regvalue, cur_col, wrap) \
775
    ahc_print_register(NULL, 0, "SCSIPHASE", 0x9e, regvalue, cur_col, wrap)
776
#endif
777

778
#if AIC_DEBUG_REGISTERS
779
ahc_reg_print_t ahc_sfunct_print;
780
#else
781
#define ahc_sfunct_print(regvalue, cur_col, wrap) \
782
    ahc_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap)
783
#endif
784

785
#if AIC_DEBUG_REGISTERS
786
ahc_reg_print_t ahc_scb_base_print;
787
#else
788
#define ahc_scb_base_print(regvalue, cur_col, wrap) \
789
    ahc_print_register(NULL, 0, "SCB_BASE", 0xa0, regvalue, cur_col, wrap)
790
#endif
791

792
#if AIC_DEBUG_REGISTERS
793
ahc_reg_print_t ahc_scb_cdb_ptr_print;
794
#else
795
#define ahc_scb_cdb_ptr_print(regvalue, cur_col, wrap) \
796
    ahc_print_register(NULL, 0, "SCB_CDB_PTR", 0xa0, regvalue, cur_col, wrap)
797
#endif
798

799
#if AIC_DEBUG_REGISTERS
800
ahc_reg_print_t ahc_scb_residual_sgptr_print;
801
#else
802
#define ahc_scb_residual_sgptr_print(regvalue, cur_col, wrap) \
803
    ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0xa4, regvalue, cur_col, wrap)
804
#endif
805

806
#if AIC_DEBUG_REGISTERS
807
ahc_reg_print_t ahc_scb_scsi_status_print;
808
#else
809
#define ahc_scb_scsi_status_print(regvalue, cur_col, wrap) \
810
    ahc_print_register(NULL, 0, "SCB_SCSI_STATUS", 0xa8, regvalue, cur_col, wrap)
811
#endif
812

813
#if AIC_DEBUG_REGISTERS
814
ahc_reg_print_t ahc_scb_target_phases_print;
815
#else
816
#define ahc_scb_target_phases_print(regvalue, cur_col, wrap) \
817
    ahc_print_register(NULL, 0, "SCB_TARGET_PHASES", 0xa9, regvalue, cur_col, wrap)
818
#endif
819

820
#if AIC_DEBUG_REGISTERS
821
ahc_reg_print_t ahc_scb_target_data_dir_print;
822
#else
823
#define ahc_scb_target_data_dir_print(regvalue, cur_col, wrap) \
824
    ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0xaa, regvalue, cur_col, wrap)
825
#endif
826

827
#if AIC_DEBUG_REGISTERS
828
ahc_reg_print_t ahc_scb_target_itag_print;
829
#else
830
#define ahc_scb_target_itag_print(regvalue, cur_col, wrap) \
831
    ahc_print_register(NULL, 0, "SCB_TARGET_ITAG", 0xab, regvalue, cur_col, wrap)
832
#endif
833

834
#if AIC_DEBUG_REGISTERS
835
ahc_reg_print_t ahc_scb_dataptr_print;
836
#else
837
#define ahc_scb_dataptr_print(regvalue, cur_col, wrap) \
838
    ahc_print_register(NULL, 0, "SCB_DATAPTR", 0xac, regvalue, cur_col, wrap)
839
#endif
840

841
#if AIC_DEBUG_REGISTERS
842
ahc_reg_print_t ahc_scb_datacnt_print;
843
#else
844
#define ahc_scb_datacnt_print(regvalue, cur_col, wrap) \
845
    ahc_print_register(NULL, 0, "SCB_DATACNT", 0xb0, regvalue, cur_col, wrap)
846
#endif
847

848
#if AIC_DEBUG_REGISTERS
849
ahc_reg_print_t ahc_scb_sgptr_print;
850
#else
851
#define ahc_scb_sgptr_print(regvalue, cur_col, wrap) \
852
    ahc_print_register(NULL, 0, "SCB_SGPTR", 0xb4, regvalue, cur_col, wrap)
853
#endif
854

855
#if AIC_DEBUG_REGISTERS
856
ahc_reg_print_t ahc_scb_control_print;
857
#else
858
#define ahc_scb_control_print(regvalue, cur_col, wrap) \
859
    ahc_print_register(NULL, 0, "SCB_CONTROL", 0xb8, regvalue, cur_col, wrap)
860
#endif
861

862
#if AIC_DEBUG_REGISTERS
863
ahc_reg_print_t ahc_scb_scsiid_print;
864
#else
865
#define ahc_scb_scsiid_print(regvalue, cur_col, wrap) \
866
    ahc_print_register(NULL, 0, "SCB_SCSIID", 0xb9, regvalue, cur_col, wrap)
867
#endif
868

869
#if AIC_DEBUG_REGISTERS
870
ahc_reg_print_t ahc_scb_lun_print;
871
#else
872
#define ahc_scb_lun_print(regvalue, cur_col, wrap) \
873
    ahc_print_register(NULL, 0, "SCB_LUN", 0xba, regvalue, cur_col, wrap)
874
#endif
875

876
#if AIC_DEBUG_REGISTERS
877
ahc_reg_print_t ahc_scb_tag_print;
878
#else
879
#define ahc_scb_tag_print(regvalue, cur_col, wrap) \
880
    ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap)
881
#endif
882

883
#if AIC_DEBUG_REGISTERS
884
ahc_reg_print_t ahc_scb_cdb_len_print;
885
#else
886
#define ahc_scb_cdb_len_print(regvalue, cur_col, wrap) \
887
    ahc_print_register(NULL, 0, "SCB_CDB_LEN", 0xbc, regvalue, cur_col, wrap)
888
#endif
889

890
#if AIC_DEBUG_REGISTERS
891
ahc_reg_print_t ahc_scb_scsirate_print;
892
#else
893
#define ahc_scb_scsirate_print(regvalue, cur_col, wrap) \
894
    ahc_print_register(NULL, 0, "SCB_SCSIRATE", 0xbd, regvalue, cur_col, wrap)
895
#endif
896

897
#if AIC_DEBUG_REGISTERS
898
ahc_reg_print_t ahc_scb_scsioffset_print;
899
#else
900
#define ahc_scb_scsioffset_print(regvalue, cur_col, wrap) \
901
    ahc_print_register(NULL, 0, "SCB_SCSIOFFSET", 0xbe, regvalue, cur_col, wrap)
902
#endif
903

904
#if AIC_DEBUG_REGISTERS
905
ahc_reg_print_t ahc_scb_next_print;
906
#else
907
#define ahc_scb_next_print(regvalue, cur_col, wrap) \
908
    ahc_print_register(NULL, 0, "SCB_NEXT", 0xbf, regvalue, cur_col, wrap)
909
#endif
910

911
#if AIC_DEBUG_REGISTERS
912
ahc_reg_print_t ahc_scb_64_spare_print;
913
#else
914
#define ahc_scb_64_spare_print(regvalue, cur_col, wrap) \
915
    ahc_print_register(NULL, 0, "SCB_64_SPARE", 0xc0, regvalue, cur_col, wrap)
916
#endif
917

918
#if AIC_DEBUG_REGISTERS
919
ahc_reg_print_t ahc_seectl_2840_print;
920
#else
921
#define ahc_seectl_2840_print(regvalue, cur_col, wrap) \
922
    ahc_print_register(NULL, 0, "SEECTL_2840", 0xc0, regvalue, cur_col, wrap)
923
#endif
924

925
#if AIC_DEBUG_REGISTERS
926
ahc_reg_print_t ahc_status_2840_print;
927
#else
928
#define ahc_status_2840_print(regvalue, cur_col, wrap) \
929
    ahc_print_register(NULL, 0, "STATUS_2840", 0xc1, regvalue, cur_col, wrap)
930
#endif
931

932
#if AIC_DEBUG_REGISTERS
933
ahc_reg_print_t ahc_scb_64_btt_print;
934
#else
935
#define ahc_scb_64_btt_print(regvalue, cur_col, wrap) \
936
    ahc_print_register(NULL, 0, "SCB_64_BTT", 0xd0, regvalue, cur_col, wrap)
937
#endif
938

939
#if AIC_DEBUG_REGISTERS
940
ahc_reg_print_t ahc_cchaddr_print;
941
#else
942
#define ahc_cchaddr_print(regvalue, cur_col, wrap) \
943
    ahc_print_register(NULL, 0, "CCHADDR", 0xe0, regvalue, cur_col, wrap)
944
#endif
945

946
#if AIC_DEBUG_REGISTERS
947
ahc_reg_print_t ahc_cchcnt_print;
948
#else
949
#define ahc_cchcnt_print(regvalue, cur_col, wrap) \
950
    ahc_print_register(NULL, 0, "CCHCNT", 0xe8, regvalue, cur_col, wrap)
951
#endif
952

953
#if AIC_DEBUG_REGISTERS
954
ahc_reg_print_t ahc_ccsgram_print;
955
#else
956
#define ahc_ccsgram_print(regvalue, cur_col, wrap) \
957
    ahc_print_register(NULL, 0, "CCSGRAM", 0xe9, regvalue, cur_col, wrap)
958
#endif
959

960
#if AIC_DEBUG_REGISTERS
961
ahc_reg_print_t ahc_ccsgaddr_print;
962
#else
963
#define ahc_ccsgaddr_print(regvalue, cur_col, wrap) \
964
    ahc_print_register(NULL, 0, "CCSGADDR", 0xea, regvalue, cur_col, wrap)
965
#endif
966

967
#if AIC_DEBUG_REGISTERS
968
ahc_reg_print_t ahc_ccsgctl_print;
969
#else
970
#define ahc_ccsgctl_print(regvalue, cur_col, wrap) \
971
    ahc_print_register(NULL, 0, "CCSGCTL", 0xeb, regvalue, cur_col, wrap)
972
#endif
973

974
#if AIC_DEBUG_REGISTERS
975
ahc_reg_print_t ahc_ccscbram_print;
976
#else
977
#define ahc_ccscbram_print(regvalue, cur_col, wrap) \
978
    ahc_print_register(NULL, 0, "CCSCBRAM", 0xec, regvalue, cur_col, wrap)
979
#endif
980

981
#if AIC_DEBUG_REGISTERS
982
ahc_reg_print_t ahc_ccscbaddr_print;
983
#else
984
#define ahc_ccscbaddr_print(regvalue, cur_col, wrap) \
985
    ahc_print_register(NULL, 0, "CCSCBADDR", 0xed, regvalue, cur_col, wrap)
986
#endif
987

988
#if AIC_DEBUG_REGISTERS
989
ahc_reg_print_t ahc_ccscbctl_print;
990
#else
991
#define ahc_ccscbctl_print(regvalue, cur_col, wrap) \
992
    ahc_print_register(NULL, 0, "CCSCBCTL", 0xee, regvalue, cur_col, wrap)
993
#endif
994

995
#if AIC_DEBUG_REGISTERS
996
ahc_reg_print_t ahc_ccscbcnt_print;
997
#else
998
#define ahc_ccscbcnt_print(regvalue, cur_col, wrap) \
999
    ahc_print_register(NULL, 0, "CCSCBCNT", 0xef, regvalue, cur_col, wrap)
1000
#endif
1001

1002
#if AIC_DEBUG_REGISTERS
1003
ahc_reg_print_t ahc_scbbaddr_print;
1004
#else
1005
#define ahc_scbbaddr_print(regvalue, cur_col, wrap) \
1006
    ahc_print_register(NULL, 0, "SCBBADDR", 0xf0, regvalue, cur_col, wrap)
1007
#endif
1008

1009
#if AIC_DEBUG_REGISTERS
1010
ahc_reg_print_t ahc_ccscbptr_print;
1011
#else
1012
#define ahc_ccscbptr_print(regvalue, cur_col, wrap) \
1013
    ahc_print_register(NULL, 0, "CCSCBPTR", 0xf1, regvalue, cur_col, wrap)
1014
#endif
1015

1016
#if AIC_DEBUG_REGISTERS
1017
ahc_reg_print_t ahc_hnscb_qoff_print;
1018
#else
1019
#define ahc_hnscb_qoff_print(regvalue, cur_col, wrap) \
1020
    ahc_print_register(NULL, 0, "HNSCB_QOFF", 0xf4, regvalue, cur_col, wrap)
1021
#endif
1022

1023
#if AIC_DEBUG_REGISTERS
1024
ahc_reg_print_t ahc_snscb_qoff_print;
1025
#else
1026
#define ahc_snscb_qoff_print(regvalue, cur_col, wrap) \
1027
    ahc_print_register(NULL, 0, "SNSCB_QOFF", 0xf6, regvalue, cur_col, wrap)
1028
#endif
1029

1030
#if AIC_DEBUG_REGISTERS
1031
ahc_reg_print_t ahc_sdscb_qoff_print;
1032
#else
1033
#define ahc_sdscb_qoff_print(regvalue, cur_col, wrap) \
1034
    ahc_print_register(NULL, 0, "SDSCB_QOFF", 0xf8, regvalue, cur_col, wrap)
1035
#endif
1036

1037
#if AIC_DEBUG_REGISTERS
1038
ahc_reg_print_t ahc_qoff_ctlsta_print;
1039
#else
1040
#define ahc_qoff_ctlsta_print(regvalue, cur_col, wrap) \
1041
    ahc_print_register(NULL, 0, "QOFF_CTLSTA", 0xfa, regvalue, cur_col, wrap)
1042
#endif
1043

1044
#if AIC_DEBUG_REGISTERS
1045
ahc_reg_print_t ahc_dff_thrsh_print;
1046
#else
1047
#define ahc_dff_thrsh_print(regvalue, cur_col, wrap) \
1048
    ahc_print_register(NULL, 0, "DFF_THRSH", 0xfb, regvalue, cur_col, wrap)
1049
#endif
1050

1051
#if AIC_DEBUG_REGISTERS
1052
ahc_reg_print_t ahc_sg_cache_shadow_print;
1053
#else
1054
#define ahc_sg_cache_shadow_print(regvalue, cur_col, wrap) \
1055
    ahc_print_register(NULL, 0, "SG_CACHE_SHADOW", 0xfc, regvalue, cur_col, wrap)
1056
#endif
1057

1058
#if AIC_DEBUG_REGISTERS
1059
ahc_reg_print_t ahc_sg_cache_pre_print;
1060
#else
1061
#define ahc_sg_cache_pre_print(regvalue, cur_col, wrap) \
1062
    ahc_print_register(NULL, 0, "SG_CACHE_PRE", 0xfc, regvalue, cur_col, wrap)
1063
#endif
1064

1065
#define	SCSISEQ         		0x00
1066
#define		TEMODE          	0x80
1067
#define		SCSIRSTO        	0x01
1068

1069
#define	SXFRCTL0        		0x01
1070
#define		DFON            	0x80
1071
#define		DFPEXP          	0x40
1072
#define		FAST20          	0x20
1073
#define		CLRSTCNT        	0x10
1074
#define		SPIOEN          	0x08
1075
#define		SCAMEN          	0x04
1076
#define		CLRCHN          	0x02
1077

1078
#define	SXFRCTL1        		0x02
1079
#define		STIMESEL        	0x18
1080
#define		BITBUCKET       	0x80
1081
#define		SWRAPEN         	0x40
1082
#define		ENSTIMER        	0x04
1083
#define		ACTNEGEN        	0x02
1084
#define		STPWEN          	0x01
1085

1086
#define	SCSISIGI        		0x03
1087
#define		P_DATAIN_DT     	0x60
1088
#define		P_DATAOUT_DT    	0x20
1089
#define		ATNI            	0x10
1090
#define		SELI            	0x08
1091
#define		BSYI            	0x04
1092
#define		REQI            	0x02
1093
#define		ACKI            	0x01
1094

1095
#define	SCSISIGO        		0x03
1096
#define		CDO             	0x80
1097
#define		IOO             	0x40
1098
#define		MSGO            	0x20
1099
#define		ATNO            	0x10
1100
#define		SELO            	0x08
1101
#define		BSYO            	0x04
1102
#define		REQO            	0x02
1103
#define		ACKO            	0x01
1104

1105
#define	SCSIRATE        		0x04
1106
#define		SXFR            	0x70
1107
#define		SXFR_ULTRA2     	0x0f
1108
#define		SOFS            	0x0f
1109
#define		WIDEXFER        	0x80
1110
#define		ENABLE_CRC      	0x40
1111
#define		SINGLE_EDGE     	0x10
1112

1113
#define	SCSIID          		0x05
1114
#define	SCSIOFFSET      		0x05
1115
#define		SOFS_ULTRA2     	0x7f
1116

1117
#define	SCSIDATL        		0x06
1118

1119
#define	SCSIDATH        		0x07
1120

1121
#define	OPTIONMODE      		0x08
1122
#define		OPTIONMODE_DEFAULTS	0x03
1123
#define		AUTORATEEN      	0x80
1124
#define		AUTOACKEN       	0x40
1125
#define		ATNMGMNTEN      	0x20
1126
#define		BUSFREEREV      	0x10
1127
#define		EXPPHASEDIS     	0x08
1128
#define		SCSIDATL_IMGEN  	0x04
1129
#define		AUTO_MSGOUT_DE  	0x02
1130
#define		DIS_MSGIN_DUALEDGE	0x01
1131

1132
#define	STCNT           		0x08
1133

1134
#define	TARGCRCCNT      		0x0a
1135

1136
#define	CLRSINT0        		0x0b
1137
#define		CLRSELDO        	0x40
1138
#define		CLRSELDI        	0x20
1139
#define		CLRSELINGO      	0x10
1140
#define		CLRIOERR        	0x08
1141
#define		CLRSWRAP        	0x08
1142
#define		CLRSPIORDY      	0x02
1143

1144
#define	SSTAT0          		0x0b
1145
#define		TARGET          	0x80
1146
#define		SELDO           	0x40
1147
#define		SELDI           	0x20
1148
#define		SELINGO         	0x10
1149
#define		SWRAP           	0x08
1150
#define		IOERR           	0x08
1151
#define		SDONE           	0x04
1152
#define		SPIORDY         	0x02
1153
#define		DMADONE         	0x01
1154

1155
#define	CLRSINT1        		0x0c
1156
#define		CLRSELTIMEO     	0x80
1157
#define		CLRATNO         	0x40
1158
#define		CLRSCSIRSTI     	0x20
1159
#define		CLRBUSFREE      	0x08
1160
#define		CLRSCSIPERR     	0x04
1161
#define		CLRPHASECHG     	0x02
1162
#define		CLRREQINIT      	0x01
1163

1164
#define	SSTAT1          		0x0c
1165
#define		SELTO           	0x80
1166
#define		ATNTARG         	0x40
1167
#define		SCSIRSTI        	0x20
1168
#define		PHASEMIS        	0x10
1169
#define		BUSFREE         	0x08
1170
#define		SCSIPERR        	0x04
1171
#define		PHASECHG        	0x02
1172
#define		REQINIT         	0x01
1173

1174
#define	SSTAT2          		0x0d
1175
#define		SFCNT           	0x1f
1176
#define		OVERRUN         	0x80
1177
#define		SHVALID         	0x40
1178
#define		EXP_ACTIVE      	0x10
1179
#define		CRCVALERR       	0x08
1180
#define		CRCENDERR       	0x04
1181
#define		CRCREQERR       	0x02
1182
#define		DUAL_EDGE_ERR   	0x01
1183

1184
#define	SSTAT3          		0x0e
1185
#define		SCSICNT         	0xf0
1186
#define		U2OFFCNT        	0x7f
1187
#define		OFFCNT          	0x0f
1188

1189
#define	SCSIID_ULTRA2   		0x0f
1190

1191
#define	SIMODE0         		0x10
1192
#define		ENSELDO         	0x40
1193
#define		ENSELDI         	0x20
1194
#define		ENSELINGO       	0x10
1195
#define		ENIOERR         	0x08
1196
#define		ENSWRAP         	0x08
1197
#define		ENSDONE         	0x04
1198
#define		ENSPIORDY       	0x02
1199
#define		ENDMADONE       	0x01
1200

1201
#define	SIMODE1         		0x11
1202
#define		ENSELTIMO       	0x80
1203
#define		ENATNTARG       	0x40
1204
#define		ENSCSIRST       	0x20
1205
#define		ENPHASEMIS      	0x10
1206
#define		ENBUSFREE       	0x08
1207
#define		ENSCSIPERR      	0x04
1208
#define		ENPHASECHG      	0x02
1209
#define		ENREQINIT       	0x01
1210

1211
#define	SCSIBUSL        		0x12
1212

1213
#define	SXFRCTL2        		0x13
1214
#define		ASYNC_SETUP     	0x07
1215
#define		AUTORSTDIS      	0x10
1216
#define		CMDDMAEN        	0x08
1217

1218
#define	SCSIBUSH        		0x13
1219

1220
#define	SHADDR          		0x14
1221

1222
#define	SELTIMER        		0x18
1223
#define	TARGIDIN        		0x18
1224
#define		STAGE6          	0x20
1225
#define		STAGE5          	0x10
1226
#define		STAGE4          	0x08
1227
#define		STAGE3          	0x04
1228
#define		STAGE2          	0x02
1229
#define		STAGE1          	0x01
1230

1231
#define	SELID           		0x19
1232
#define		SELID_MASK      	0xf0
1233
#define		ONEBIT          	0x08
1234

1235
#define	SCAMCTL         		0x1a
1236
#define		SCAMLVL         	0x03
1237
#define		ENSCAMSELO      	0x80
1238
#define		CLRSCAMSELID    	0x40
1239
#define		ALTSTIM         	0x20
1240
#define		DFLTTID         	0x10
1241

1242
#define	TARGID          		0x1b
1243

1244
#define	SPIOCAP         		0x1b
1245
#define		SOFT1           	0x80
1246
#define		SOFT0           	0x40
1247
#define		SOFTCMDEN       	0x20
1248
#define		EXT_BRDCTL      	0x10
1249
#define		SEEPROM         	0x08
1250
#define		EEPROM          	0x04
1251
#define		ROM             	0x02
1252
#define		SSPIOCPS        	0x01
1253

1254
#define	BRDCTL          		0x1d
1255
#define		BRDDAT7         	0x80
1256
#define		BRDDAT6         	0x40
1257
#define		BRDDAT5         	0x20
1258
#define		BRDDAT4         	0x10
1259
#define		BRDSTB          	0x10
1260
#define		BRDDAT3         	0x08
1261
#define		BRDCS           	0x08
1262
#define		BRDDAT2         	0x04
1263
#define		BRDRW           	0x04
1264
#define		BRDCTL1         	0x02
1265
#define		BRDRW_ULTRA2    	0x02
1266
#define		BRDCTL0         	0x01
1267
#define		BRDSTB_ULTRA2   	0x01
1268

1269
#define	SEECTL          		0x1e
1270
#define		EXTARBACK       	0x80
1271
#define		EXTARBREQ       	0x40
1272
#define		SEEMS           	0x20
1273
#define		SEERDY          	0x10
1274
#define		SEECS           	0x08
1275
#define		SEECK           	0x04
1276
#define		SEEDO           	0x02
1277
#define		SEEDI           	0x01
1278

1279
#define	SBLKCTL         		0x1f
1280
#define		DIAGLEDEN       	0x80
1281
#define		DIAGLEDON       	0x40
1282
#define		AUTOFLUSHDIS    	0x20
1283
#define		ENAB40          	0x08
1284
#define		SELBUSB         	0x08
1285
#define		ENAB20          	0x04
1286
#define		SELWIDE         	0x02
1287
#define		XCVR            	0x01
1288

1289
#define	BUSY_TARGETS    		0x20
1290
#define	TARG_SCSIRATE   		0x20
1291

1292
#define	ULTRA_ENB       		0x30
1293
#define	CMDSIZE_TABLE   		0x30
1294

1295
#define	DISC_DSB        		0x32
1296

1297
#define	CMDSIZE_TABLE_TAIL		0x34
1298

1299
#define	MWI_RESIDUAL    		0x38
1300

1301
#define	NEXT_QUEUED_SCB 		0x39
1302

1303
#define	MSG_OUT         		0x3a
1304

1305
#define	DMAPARAMS       		0x3b
1306
#define		PRELOADEN       	0x80
1307
#define		WIDEODD         	0x40
1308
#define		SCSIEN          	0x20
1309
#define		SDMAENACK       	0x10
1310
#define		SDMAEN          	0x10
1311
#define		HDMAEN          	0x08
1312
#define		HDMAENACK       	0x08
1313
#define		DIRECTION       	0x04
1314
#define		FIFOFLUSH       	0x02
1315
#define		FIFORESET       	0x01
1316

1317
#define	SEQ_FLAGS       		0x3c
1318
#define		NOT_IDENTIFIED  	0x80
1319
#define		NO_CDB_SENT     	0x40
1320
#define		TARGET_CMD_IS_TAGGED	0x40
1321
#define		DPHASE          	0x20
1322
#define		TARG_CMD_PENDING	0x10
1323
#define		CMDPHASE_PENDING	0x08
1324
#define		DPHASE_PENDING  	0x04
1325
#define		SPHASE_PENDING  	0x02
1326
#define		NO_DISCONNECT   	0x01
1327

1328
#define	SAVED_SCSIID    		0x3d
1329

1330
#define	SAVED_LUN       		0x3e
1331

1332
#define	LASTPHASE       		0x3f
1333
#define		PHASE_MASK      	0xe0
1334
#define		P_MESGIN        	0xe0
1335
#define		P_STATUS        	0xc0
1336
#define		P_MESGOUT       	0xa0
1337
#define		P_COMMAND       	0x80
1338
#define		P_DATAIN        	0x40
1339
#define		P_BUSFREE       	0x01
1340
#define		P_DATAOUT       	0x00
1341
#define		CDI             	0x80
1342
#define		IOI             	0x40
1343
#define		MSGI            	0x20
1344

1345
#define	WAITING_SCBH    		0x40
1346

1347
#define	DISCONNECTED_SCBH		0x41
1348

1349
#define	FREE_SCBH       		0x42
1350

1351
#define	COMPLETE_SCBH   		0x43
1352

1353
#define	HSCB_ADDR       		0x44
1354

1355
#define	SHARED_DATA_ADDR		0x48
1356

1357
#define	KERNEL_QINPOS   		0x4c
1358

1359
#define	QINPOS          		0x4d
1360

1361
#define	QOUTPOS         		0x4e
1362

1363
#define	KERNEL_TQINPOS  		0x4f
1364

1365
#define	TQINPOS         		0x50
1366

1367
#define	ARG_1           		0x51
1368
#define	RETURN_1        		0x51
1369
#define		SEND_MSG        	0x80
1370
#define		SEND_SENSE      	0x40
1371
#define		SEND_REJ        	0x20
1372
#define		MSGOUT_PHASEMIS 	0x10
1373
#define		EXIT_MSG_LOOP   	0x08
1374
#define		CONT_MSG_LOOP   	0x04
1375
#define		CONT_TARG_SESSION	0x02
1376
#define		SPARE           	0x01
1377

1378
#define	ARG_2           		0x52
1379
#define	RETURN_2        		0x52
1380

1381
#define	LAST_MSG        		0x53
1382
#define	TARG_IMMEDIATE_SCB		0x53
1383

1384
#define	SCSISEQ_TEMPLATE		0x54
1385
#define		ENSELO          	0x40
1386
#define		ENSELI          	0x20
1387
#define		ENRSELI         	0x10
1388
#define		ENAUTOATNO      	0x08
1389
#define		ENAUTOATNI      	0x04
1390
#define		ENAUTOATNP      	0x02
1391

1392
#define	HA_274_BIOSGLOBAL		0x56
1393
#define	INITIATOR_TAG   		0x56
1394
#define		HA_274_EXTENDED_TRANS	0x01
1395

1396
#define	SEQ_FLAGS2      		0x57
1397
#define		TARGET_MSG_PENDING	0x02
1398
#define		SCB_DMA         	0x01
1399

1400
#define	SCSICONF        		0x5a
1401
#define		HWSCSIID        	0x0f
1402
#define		HSCSIID         	0x07
1403
#define		TERM_ENB        	0x80
1404
#define		RESET_SCSI      	0x40
1405
#define		ENSPCHK         	0x20
1406

1407
#define	INTDEF          		0x5c
1408
#define		VECTOR          	0x0f
1409
#define		EDGE_TRIG       	0x80
1410

1411
#define	HOSTCONF        		0x5d
1412

1413
#define	HA_274_BIOSCTRL 		0x5f
1414
#define		BIOSDISABLED    	0x30
1415
#define		BIOSMODE        	0x30
1416
#define		CHANNEL_B_PRIMARY	0x08
1417

1418
#define	SEQCTL          		0x60
1419
#define		PERRORDIS       	0x80
1420
#define		PAUSEDIS        	0x40
1421
#define		FAILDIS         	0x20
1422
#define		FASTMODE        	0x10
1423
#define		BRKADRINTEN     	0x08
1424
#define		STEP            	0x04
1425
#define		SEQRESET        	0x02
1426
#define		LOADRAM         	0x01
1427

1428
#define	SEQRAM          		0x61
1429

1430
#define	SEQADDR0        		0x62
1431

1432
#define	SEQADDR1        		0x63
1433
#define		SEQADDR1_MASK   	0x01
1434

1435
#define	ACCUM           		0x64
1436

1437
#define	SINDEX          		0x65
1438

1439
#define	DINDEX          		0x66
1440

1441
#define	ALLONES         		0x69
1442

1443
#define	NONE            		0x6a
1444

1445
#define	ALLZEROS        		0x6a
1446

1447
#define	FLAGS           		0x6b
1448
#define		ZERO            	0x02
1449
#define		CARRY           	0x01
1450

1451
#define	SINDIR          		0x6c
1452

1453
#define	DINDIR          		0x6d
1454

1455
#define	FUNCTION1       		0x6e
1456

1457
#define	STACK           		0x6f
1458

1459
#define	TARG_OFFSET     		0x70
1460

1461
#define	SRAM_BASE       		0x70
1462

1463
#define	DSCOMMAND0      		0x84
1464
#define		CACHETHEN       	0x80
1465
#define		DPARCKEN        	0x40
1466
#define		MPARCKEN        	0x20
1467
#define		EXTREQLCK       	0x10
1468
#define		INTSCBRAMSEL    	0x08
1469
#define		RAMPS           	0x04
1470
#define		USCBSIZE32      	0x02
1471
#define		CIOPARCKEN      	0x01
1472

1473
#define	BCTL            		0x84
1474
#define		ACE             	0x08
1475
#define		ENABLE          	0x01
1476

1477
#define	BUSTIME         		0x85
1478
#define		BOFF            	0xf0
1479
#define		BON             	0x0f
1480

1481
#define	DSCOMMAND1      		0x85
1482
#define		DSLATT          	0xfc
1483
#define		HADDLDSEL1      	0x02
1484
#define		HADDLDSEL0      	0x01
1485

1486
#define	BUSSPD          		0x86
1487
#define		DFTHRSH         	0xc0
1488
#define		DFTHRSH_75      	0x80
1489
#define		STBOFF          	0x38
1490
#define		STBON           	0x07
1491

1492
#define	HS_MAILBOX      		0x86
1493
#define		HOST_MAILBOX    	0xf0
1494
#define		HOST_TQINPOS    	0x80
1495
#define		SEQ_MAILBOX     	0x0f
1496

1497
#define	DSPCISTATUS     		0x86
1498
#define		DFTHRSH_100     	0xc0
1499

1500
#define	HCNTRL          		0x87
1501
#define		POWRDN          	0x40
1502
#define		SWINT           	0x10
1503
#define		IRQMS           	0x08
1504
#define		PAUSE           	0x04
1505
#define		INTEN           	0x02
1506
#define		CHIPRST         	0x01
1507
#define		CHIPRSTACK      	0x01
1508

1509
#define	HADDR           		0x88
1510

1511
#define	HCNT            		0x8c
1512

1513
#define	SCBPTR          		0x90
1514

1515
#define	INTSTAT         		0x91
1516
#define		SEQINT_MASK     	0xf1
1517
#define		OUT_OF_RANGE    	0xe1
1518
#define		NO_FREE_SCB     	0xd1
1519
#define		SCB_MISMATCH    	0xc1
1520
#define		MISSED_BUSFREE  	0xb1
1521
#define		MKMSG_FAILED    	0xa1
1522
#define		DATA_OVERRUN    	0x91
1523
#define		PERR_DETECTED   	0x81
1524
#define		BAD_STATUS      	0x71
1525
#define		HOST_MSG_LOOP   	0x61
1526
#define		PDATA_REINIT    	0x51
1527
#define		IGN_WIDE_RES    	0x41
1528
#define		NO_MATCH        	0x31
1529
#define		PROTO_VIOLATION 	0x21
1530
#define		SEND_REJECT     	0x11
1531
#define		INT_PEND        	0x0f
1532
#define		BAD_PHASE       	0x01
1533
#define		BRKADRINT       	0x08
1534
#define		SCSIINT         	0x04
1535
#define		CMDCMPLT        	0x02
1536
#define		SEQINT          	0x01
1537

1538
#define	ERROR           		0x92
1539
#define		CIOPARERR       	0x80
1540
#define		PCIERRSTAT      	0x40
1541
#define		MPARERR         	0x20
1542
#define		DPARERR         	0x10
1543
#define		SQPARERR        	0x08
1544
#define		ILLOPCODE       	0x04
1545
#define		ILLSADDR        	0x02
1546
#define		ILLHADDR        	0x01
1547

1548
#define	CLRINT          		0x92
1549
#define		CLRPARERR       	0x10
1550
#define		CLRBRKADRINT    	0x08
1551
#define		CLRSCSIINT      	0x04
1552
#define		CLRCMDINT       	0x02
1553
#define		CLRSEQINT       	0x01
1554

1555
#define	DFCNTRL         		0x93
1556

1557
#define	DFSTATUS        		0x94
1558
#define		PRELOAD_AVAIL   	0x80
1559
#define		DFCACHETH       	0x40
1560
#define		FIFOQWDEMP      	0x20
1561
#define		MREQPEND        	0x10
1562
#define		HDONE           	0x08
1563
#define		DFTHRESH        	0x04
1564
#define		FIFOFULL        	0x02
1565
#define		FIFOEMP         	0x01
1566

1567
#define	DFWADDR         		0x95
1568

1569
#define	DFRADDR         		0x97
1570

1571
#define	DFDAT           		0x99
1572

1573
#define	SCBCNT          		0x9a
1574
#define		SCBCNT_MASK     	0x1f
1575
#define		SCBAUTO         	0x80
1576

1577
#define	QINFIFO         		0x9b
1578

1579
#define	QINCNT          		0x9c
1580

1581
#define	CRCCONTROL1     		0x9d
1582
#define		CRCONSEEN       	0x80
1583
#define		CRCVALCHKEN     	0x40
1584
#define		CRCENDCHKEN     	0x20
1585
#define		CRCREQCHKEN     	0x10
1586
#define		TARGCRCENDEN    	0x08
1587
#define		TARGCRCCNTEN    	0x04
1588

1589
#define	QOUTFIFO        		0x9d
1590

1591
#define	QOUTCNT         		0x9e
1592

1593
#define	SCSIPHASE       		0x9e
1594
#define		DATA_PHASE_MASK 	0x03
1595
#define		STATUS_PHASE    	0x20
1596
#define		COMMAND_PHASE   	0x10
1597
#define		MSG_IN_PHASE    	0x08
1598
#define		MSG_OUT_PHASE   	0x04
1599
#define		DATA_IN_PHASE   	0x02
1600
#define		DATA_OUT_PHASE  	0x01
1601

1602
#define	SFUNCT          		0x9f
1603
#define		ALT_MODE        	0x80
1604

1605
#define	SCB_BASE        		0xa0
1606

1607
#define	SCB_CDB_PTR     		0xa0
1608
#define	SCB_RESIDUAL_DATACNT		0xa0
1609
#define	SCB_CDB_STORE   		0xa0
1610

1611
#define	SCB_RESIDUAL_SGPTR		0xa4
1612

1613
#define	SCB_SCSI_STATUS 		0xa8
1614

1615
#define	SCB_TARGET_PHASES		0xa9
1616

1617
#define	SCB_TARGET_DATA_DIR		0xaa
1618

1619
#define	SCB_TARGET_ITAG 		0xab
1620

1621
#define	SCB_DATAPTR     		0xac
1622

1623
#define	SCB_DATACNT     		0xb0
1624
#define		SG_HIGH_ADDR_BITS	0x7f
1625
#define		SG_LAST_SEG     	0x80
1626

1627
#define	SCB_SGPTR       		0xb4
1628
#define		SG_RESID_VALID  	0x04
1629
#define		SG_FULL_RESID   	0x02
1630
#define		SG_LIST_NULL    	0x01
1631

1632
#define	SCB_CONTROL     		0xb8
1633
#define		SCB_TAG_TYPE    	0x03
1634
#define		STATUS_RCVD     	0x80
1635
#define		TARGET_SCB      	0x80
1636
#define		DISCENB         	0x40
1637
#define		TAG_ENB         	0x20
1638
#define		MK_MESSAGE      	0x10
1639
#define		ULTRAENB        	0x08
1640
#define		DISCONNECTED    	0x04
1641

1642
#define	SCB_SCSIID      		0xb9
1643
#define		TID             	0xf0
1644
#define		TWIN_TID        	0x70
1645
#define		OID             	0x0f
1646
#define		TWIN_CHNLB      	0x80
1647

1648
#define	SCB_LUN         		0xba
1649
#define		LID             	0x3f
1650
#define		SCB_XFERLEN_ODD 	0x80
1651

1652
#define	SCB_TAG         		0xbb
1653

1654
#define	SCB_CDB_LEN     		0xbc
1655

1656
#define	SCB_SCSIRATE    		0xbd
1657

1658
#define	SCB_SCSIOFFSET  		0xbe
1659

1660
#define	SCB_NEXT        		0xbf
1661

1662
#define	SCB_64_SPARE    		0xc0
1663

1664
#define	SEECTL_2840     		0xc0
1665
#define		CS_2840         	0x04
1666
#define		CK_2840         	0x02
1667
#define		DO_2840         	0x01
1668

1669
#define	STATUS_2840     		0xc1
1670
#define		BIOS_SEL        	0x60
1671
#define		ADSEL           	0x1e
1672
#define		EEPROM_TF       	0x80
1673
#define		DI_2840         	0x01
1674

1675
#define	SCB_64_BTT      		0xd0
1676

1677
#define	CCHADDR         		0xe0
1678

1679
#define	CCHCNT          		0xe8
1680

1681
#define	CCSGRAM         		0xe9
1682

1683
#define	CCSGADDR        		0xea
1684

1685
#define	CCSGCTL         		0xeb
1686
#define		CCSGDONE        	0x80
1687
#define		CCSGEN          	0x08
1688
#define		SG_FETCH_NEEDED 	0x02
1689
#define		CCSGRESET       	0x01
1690

1691
#define	CCSCBRAM        		0xec
1692

1693
#define	CCSCBADDR       		0xed
1694

1695
#define	CCSCBCTL        		0xee
1696
#define		CCSCBDONE       	0x80
1697
#define		ARRDONE         	0x40
1698
#define		CCARREN         	0x10
1699
#define		CCSCBEN         	0x08
1700
#define		CCSCBDIR        	0x04
1701
#define		CCSCBRESET      	0x01
1702

1703
#define	CCSCBCNT        		0xef
1704

1705
#define	SCBBADDR        		0xf0
1706

1707
#define	CCSCBPTR        		0xf1
1708

1709
#define	HNSCB_QOFF      		0xf4
1710

1711
#define	SNSCB_QOFF      		0xf6
1712

1713
#define	SDSCB_QOFF      		0xf8
1714

1715
#define	QOFF_CTLSTA     		0xfa
1716
#define		SCB_QSIZE       	0x07
1717
#define		SCB_QSIZE_256   	0x06
1718
#define		SCB_AVAIL       	0x40
1719
#define		SNSCB_ROLLOVER  	0x20
1720
#define		SDSCB_ROLLOVER  	0x10
1721

1722
#define	DFF_THRSH       		0xfb
1723
#define		WR_DFTHRSH      	0x70
1724
#define		WR_DFTHRSH_MAX  	0x70
1725
#define		WR_DFTHRSH_90   	0x60
1726
#define		WR_DFTHRSH_85   	0x50
1727
#define		WR_DFTHRSH_75   	0x40
1728
#define		WR_DFTHRSH_63   	0x30
1729
#define		WR_DFTHRSH_50   	0x20
1730
#define		WR_DFTHRSH_25   	0x10
1731
#define		RD_DFTHRSH_MAX  	0x07
1732
#define		RD_DFTHRSH      	0x07
1733
#define		RD_DFTHRSH_90   	0x06
1734
#define		RD_DFTHRSH_85   	0x05
1735
#define		RD_DFTHRSH_75   	0x04
1736
#define		RD_DFTHRSH_63   	0x03
1737
#define		RD_DFTHRSH_50   	0x02
1738
#define		RD_DFTHRSH_25   	0x01
1739
#define		RD_DFTHRSH_MIN  	0x00
1740
#define		WR_DFTHRSH_MIN  	0x00
1741

1742
#define	SG_CACHE_SHADOW 		0xfc
1743
#define		SG_ADDR_MASK    	0xf8
1744
#define		LAST_SEG        	0x02
1745
#define		LAST_SEG_DONE   	0x01
1746

1747
#define	SG_CACHE_PRE    		0xfc
1748

1749
#define	MAX_OFFSET_ULTRA2	0x7f
1750
#define	SCB_LIST_NULL	0xff
1751
#define	HOST_MSG	0xff
1752
#define	MAX_OFFSET	0x7f
1753
#define	BUS_32_BIT	0x02
1754
#define	CMD_GROUP_CODE_SHIFT	0x05
1755
#define	BUS_8_BIT	0x00
1756
#define	CCSGRAM_MAXSEGS	0x10
1757
#define	TARGET_DATA_IN	0x01
1758
#define	STATUS_QUEUE_FULL	0x28
1759
#define	STATUS_BUSY	0x08
1760
#define	MAX_OFFSET_8BIT	0x0f
1761
#define	BUS_16_BIT	0x01
1762
#define	TID_SHIFT	0x04
1763
#define	SCB_DOWNLOAD_SIZE_64	0x30
1764
#define	SCB_UPLOAD_SIZE	0x20
1765
#define	HOST_MAILBOX_SHIFT	0x04
1766
#define	MAX_OFFSET_16BIT	0x08
1767
#define	TARGET_CMD_CMPLT	0xfe
1768
#define	SG_SIZEOF	0x08
1769
#define	SCB_DOWNLOAD_SIZE	0x20
1770
#define	SEQ_MAILBOX_SHIFT	0x00
1771
#define	CCSGADDR_MAX	0x80
1772
#define	STACK_SIZE	0x04
1773

1774
/* Downloaded Constant Definitions */
1775
#define	SG_PREFETCH_ADDR_MASK	0x06
1776
#define	SG_PREFETCH_ALIGN_MASK	0x05
1777
#define	QOUTFIFO_OFFSET	0x00
1778
#define	SG_PREFETCH_CNT	0x04
1779
#define	INVERTED_CACHESIZE_MASK	0x03
1780
#define	CACHESIZE_MASK	0x02
1781
#define	QINFIFO_OFFSET	0x01
1782
#define	DOWNLOAD_CONST_COUNT	0x07
1783

1784
/* Exported Labels */
1785

1786
Product

Resources

Company
