CoCalc -- aq_hw

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/dev/aq/aq_hw_llh.h
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/*
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 * aQuantia Corporation Network Driver
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 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 *   (1) Redistributions of source code must retain the above
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 *   copyright notice, this list of conditions and the following
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 *   disclaimer.
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 *
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 *   (2) Redistributions in binary form must reproduce the above
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 *   copyright notice, this list of conditions and the following
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 *   disclaimer in the documentation and/or other materials provided
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 *   with the distribution.
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 *
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 *   (3)The name of the author may not be used to endorse or promote
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 *   products derived from this software without specific prior
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 *   written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/* File hw_atl_llh.h: Declarations of bitfield and register access functions for
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 * Atlantic registers.
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 */
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#ifndef HW_ATL_LLH_H
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#define HW_ATL_LLH_H
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#include "aq_common.h"
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struct aq_hw;
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/* global */
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void reg_glb_fw_image_id1_set(struct aq_hw* hw, uint32_t value);
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uint32_t reg_glb_fw_image_id1_get(struct aq_hw* hw);
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/* set global microprocessor semaphore */
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void reg_glb_cpu_sem_set(struct aq_hw *aq_hw, uint32_t sem_value,
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    uint32_t sem_index);
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/* get global microprocessor semaphore */
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uint32_t reg_glb_cpu_sem_get(struct aq_hw *aq_hw, uint32_t sem_index);
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/*
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 *  \brief Get Global Standard Control 1
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 *  \return GlobalStandardControl1
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 */
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uint32_t reg_glb_standard_ctl1_get(struct aq_hw* hw);
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/*
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 *  \brief Set Global Standard Control 1
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 */
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void reg_glb_standard_ctl1_set(struct aq_hw* hw, uint32_t glb_standard_ctl1);
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/*
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 *  \brief Set Global Control 2
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 */
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void reg_global_ctl2_set(struct aq_hw* hw, uint32_t global_ctl2);
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/*
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 *  \brief Get Global Control 2
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 *  \return GlobalControl2
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 */
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uint32_t reg_global_ctl2_get(struct aq_hw* hw);
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/*
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 *  \brief Set Global Daisy Chain Status 1
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 */
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void reg_glb_daisy_chain_status1_set(struct aq_hw* hw,
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    uint32_t glb_daisy_chain_status1);
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/*
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 *  \brief Get Global Daisy Chain Status 1
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 *  \return glb_daisy_chain_status1
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 */
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uint32_t reg_glb_daisy_chain_status1_get(struct aq_hw* hw);
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/*
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 *  \brief Set Global General Provisioning 9
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 */
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void reg_glb_general_provisioning9_set(struct aq_hw* hw, uint32_t value);
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/*
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 *  \brief Get Global General Provisioning 9
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 *  \return GlobalGeneralProvisioning9
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 */
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uint32_t reg_glb_general_provisioning9_get(struct aq_hw* hw);
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/*
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 *  \brief Set Global NVR Provisioning 2
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 */
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void reg_glb_nvr_provisioning2_set(struct aq_hw* hw, uint32_t value);
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/*
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 *  \brief Get Global NVR Provisioning 2
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 *  \return GlobalNvrProvisioning2
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 */
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uint32_t reg_glb_nvr_provisioning2_get(struct aq_hw* hw);
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/*
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 *  \brief Set Global NVR Interface 1
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 */
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void reg_glb_nvr_interface1_set(struct aq_hw* hw, uint32_t value);
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/*
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 *  \brief Get Global NVR Interface 1
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 *  \return GlobalNvrInterface1
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 */
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uint32_t reg_glb_nvr_interface1_get(struct aq_hw* hw);
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/* set global register reset disable */
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void glb_glb_reg_res_dis_set(struct aq_hw *aq_hw, uint32_t glb_reg_res_dis);
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/* set soft reset */
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void glb_soft_res_set(struct aq_hw *aq_hw, uint32_t soft_res);
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/* get soft reset */
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uint32_t glb_soft_res_get(struct aq_hw *aq_hw);
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/* stats */
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uint32_t rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw *aq_hw);
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/* get rx dma good octet counter lsw */
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uint32_t stats_rx_dma_good_octet_counterlsw_get(struct aq_hw *aq_hw);
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/* get rx dma good packet counter lsw */
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uint32_t stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw *aq_hw);
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/* get tx dma good octet counter lsw */
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uint32_t stats_tx_dma_good_octet_counterlsw_get(struct aq_hw *aq_hw);
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/* get tx dma good packet counter lsw */
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uint32_t stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw *aq_hw);
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/* get rx dma good octet counter msw */
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uint32_t stats_rx_dma_good_octet_countermsw_get(struct aq_hw *aq_hw);
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/* get rx dma good packet counter msw */
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uint32_t stats_rx_dma_good_pkt_countermsw_get(struct aq_hw *aq_hw);
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/* get tx dma good octet counter msw */
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uint32_t stats_tx_dma_good_octet_countermsw_get(struct aq_hw *aq_hw);
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/* get tx dma good packet counter msw */
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uint32_t stats_tx_dma_good_pkt_countermsw_get(struct aq_hw *aq_hw);
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/* get  rx lro coalesced packet count lsw */
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uint32_t stats_rx_lro_coalesced_pkt_count0_get(struct aq_hw *aq_hw);
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/* get msm rx errors counter register */
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uint32_t reg_mac_msm_rx_errs_cnt_get(struct aq_hw *aq_hw);
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/* get msm rx unicast frames counter register */
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uint32_t reg_mac_msm_rx_ucst_frm_cnt_get(struct aq_hw *aq_hw);
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/* get msm rx multicast frames counter register */
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uint32_t reg_mac_msm_rx_mcst_frm_cnt_get(struct aq_hw *aq_hw);
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/* get msm rx broadcast frames counter register */
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uint32_t reg_mac_msm_rx_bcst_frm_cnt_get(struct aq_hw *aq_hw);
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/* get msm rx broadcast octets counter register 1 */
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uint32_t reg_mac_msm_rx_bcst_octets_counter1get(struct aq_hw *aq_hw);
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/* get msm rx unicast octets counter register 0 */
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uint32_t reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw *aq_hw);
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/* get rx dma statistics counter 7 */
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uint32_t reg_rx_dma_stat_counter7get(struct aq_hw *aq_hw);
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/* get msm tx errors counter register */
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uint32_t reg_mac_msm_tx_errs_cnt_get(struct aq_hw *aq_hw);
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/* get msm tx unicast frames counter register */
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uint32_t reg_mac_msm_tx_ucst_frm_cnt_get(struct aq_hw *aq_hw);
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/* get msm tx multicast frames counter register */
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uint32_t reg_mac_msm_tx_mcst_frm_cnt_get(struct aq_hw *aq_hw);
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/* get msm tx broadcast frames counter register */
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uint32_t reg_mac_msm_tx_bcst_frm_cnt_get(struct aq_hw *aq_hw);
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/* get msm tx multicast octets counter register 1 */
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uint32_t reg_mac_msm_tx_mcst_octets_counter1get(struct aq_hw *aq_hw);
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/* get msm tx broadcast octets counter register 1 */
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uint32_t reg_mac_msm_tx_bcst_octets_counter1get(struct aq_hw *aq_hw);
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/* get msm tx unicast octets counter register 0 */
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uint32_t reg_mac_msm_tx_ucst_octets_counter0get(struct aq_hw *aq_hw);
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/* get global mif identification */
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uint32_t reg_glb_mif_id_get(struct aq_hw *aq_hw);
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/** \brief Set Tx Register Reset Disable
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 *   \param txRegisterResetDisable 1 = Disable the S/W reset to MAC-PHY registers, 0 = Enable the S/W reset to MAC-PHY registers
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 *   \note Default value: 0x1
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 *   \note PORT="pif_mpi_reg_reset_dsbl_i"
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 */
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void mpi_tx_reg_res_dis_set(struct aq_hw* hw, uint32_t mpi_tx_reg_res_dis);
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/** \brief Get Tx Register Reset Disable
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 *   \return 1 = Disable the S/W reset to MAC-PHY registers, 0 = Enable the S/W reset to MAC-PHY registers
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 *   \note Default value: 0x1
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 *   \note PORT="pif_mpi_reg_reset_dsbl_i"
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 */
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uint32_t mpi_tx_reg_res_dis_get(struct aq_hw* hw);
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/* interrupt */
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/* set interrupt auto mask lsw */
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void itr_irq_auto_masklsw_set(struct aq_hw *aq_hw, uint32_t irq_auto_masklsw);
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/* set interrupt mapping enable rx */
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void itr_irq_map_en_rx_set(struct aq_hw *aq_hw, uint32_t irq_map_en_rx,
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    uint32_t rx);
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/* set interrupt mapping enable tx */
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void itr_irq_map_en_tx_set(struct aq_hw *aq_hw, uint32_t irq_map_en_tx,
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    uint32_t tx);
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/* set interrupt mapping rx */
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void itr_irq_map_rx_set(struct aq_hw *aq_hw, uint32_t irq_map_rx, uint32_t rx);
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/* set interrupt mapping tx */
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void itr_irq_map_tx_set(struct aq_hw *aq_hw, uint32_t irq_map_tx, uint32_t tx);
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/* set interrupt mask clear lsw */
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void itr_irq_msk_clearlsw_set(struct aq_hw *aq_hw, uint32_t irq_msk_clearlsw);
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/* set interrupt mask set lsw */
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void itr_irq_msk_setlsw_set(struct aq_hw *aq_hw, uint32_t irq_msk_setlsw);
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/* set interrupt register reset disable */
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void itr_irq_reg_res_dis_set(struct aq_hw *aq_hw, uint32_t irq_reg_res_dis);
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/* set interrupt status clear lsw */
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void itr_irq_status_clearlsw_set(struct aq_hw *aq_hw,
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    uint32_t irq_status_clearlsw);
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/* get interrupt status lsw */
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uint32_t itr_irq_statuslsw_get(struct aq_hw *aq_hw);
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/* get reset interrupt */
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uint32_t itr_res_irq_get(struct aq_hw *aq_hw);
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/* set reset interrupt */
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void itr_res_irq_set(struct aq_hw *aq_hw, uint32_t res_irq);
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void itr_irq_mode_set(struct aq_hw *aq_hw, uint32_t irq_mode);
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/* Set Link Interrupt Mapping Enable */
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void itr_link_int_map_en_set(struct aq_hw *aq_hw, uint32_t link_int_en_map_en);
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/* Get Link Interrupt Mapping Enable */
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uint32_t itr_link_int_map_en_get(struct aq_hw *aq_hw);
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/* Set Link Interrupt Mapping */
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void itr_link_int_map_set(struct aq_hw *aq_hw, uint32_t link_int_map);
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/* Get Link Interrupt Mapping */
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uint32_t itr_link_int_map_get(struct aq_hw *aq_hw);
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/* Set MIF Interrupt Mapping Enable */
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void itr_mif_int_map_en_set(struct aq_hw *aq_hw, uint32_t mif_int_map_en,
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    uint32_t mif);
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/* Get MIF Interrupt Mapping Enable */
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uint32_t itr_mif_int_map_en_get(struct aq_hw *aq_hw, uint32_t mif);
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/* Set MIF Interrupt Mapping */
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void itr_mif_int_map_set(struct aq_hw *aq_hw, uint32_t mif_int_map,
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    uint32_t mif);
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/* Get MIF Interrupt Mapping */
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uint32_t itr_mif_int_map_get(struct aq_hw *aq_hw, uint32_t mif);
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void itr_irq_status_cor_en_set(struct aq_hw *aq_hw,
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    uint32_t irq_status_cor_enable);
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void itr_irq_auto_mask_clr_en_set(struct aq_hw *aq_hw, 
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    uint32_t irq_auto_mask_clr_en);
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/* rdm */
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/* set cpu id */
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void rdm_cpu_id_set(struct aq_hw *aq_hw, uint32_t cpuid, uint32_t dca);
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/* set rx dca enable */
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void rdm_rx_dca_en_set(struct aq_hw *aq_hw, uint32_t rx_dca_en);
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/* set rx dca mode */
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void rdm_rx_dca_mode_set(struct aq_hw *aq_hw, uint32_t rx_dca_mode);
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/* set rx descriptor data buffer size */
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void rdm_rx_desc_data_buff_size_set(struct aq_hw *aq_hw,
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    uint32_t rx_desc_data_buff_size, uint32_t descriptor);
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/* set rx descriptor dca enable */
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void rdm_rx_desc_dca_en_set(struct aq_hw *aq_hw, uint32_t rx_desc_dca_en,
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    uint32_t dca);
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/* set rx descriptor enable */
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void rdm_rx_desc_en_set(struct aq_hw *aq_hw, uint32_t rx_desc_en,
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    uint32_t descriptor);
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/* set rx descriptor header splitting */
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void rdm_rx_desc_head_splitting_set(struct aq_hw *aq_hw,
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    uint32_t rx_desc_head_splitting, uint32_t descriptor);
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/* get rx descriptor head pointer */
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uint32_t rdm_rx_desc_head_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor);
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/* set rx descriptor length */
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void rdm_rx_desc_len_set(struct aq_hw *aq_hw, uint32_t rx_desc_len,
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    uint32_t descriptor);
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/* set rx descriptor write-back interrupt enable */
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void rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw *aq_hw,
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    uint32_t rx_desc_wr_wb_irq_en);
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/* set rx header dca enable */
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void rdm_rx_head_dca_en_set(struct aq_hw *aq_hw, uint32_t rx_head_dca_en,
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    uint32_t dca);
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/* set rx payload dca enable */
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void rdm_rx_pld_dca_en_set(struct aq_hw *aq_hw, uint32_t rx_pld_dca_en,
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    uint32_t dca);
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/* set rx descriptor header buffer size */
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void rdm_rx_desc_head_buff_size_set(struct aq_hw *aq_hw,
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    uint32_t rx_desc_head_buff_size, uint32_t descriptor);
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/* set rx descriptor reset */
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void rdm_rx_desc_res_set(struct aq_hw *aq_hw, uint32_t rx_desc_res,
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    uint32_t descriptor);
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/* Set RDM Interrupt Moderation Enable */
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void rdm_rdm_intr_moder_en_set(struct aq_hw *aq_hw, uint32_t rdm_intr_moder_en);
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/* reg */
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/* set general interrupt mapping register */
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void reg_gen_irq_map_set(struct aq_hw *aq_hw, uint32_t gen_intr_map,
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    uint32_t regidx);
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/* get general interrupt status register */
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uint32_t reg_gen_irq_status_get(struct aq_hw *aq_hw);
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/* set interrupt global control register */
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void reg_irq_glb_ctl_set(struct aq_hw *aq_hw, uint32_t intr_glb_ctl);
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/* set interrupt throttle register */
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void reg_irq_thr_set(struct aq_hw *aq_hw, uint32_t intr_thr, uint32_t throttle);
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/* set rx dma descriptor base address lsw */
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void reg_rx_dma_desc_base_addresslswset(struct aq_hw *aq_hw,
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    uint32_t rx_dma_desc_base_addrlsw, uint32_t descriptor);
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/* set rx dma descriptor base address msw */
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void reg_rx_dma_desc_base_addressmswset(struct aq_hw *aq_hw,
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    uint32_t rx_dma_desc_base_addrmsw, uint32_t descriptor);
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/* get rx dma descriptor status register */
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uint32_t reg_rx_dma_desc_status_get(struct aq_hw *aq_hw, uint32_t descriptor);
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/* set rx dma descriptor tail pointer register */
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void reg_rx_dma_desc_tail_ptr_set(struct aq_hw *aq_hw,
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    uint32_t rx_dma_desc_tail_ptr, uint32_t descriptor);
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/* get rx dma descriptor tail pointer register */
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uint32_t reg_rx_dma_desc_tail_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor);
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/* set rx filter multicast filter mask register */
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void reg_rx_flr_mcst_flr_msk_set(struct aq_hw *aq_hw,
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    uint32_t rx_flr_mcst_flr_msk);
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/* set rx filter multicast filter register */
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void reg_rx_flr_mcst_flr_set(struct aq_hw *aq_hw, uint32_t rx_flr_mcst_flr,
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    uint32_t filter);
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/* set rx filter rss control register 1 */
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void reg_rx_flr_rss_control1set(struct aq_hw *aq_hw,
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    uint32_t rx_flr_rss_control1);
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/* Set RX Filter Control Register 2 */
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void reg_rx_flr_control2_set(struct aq_hw *aq_hw, uint32_t rx_flr_control2);
401

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/* Set RX Interrupt Moderation Control Register */
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void reg_rx_intr_moder_ctrl_set(struct aq_hw *aq_hw,
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    uint32_t rx_intr_moderation_ctl, uint32_t queue);
405

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/* set tx dma debug control */
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void reg_tx_dma_debug_ctl_set(struct aq_hw *aq_hw, uint32_t tx_dma_debug_ctl);
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/* set tx dma descriptor base address lsw */
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void reg_tx_dma_desc_base_addresslswset(struct aq_hw *aq_hw,
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    uint32_t tx_dma_desc_base_addrlsw, uint32_t descriptor);
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/* set tx dma descriptor base address msw */
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void reg_tx_dma_desc_base_addressmswset(struct aq_hw *aq_hw,
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    uint32_t tx_dma_desc_base_addrmsw, uint32_t descriptor);
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/* set tx dma descriptor tail pointer register */
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void reg_tx_dma_desc_tail_ptr_set(struct aq_hw *aq_hw,
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    uint32_t tx_dma_desc_tail_ptr, uint32_t descriptor);
420

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/* get tx dma descriptor tail pointer register */
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uint32_t reg_tx_dma_desc_tail_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor);
423

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/* Set TX Interrupt Moderation Control Register */
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void reg_tx_intr_moder_ctrl_set(struct aq_hw *aq_hw,
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    uint32_t tx_intr_moderation_ctl, uint32_t queue);
427

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/* get global microprocessor scratch pad */
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uint32_t reg_glb_cpu_scratch_scp_get(struct aq_hw *hw,
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    uint32_t glb_cpu_scratch_scp_idx);
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/* set global microprocessor scratch pad */
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void reg_glb_cpu_scratch_scp_set(struct aq_hw *aq_hw,
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    uint32_t glb_cpu_scratch_scp, uint32_t scratch_scp);
434

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/* get global microprocessor no reset scratch pad */
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uint32_t reg_glb_cpu_no_reset_scratchpad_get(struct aq_hw* hw, uint32_t index);
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/* set global microprocessor no reset scratch pad */
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void reg_glb_cpu_no_reset_scratchpad_set(struct aq_hw* aq_hw, uint32_t value,
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    uint32_t index);
440

441
/* rpb */
442

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/* set dma system loopback */
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void rpb_dma_sys_lbk_set(struct aq_hw *aq_hw, uint32_t dma_sys_lbk);
445

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/* set rx traffic class mode */
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void rpb_rpf_rx_traf_class_mode_set(struct aq_hw *aq_hw,
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    uint32_t rx_traf_class_mode);
449

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/* set rx buffer enable */
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void rpb_rx_buff_en_set(struct aq_hw *aq_hw, uint32_t rx_buff_en);
452

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/* set rx buffer high threshold (per tc) */
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void rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw *aq_hw,
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    uint32_t rx_buff_hi_threshold_per_tc, uint32_t buffer);
456

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/* set rx buffer low threshold (per tc) */
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void rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw *aq_hw,
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    uint32_t rx_buff_lo_threshold_per_tc, uint32_t buffer);
460

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/* set rx flow control mode */
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void rpb_rx_flow_ctl_mode_set(struct aq_hw *aq_hw, uint32_t rx_flow_ctl_mode);
463

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/* set rx packet buffer size (per tc) */
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void rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw *aq_hw,
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    uint32_t rx_pkt_buff_size_per_tc, uint32_t buffer);
467

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/* set rx xoff enable (per tc) */
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void rpb_rx_xoff_en_per_tc_set(struct aq_hw *aq_hw, uint32_t rx_xoff_en_per_tc,
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    uint32_t buffer);
471

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/* rpf */
473

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/* set l2 broadcast count threshold */
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void rpfl2broadcast_count_threshold_set(struct aq_hw *aq_hw,
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    uint32_t l2broadcast_count_threshold);
477

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/* set l2 broadcast enable */
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void rpfl2broadcast_en_set(struct aq_hw *aq_hw, uint32_t l2broadcast_en);
480

481
/* set l2 broadcast filter action */
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void rpfl2broadcast_flr_act_set(struct aq_hw *aq_hw,
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    uint32_t l2broadcast_flr_act);
484

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/* set l2 multicast filter enable */
486
void rpfl2multicast_flr_en_set(struct aq_hw *aq_hw, uint32_t l2multicast_flr_en,
487
    uint32_t filter);
488

489
/* set l2 promiscuous mode enable */
490
void rpfl2promiscuous_mode_en_set(struct aq_hw *aq_hw,
491
    uint32_t l2promiscuous_mode_en);
492

493
/* set l2 unicast filter action */
494
void rpfl2unicast_flr_act_set(struct aq_hw *aq_hw, uint32_t l2unicast_flr_act,
495
    uint32_t filter);
496

497
/* set l2 unicast filter enable */
498
void rpfl2_uc_flr_en_set(struct aq_hw *aq_hw, uint32_t l2unicast_flr_en,
499
    uint32_t filter);
500

501
/* set l2 unicast destination address lsw */
502
void rpfl2unicast_dest_addresslsw_set(struct aq_hw *aq_hw,
503
    uint32_t l2unicast_dest_addresslsw, uint32_t filter);
504

505
/* set l2 unicast destination address msw */
506
void rpfl2unicast_dest_addressmsw_set(struct aq_hw *aq_hw,
507
    uint32_t l2unicast_dest_addressmsw, uint32_t filter);
508

509
/* Set L2 Accept all Multicast packets */
510
void rpfl2_accept_all_mc_packets_set(struct aq_hw *aq_hw,
511
    uint32_t l2_accept_all_mc_packets);
512

513
/* set user-priority tc mapping */
514
void rpf_rpb_user_priority_tc_map_set(struct aq_hw *aq_hw,
515
    uint32_t user_priority_tc_map, uint32_t tc);
516

517
/* set rss key address */
518
void rpf_rss_key_addr_set(struct aq_hw *aq_hw, uint32_t rss_key_addr);
519

520
/* set rss key write data */
521
void rpf_rss_key_wr_data_set(struct aq_hw *aq_hw, uint32_t rss_key_wr_data);
522

523
/* get rss key read data */
524
uint32_t rpf_rss_key_rd_data_get(struct aq_hw *aq_hw);
525

526
/* get rss key write enable */
527
uint32_t rpf_rss_key_wr_en_get(struct aq_hw *aq_hw);
528

529
/* set rss key write enable */
530
void rpf_rss_key_wr_en_set(struct aq_hw *aq_hw, uint32_t rss_key_wr_en);
531

532
/* set rss redirection table address */
533
void rpf_rss_redir_tbl_addr_set(struct aq_hw *aq_hw,
534
    uint32_t rss_redir_tbl_addr);
535

536
/* set rss redirection table write data */
537
void rpf_rss_redir_tbl_wr_data_set(struct aq_hw *aq_hw,
538
    uint32_t rss_redir_tbl_wr_data);
539

540
/* get rss redirection write enable */
541
uint32_t rpf_rss_redir_wr_en_get(struct aq_hw *aq_hw);
542

543
/* set rss redirection write enable */
544
void rpf_rss_redir_wr_en_set(struct aq_hw *aq_hw, uint32_t rss_redir_wr_en);
545

546
/* set tpo to rpf system loopback */
547
void rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw *aq_hw,
548
    uint32_t tpo_to_rpf_sys_lbk);
549

550
/* set vlan inner ethertype */
551
void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw *aq_hw,
552
    uint32_t vlan_inner_etht);
553

554
/* set vlan outer ethertype */
555
void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw *aq_hw,
556
    uint32_t vlan_outer_etht);
557

558
/* set vlan promiscuous mode enable */
559
void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw *aq_hw,
560
    uint32_t vlan_prom_mode_en);
561

562
/* Set VLAN untagged action */
563
void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw *aq_hw,
564
    uint32_t vlan_untagged_act);
565

566
/* Set VLAN accept untagged packets */
567
void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw *aq_hw,
568
    uint32_t vlan_acc_untagged_packets);
569

570
/* Set VLAN filter enable */
571
void hw_atl_rpf_vlan_flr_en_set(struct aq_hw *aq_hw, uint32_t vlan_flr_en,
572
    uint32_t filter);
573

574
/* Set VLAN Filter Action */
575
void hw_atl_rpf_vlan_flr_act_set(struct aq_hw *aq_hw, uint32_t vlan_filter_act,
576
    uint32_t filter);
577

578
/* Set VLAN ID Filter */
579
void hw_atl_rpf_vlan_id_flr_set(struct aq_hw *aq_hw, uint32_t vlan_id_flr,
580
    uint32_t filter);
581

582
/* Set VLAN RX queue assignment enable */
583
void hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw *aq_hw, uint32_t vlan_rxq_en,
584
    uint32_t filter);
585

586
/* Set VLAN RX queue */
587
void hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw *aq_hw, uint32_t vlan_rxq,
588
    uint32_t filter);
589

590
/* set ethertype filter enable */
591
void hw_atl_rpf_etht_flr_en_set(struct aq_hw *aq_hw, uint32_t etht_flr_en,
592
    uint32_t filter);
593

594
/* set  ethertype user-priority enable */
595
void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw *aq_hw,
596
    uint32_t etht_user_priority_en, uint32_t filter);
597

598
/* set  ethertype rx queue enable */
599
void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw *aq_hw,
600
    uint32_t etht_rx_queue_en, uint32_t filter);
601

602
/* set ethertype rx queue */
603
void hw_atl_rpf_etht_rx_queue_set(struct aq_hw *aq_hw, uint32_t etht_rx_queue,
604
    uint32_t filter);
605

606
/* set ethertype user-priority */
607
void hw_atl_rpf_etht_user_priority_set(struct aq_hw *aq_hw,
608
    uint32_t etht_user_priority, uint32_t filter);
609

610
/* set ethertype management queue */
611
void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw *aq_hw, uint32_t etht_mgt_queue,
612
    uint32_t filter);
613

614
/* set ethertype filter action */
615
void hw_atl_rpf_etht_flr_act_set(struct aq_hw *aq_hw, uint32_t etht_flr_act,
616
    uint32_t filter);
617

618
/* set ethertype filter */
619
void hw_atl_rpf_etht_flr_set(struct aq_hw *aq_hw, uint32_t etht_flr,
620
    uint32_t filter);
621

622
/* set L3/L4 filter enable */
623
void hw_atl_rpf_l3_l4_enf_set(struct aq_hw *aq_hw, uint32_t val,
624
    uint32_t filter);
625

626
/* set L3 IPv6 enable */
627
void hw_atl_rpf_l3_v6_enf_set(struct aq_hw *aq_hw, uint32_t val,
628
    uint32_t filter);
629

630
/* set L3 source address enable */
631
void hw_atl_rpf_l3_saf_en_set(struct aq_hw *aq_hw, uint32_t val,
632
    uint32_t filter);
633

634
/* set L3 destination address enable */
635
void hw_atl_rpf_l3_daf_en_set(struct aq_hw *aq_hw, uint32_t val,
636
    uint32_t filter);
637

638
/* set L4 source port enable */
639
void hw_atl_rpf_l4_spf_en_set(struct aq_hw *aq_hw, uint32_t val,
640
    uint32_t filter);
641

642
/* set L4 destination port enable */
643
void hw_atl_rpf_l4_dpf_en_set(struct aq_hw *aq_hw, uint32_t val,
644
    uint32_t filter);
645

646
/* set L4 protocol enable */
647
void hw_atl_rpf_l4_protf_en_set(struct aq_hw *aq_hw, uint32_t val,
648
    uint32_t filter);
649

650
/* set L3 ARP filter enable */
651
void hw_atl_rpf_l3_arpf_en_set(struct aq_hw *aq_hw, uint32_t val,
652
    uint32_t filter);
653

654
/* set L3/L4 rx queue enable */
655
void hw_atl_rpf_l3_l4_rxqf_en_set(struct aq_hw *aq_hw, uint32_t val,
656
    uint32_t filter);
657

658
/* set L3/L4 management queue */
659
void hw_atl_rpf_l3_l4_mng_rxqf_set(struct aq_hw *aq_hw, uint32_t val,
660
    uint32_t filter);
661

662
/* set L3/L4 filter action */
663
void hw_atl_rpf_l3_l4_actf_set(struct aq_hw *aq_hw, uint32_t val,
664
    uint32_t filter);
665

666
/* set L3/L4 rx queue */
667
void hw_atl_rpf_l3_l4_rxqf_set(struct aq_hw *aq_hw, uint32_t val,
668
    uint32_t filter);
669

670
/* set L4 protocol value */
671
void hw_atl_rpf_l4_protf_set(struct aq_hw *aq_hw, uint32_t val,
672
    uint32_t filter);
673

674
/* set L4 source port */
675
void hw_atl_rpf_l4_spd_set(struct aq_hw *aq_hw, uint32_t val, uint32_t filter);
676

677
/* set L4 destination port */
678
void hw_atl_rpf_l4_dpd_set(struct aq_hw *aq_hw, uint32_t val, uint32_t filter);
679

680
/* set vlan inner ethertype */
681
void rpf_vlan_inner_etht_set(struct aq_hw *aq_hw, uint32_t vlan_inner_etht);
682

683
/* set vlan outer ethertype */
684
void rpf_vlan_outer_etht_set(struct aq_hw *aq_hw, uint32_t vlan_outer_etht);
685

686
/* set vlan promiscuous mode enable */
687
void rpf_vlan_prom_mode_en_set(struct aq_hw *aq_hw, uint32_t vlan_prom_mode_en);
688

689
/* Set VLAN untagged action */
690
void rpf_vlan_untagged_act_set(struct aq_hw *aq_hw, uint32_t vlan_untagged_act);
691

692
/* Set VLAN accept untagged packets */
693
void rpf_vlan_accept_untagged_packets_set(struct aq_hw *aq_hw,
694
    uint32_t vlan_accept_untagged_packets);
695

696
/* Set VLAN filter enable */
697
void rpf_vlan_flr_en_set(struct aq_hw *aq_hw, uint32_t vlan_flr_en,
698
    uint32_t filter);
699

700
/* Set VLAN Filter Action */
701
void rpf_vlan_flr_act_set(struct aq_hw *aq_hw, uint32_t vlan_filter_act,
702
    uint32_t filter);
703

704
/* Set VLAN ID Filter */
705
void rpf_vlan_id_flr_set(struct aq_hw *aq_hw, uint32_t vlan_id_flr,
706
    uint32_t filter);
707

708
/* set ethertype filter enable */
709
void rpf_etht_flr_en_set(struct aq_hw *aq_hw, uint32_t etht_flr_en,
710
    uint32_t filter);
711

712
/* set  ethertype user-priority enable */
713
void rpf_etht_user_priority_en_set(struct aq_hw *aq_hw,
714
    uint32_t etht_user_priority_en, uint32_t filter);
715

716
/* set  ethertype rx queue enable */
717
void rpf_etht_rx_queue_en_set(struct aq_hw *aq_hw, uint32_t etht_rx_queue_en,
718
    uint32_t filter);
719

720
/* set ethertype rx queue */
721
void rpf_etht_rx_queue_set(struct aq_hw *aq_hw, uint32_t etht_rx_queue,
722
    uint32_t filter);
723

724
/* set ethertype user-priority */
725
void rpf_etht_user_priority_set(struct aq_hw *aq_hw,
726
    uint32_t etht_user_priority, uint32_t filter);
727

728
/* set ethertype management queue */
729
void rpf_etht_mgt_queue_set(struct aq_hw *aq_hw, uint32_t etht_mgt_queue,
730
    uint32_t filter);
731

732
/* set ethertype filter action */
733
void rpf_etht_flr_act_set(struct aq_hw *aq_hw, uint32_t etht_flr_act,
734
    uint32_t filter);
735

736
/* set ethertype filter */
737
void rpf_etht_flr_set(struct aq_hw *aq_hw, uint32_t etht_flr, uint32_t filter);
738

739
/* set L3/L4 filter enable */
740
void hw_atl_rpf_l3_l4_enf_set(struct aq_hw *aq_hw, uint32_t val,
741
    uint32_t filter);
742

743
/* set L3 IPv6 enable */
744
void hw_atl_rpf_l3_v6_enf_set(struct aq_hw *aq_hw, uint32_t val,
745
    uint32_t filter);
746

747
/* set L3 source address enable */
748
void hw_atl_rpf_l3_saf_en_set(struct aq_hw *aq_hw, uint32_t val,
749
    uint32_t filter);
750

751
/* set L3 destination address enable */
752
void hw_atl_rpf_l3_daf_en_set(struct aq_hw *aq_hw, uint32_t val,
753
    uint32_t filter);
754

755
/* set L4 source port enable */
756
void hw_atl_rpf_l4_spf_en_set(struct aq_hw *aq_hw, uint32_t val,
757
    uint32_t filter);
758

759
/* set L4 destination port enable */
760
void hw_atl_rpf_l4_dpf_en_set(struct aq_hw *aq_hw, uint32_t val,
761
    uint32_t filter);
762

763
/* set L4 protocol enable */
764
void hw_atl_rpf_l4_protf_en_set(struct aq_hw *aq_hw, uint32_t val,
765
    uint32_t filter);
766

767
/* set L3 ARP filter enable */
768
void hw_atl_rpf_l3_arpf_en_set(struct aq_hw *aq_hw, uint32_t val,
769
    uint32_t filter);
770

771
/* set L3/L4 rx queue enable */
772
void hw_atl_rpf_l3_l4_rxqf_en_set(struct aq_hw *aq_hw, uint32_t val,
773
    uint32_t filter);
774

775
/* set L3/L4 management queue */
776
void hw_atl_rpf_l3_l4_mng_rxqf_set(struct aq_hw *aq_hw, uint32_t val,
777
    uint32_t filter);
778

779
/* set L3/L4 filter action */
780
void hw_atl_rpf_l3_l4_actf_set(struct aq_hw *aq_hw, uint32_t val,
781
    uint32_t filter);
782

783
/* set L3/L4 rx queue */
784
void hw_atl_rpf_l3_l4_rxqf_set(struct aq_hw *aq_hw, uint32_t val,
785
    uint32_t filter);
786

787
/* set L4 protocol value */
788
void hw_atl_rpf_l4_protf_set(struct aq_hw *aq_hw, uint32_t val,
789
    uint32_t filter);
790

791
/* set L4 source port */
792
void hw_atl_rpf_l4_spd_set(struct aq_hw *aq_hw, uint32_t val, uint32_t filter);
793

794
/* set L4 destination port */
795
void hw_atl_rpf_l4_dpd_set(struct aq_hw *aq_hw, uint32_t val, uint32_t filter);
796

797
/* rpo */
798

799
/* set ipv4 header checksum offload enable */
800
void rpo_ipv4header_crc_offload_en_set(struct aq_hw *aq_hw,
801
    uint32_t ipv4header_crc_offload_en);
802

803
/* set rx descriptor vlan stripping */
804
void rpo_rx_desc_vlan_stripping_set(struct aq_hw *aq_hw,
805
    uint32_t rx_desc_vlan_stripping, uint32_t descriptor);
806

807
/* set tcp/udp checksum offload enable */
808
void rpo_tcp_udp_crc_offload_en_set(struct aq_hw *aq_hw,
809
    uint32_t tcp_udp_crc_offload_en);
810

811
/* Set LRO Patch Optimization Enable. */
812
void rpo_lro_patch_optimization_en_set(struct aq_hw *aq_hw,
813
    uint32_t lro_patch_optimization_en);
814

815
/* Set Large Receive Offload Enable */
816
void rpo_lro_en_set(struct aq_hw *aq_hw, uint32_t lro_en);
817

818
/* Set LRO Q Sessions Limit */
819
void rpo_lro_qsessions_lim_set(struct aq_hw *aq_hw, uint32_t lro_qsessions_lim);
820

821
/* Set LRO Total Descriptor Limit */
822
void rpo_lro_total_desc_lim_set(struct aq_hw *aq_hw,
823
    uint32_t lro_total_desc_lim);
824

825
/* Set LRO Min Payload of First Packet */
826
void rpo_lro_min_pay_of_first_pkt_set(struct aq_hw *aq_hw,
827
    uint32_t lro_min_pld_of_first_pkt);
828

829
/* Set LRO Packet Limit */
830
void rpo_lro_pkt_lim_set(struct aq_hw *aq_hw, uint32_t lro_packet_lim);
831

832
/* Set LRO Max Number of Descriptors */
833
void rpo_lro_max_num_of_descriptors_set(struct aq_hw *aq_hw,
834
    uint32_t lro_max_desc_num, uint32_t lro);
835

836
/* Set LRO Time Base Divider */
837
void rpo_lro_time_base_divider_set(struct aq_hw *aq_hw,
838
    uint32_t lro_time_base_divider);
839
/*Set LRO Inactive Interval */
840
void rpo_lro_inactive_interval_set(struct aq_hw *aq_hw,
841
    uint32_t lro_inactive_interval);
842

843
/*Set LRO Max Coalescing Interval */
844
void rpo_lro_max_coalescing_interval_set(struct aq_hw *aq_hw,
845
    uint32_t lro_max_coalescing_interval);
846

847
/* rx */
848

849
/* set rx register reset disable */
850
void rx_rx_reg_res_dis_set(struct aq_hw *aq_hw, uint32_t rx_reg_res_dis);
851

852
/* tdm */
853

854
/* set cpu id */
855
void tdm_cpu_id_set(struct aq_hw *aq_hw, uint32_t cpuid, uint32_t dca);
856

857
/* set large send offload enable */
858
void tdm_large_send_offload_en_set(struct aq_hw *aq_hw,
859
    uint32_t large_send_offload_en);
860

861
/* set tx descriptor enable */
862
void tdm_tx_desc_en_set(struct aq_hw *aq_hw, uint32_t tx_desc_en,
863
    uint32_t descriptor);
864

865
/* set tx dca enable */
866
void tdm_tx_dca_en_set(struct aq_hw *aq_hw, uint32_t tx_dca_en);
867

868
/* set tx dca mode */
869
void tdm_tx_dca_mode_set(struct aq_hw *aq_hw, uint32_t tx_dca_mode);
870

871
/* set tx descriptor dca enable */
872
void tdm_tx_desc_dca_en_set(struct aq_hw *aq_hw, uint32_t tx_desc_dca_en,
873
    uint32_t dca);
874

875
/* get tx descriptor head pointer */
876
uint32_t tdm_tx_desc_head_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor);
877

878
/* set tx descriptor length */
879
void tdm_tx_desc_len_set(struct aq_hw *aq_hw, uint32_t tx_desc_len,
880
    uint32_t descriptor);
881

882
/* set tx descriptor write-back interrupt enable */
883
void tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw *aq_hw,
884
    uint32_t tx_desc_wr_wb_irq_en);
885

886
/* set tx descriptor write-back threshold */
887
void tdm_tx_desc_wr_wb_threshold_set(struct aq_hw *aq_hw,
888
    uint32_t tx_desc_wr_wb_threshold, uint32_t descriptor);
889

890
/* Set TDM Interrupt Moderation Enable */
891
void tdm_tdm_intr_moder_en_set(struct aq_hw *aq_hw,
892
    uint32_t tdm_irq_moderation_en);
893
/* thm */
894

895
/* set lso tcp flag of first packet */
896
void thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw *aq_hw,
897
    uint32_t lso_tcp_flag_of_first_pkt);
898

899
/* set lso tcp flag of last packet */
900
void thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw *aq_hw,
901
    uint32_t lso_tcp_flag_of_last_pkt);
902

903
/* set lso tcp flag of middle packet */
904
void thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw *aq_hw,
905
    uint32_t lso_tcp_flag_of_middle_pkt);
906

907
/* tpb */
908

909
/* set tx buffer enable */
910
void tpb_tx_buff_en_set(struct aq_hw *aq_hw, uint32_t tx_buff_en);
911

912
/* set tx tc mode */
913
void tpb_tx_tc_mode_set(struct aq_hw *aq_hw, uint32_t tc_mode);
914

915
/* set tx buffer high threshold (per tc) */
916
void tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw *aq_hw,
917
    uint32_t tx_buff_hi_threshold_per_tc, uint32_t buffer);
918

919
/* set tx buffer low threshold (per tc) */
920
void tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw *aq_hw,
921
    uint32_t tx_buff_lo_threshold_per_tc, uint32_t buffer);
922

923
/* set tx dma system loopback enable */
924
void tpb_tx_dma_sys_lbk_en_set(struct aq_hw *aq_hw, uint32_t tx_dma_sys_lbk_en);
925

926
/* set tx packet buffer size (per tc) */
927
void tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw *aq_hw,
928
    uint32_t tx_pkt_buff_size_per_tc, uint32_t buffer);
929

930
/* toggle rdm rx dma descriptor cache init */
931
void rdm_rx_dma_desc_cache_init_tgl(struct aq_hw *aq_hw);
932

933
/* set tx path pad insert enable */
934
void tpb_tx_path_scp_ins_en_set(struct aq_hw *aq_hw,
935
    uint32_t tx_path_scp_ins_en);
936

937
/* tpo */
938

939
/* set ipv4 header checksum offload enable */
940
void tpo_ipv4header_crc_offload_en_set(struct aq_hw *aq_hw,
941
    uint32_t ipv4header_crc_offload_en);
942

943
/* set tcp/udp checksum offload enable */
944
void tpo_tcp_udp_crc_offload_en_set(struct aq_hw *aq_hw,
945
    uint32_t tcp_udp_crc_offload_en);
946

947
/* set tx pkt system loopback enable */
948
void tpo_tx_pkt_sys_lbk_en_set(struct aq_hw *aq_hw, uint32_t tx_pkt_sys_lbk_en);
949

950
/* tps */
951

952
/* set tx packet scheduler data arbitration mode */
953
void tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw *aq_hw,
954
    uint32_t tx_pkt_shed_data_arb_mode);
955

956
/* set tx packet scheduler descriptor rate current time reset */
957
void tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw *aq_hw,
958
    uint32_t curr_time_res);
959

960
/* set tx packet scheduler descriptor rate limit */
961
void tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw *aq_hw,
962
    uint32_t tx_pkt_shed_desc_rate_lim);
963

964
/* set tx packet scheduler descriptor tc arbitration mode */
965
void tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw *aq_hw,
966
    uint32_t tx_pkt_shed_desc_tc_arb_mode);
967

968
/* set tx packet scheduler descriptor tc max credit */
969
void tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw *aq_hw,
970
    uint32_t tx_pkt_shed_desc_tc_max_credit, uint32_t tc);
971

972
/* set tx packet scheduler descriptor tc weight */
973
void tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw *aq_hw,
974
    uint32_t tx_pkt_shed_desc_tc_weight, uint32_t tc);
975

976
/* set tx packet scheduler descriptor vm arbitration mode */
977
void tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw *aq_hw,
978
    uint32_t tx_pkt_shed_desc_vm_arb_mode);
979

980
/* set tx packet scheduler tc data max credit */
981
void tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw *aq_hw,
982
    uint32_t tx_pkt_shed_tc_data_max_credit, uint32_t tc);
983

984
/* set tx packet scheduler tc data weight */
985
void tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw *aq_hw,
986
    uint32_t tx_pkt_shed_tc_data_weight, uint32_t tc);
987

988
/* tx */
989

990
/* set tx register reset disable */
991
void tx_tx_reg_res_dis_set(struct aq_hw *aq_hw, uint32_t tx_reg_res_dis);
992

993
/* msm */
994

995
/* get register access status */
996
uint32_t msm_reg_access_status_get(struct aq_hw *aq_hw);
997

998
/* set  register address for indirect address */
999
void msm_reg_addr_for_indirect_addr_set(struct aq_hw *aq_hw,
1000
    uint32_t reg_addr_for_indirect_addr);
1001

1002
/* set register read strobe */
1003
void msm_reg_rd_strobe_set(struct aq_hw *aq_hw, uint32_t reg_rd_strobe);
1004

1005
/* get  register read data */
1006
uint32_t msm_reg_rd_data_get(struct aq_hw *aq_hw);
1007

1008
/* set  register write data */
1009
void msm_reg_wr_data_set(struct aq_hw *aq_hw, uint32_t reg_wr_data);
1010

1011
/* set register write strobe */
1012
void msm_reg_wr_strobe_set(struct aq_hw *aq_hw, uint32_t reg_wr_strobe);
1013

1014
/* pci */
1015

1016
/* set pci register reset disable */
1017
void pci_pci_reg_res_dis_set(struct aq_hw *aq_hw, uint32_t pci_reg_res_dis);
1018

1019

1020
/*
1021
 *  \brief Set MIF Power Gating Enable Control
1022
 */
1023
void reg_mif_power_gating_enable_control_set(struct aq_hw* hw, uint32_t value);
1024
/*
1025
 *  \brief Get MIF Power Gating Enable Control
1026
 *  \return MifPowerGatingEnableControl
1027
 */
1028
uint32_t reg_mif_power_gating_enable_control_get(struct aq_hw* hw);
1029

1030
/* get mif up mailbox busy */
1031
uint32_t mif_mcp_up_mailbox_busy_get(struct aq_hw *aq_hw);
1032

1033
/* set mif up mailbox execute operation */
1034
void mif_mcp_up_mailbox_execute_operation_set(struct aq_hw* hw, uint32_t value);
1035

1036
/* get mif uP mailbox address */
1037
uint32_t mif_mcp_up_mailbox_addr_get(struct aq_hw *aq_hw);
1038
/* set mif uP mailbox address */
1039
void mif_mcp_up_mailbox_addr_set(struct aq_hw *hw, uint32_t value);
1040

1041
/* get mif uP mailbox data */
1042
uint32_t mif_mcp_up_mailbox_data_get(struct aq_hw *aq_hw);
1043

1044
/* clear ipv4 filter destination address */
1045
void hw_atl_rpfl3l4_ipv4_dest_addr_clear(struct aq_hw *aq_hw, uint8_t location);
1046

1047
/* clear ipv4 filter source address */
1048
void hw_atl_rpfl3l4_ipv4_src_addr_clear(struct aq_hw *aq_hw, uint8_t location);
1049

1050
/* clear command for filter l3-l4 */
1051
void hw_atl_rpfl3l4_cmd_clear(struct aq_hw *aq_hw, uint8_t location);
1052

1053
/* clear ipv6 filter destination address */
1054
void hw_atl_rpfl3l4_ipv6_dest_addr_clear(struct aq_hw *aq_hw, uint8_t location);
1055

1056
/* clear ipv6 filter source address */
1057
void hw_atl_rpfl3l4_ipv6_src_addr_clear(struct aq_hw *aq_hw, uint8_t location);
1058

1059
/* set ipv4 filter destination address */
1060
void hw_atl_rpfl3l4_ipv4_dest_addr_set(struct aq_hw *aq_hw, uint8_t location,
1061
    uint32_t ipv4_dest);
1062

1063
/* set ipv4 filter source address */
1064
void hw_atl_rpfl3l4_ipv4_src_addr_set(struct aq_hw *aq_hw, uint8_t location,
1065
    uint32_t ipv4_src);
1066

1067
/* set command for filter l3-l4 */
1068
void hw_atl_rpfl3l4_cmd_set(struct aq_hw *aq_hw, uint8_t location,
1069
    uint32_t cmd);
1070

1071
/* set ipv6 filter source address */
1072
void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw *aq_hw, uint8_t location,
1073
    uint32_t *ipv6_src);
1074

1075
/* set ipv6 filter destination address */
1076
void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw *aq_hw, uint8_t location,
1077
    uint32_t *ipv6_dest);
1078

1079
/* set vlan inner ethertype */
1080
void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw *aq_hw,
1081
    uint32_t vlan_inner_etht);
1082

1083
/* set vlan outer ethertype */
1084
void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw *aq_hw,
1085
    uint32_t vlan_outer_etht);
1086

1087
/* set vlan promiscuous mode enable */
1088
void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw *aq_hw,
1089
    uint32_t vlan_prom_mode_en);
1090

1091
/* Set VLAN untagged action */
1092
void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw *aq_hw,
1093
    uint32_t vlan_untagged_act);
1094

1095
/* Set VLAN accept untagged packets */
1096
void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw *aq_hw,
1097
    uint32_t vlan_acc_untagged_packets);
1098

1099
/* Set VLAN filter enable */
1100
void hw_atl_rpf_vlan_flr_en_set(struct aq_hw *aq_hw, uint32_t vlan_flr_en,
1101
    uint32_t filter);
1102

1103
/* Set VLAN Filter Action */
1104
void hw_atl_rpf_vlan_flr_act_set(struct aq_hw *aq_hw, uint32_t vlan_filter_act,
1105
    uint32_t filter);
1106

1107
/* Set VLAN ID Filter */
1108
void hw_atl_rpf_vlan_id_flr_set(struct aq_hw *aq_hw, uint32_t vlan_id_flr,
1109
    uint32_t filter);
1110

1111
/* Set VLAN RX queue assignment enable */
1112
void hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw *aq_hw, uint32_t vlan_rxq_en,
1113
    uint32_t filter);
1114

1115
/* Set VLAN RX queue */
1116
void hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw *aq_hw, uint32_t vlan_rxq,
1117
    uint32_t filter);
1118

1119
/* set ethertype filter enable */
1120
void hw_atl_rpf_etht_flr_en_set(struct aq_hw *aq_hw, uint32_t etht_flr_en,
1121
    uint32_t filter);
1122

1123
/* set  ethertype user-priority enable */
1124
void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw *aq_hw,
1125
    uint32_t etht_user_priority_en, uint32_t filter);
1126

1127
/* set  ethertype rx queue enable */
1128
void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw *aq_hw,
1129
    uint32_t etht_rx_queue_en, uint32_t filter);
1130

1131
/* set ethertype rx queue */
1132
void hw_atl_rpf_etht_rx_queue_set(struct aq_hw *aq_hw, uint32_t etht_rx_queue,
1133
    uint32_t filter);
1134

1135
/* set ethertype user-priority */
1136
void hw_atl_rpf_etht_user_priority_set(struct aq_hw *aq_hw,
1137
    uint32_t etht_user_priority, uint32_t filter);
1138

1139
/* set ethertype management queue */
1140
void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw *aq_hw, uint32_t etht_mgt_queue,
1141
    uint32_t filter);
1142

1143
/* set ethertype filter action */
1144
void hw_atl_rpf_etht_flr_act_set(struct aq_hw *aq_hw, uint32_t etht_flr_act,
1145
    uint32_t filter);
1146

1147
/* set ethertype filter */
1148
void hw_atl_rpf_etht_flr_set(struct aq_hw *aq_hw, uint32_t etht_flr,
1149
    uint32_t filter);
1150

1151
/* set L3/L4 filter enable */
1152
void hw_atl_rpf_l3_l4_enf_set(struct aq_hw *aq_hw, uint32_t val,
1153
    uint32_t filter);
1154

1155
/* set L3 IPv6 enable */
1156
void hw_atl_rpf_l3_v6_enf_set(struct aq_hw *aq_hw, uint32_t val,
1157
    uint32_t filter);
1158

1159
/* set L3 source address enable */
1160
void hw_atl_rpf_l3_saf_en_set(struct aq_hw *aq_hw, uint32_t val,
1161
    uint32_t filter);
1162

1163
/* set L3 destination address enable */
1164
void hw_atl_rpf_l3_daf_en_set(struct aq_hw *aq_hw, uint32_t val,
1165
    uint32_t filter);
1166

1167
/* set L4 source port enable */
1168
void hw_atl_rpf_l4_spf_en_set(struct aq_hw *aq_hw, uint32_t val,
1169
    uint32_t filter);
1170

1171
/* set L4 destination port enable */
1172
void hw_atl_rpf_l4_dpf_en_set(struct aq_hw *aq_hw, uint32_t val,
1173
    uint32_t filter);
1174

1175
/* set L4 protocol enable */
1176
void hw_atl_rpf_l4_protf_en_set(struct aq_hw *aq_hw, uint32_t val,
1177
    uint32_t filter);
1178

1179
/* set L3 ARP filter enable */
1180
void hw_atl_rpf_l3_arpf_en_set(struct aq_hw *aq_hw, uint32_t val,
1181
    uint32_t filter);
1182

1183
/* set L3/L4 rx queue enable */
1184
void hw_atl_rpf_l3_l4_rxqf_en_set(struct aq_hw *aq_hw, uint32_t val,
1185
    uint32_t filter);
1186

1187
/* set L3/L4 management queue */
1188
void hw_atl_rpf_l3_l4_mng_rxqf_set(struct aq_hw *aq_hw, uint32_t val,
1189
    uint32_t filter);
1190

1191
/* set L3/L4 filter action */
1192
void hw_atl_rpf_l3_l4_actf_set(struct aq_hw *aq_hw, uint32_t val,
1193
    uint32_t filter);
1194

1195
/* set L3/L4 rx queue */
1196
void hw_atl_rpf_l3_l4_rxqf_set(struct aq_hw *aq_hw, uint32_t val,
1197
    uint32_t filter);
1198

1199
/* set L4 protocol value */
1200
void hw_atl_rpf_l4_protf_set(struct aq_hw *aq_hw, uint32_t val,
1201
    uint32_t filter);
1202

1203
/* set L4 source port */
1204
void hw_atl_rpf_l4_spd_set(struct aq_hw *aq_hw, uint32_t val, uint32_t filter);
1205

1206
/* set L4 destination port */
1207
void hw_atl_rpf_l4_dpd_set(struct aq_hw *aq_hw, uint32_t val, uint32_t filter);
1208

1209
#endif /* HW_ATL_LLH_H */
1210

1211
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