CoCalc -- aq_hw_llh

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/dev/aq/aq_hw_llh_internal.h
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/*
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 * aQuantia Corporation Network Driver
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 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 *   (1) Redistributions of source code must retain the above
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 *   copyright notice, this list of conditions and the following
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 *   disclaimer.
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 *
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 *   (2) Redistributions in binary form must reproduce the above
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 *   copyright notice, this list of conditions and the following
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 *   disclaimer in the documentation and/or other materials provided
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 *   with the distribution.
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 *
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 *   (3)The name of the author may not be used to endorse or promote
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 *   products derived from this software without specific prior
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 *   written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/* File aq_hw_llh_internal.h: Preprocessor definitions
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 * for Atlantic registers.
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 */
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#ifndef HW_ATL_LLH_INTERNAL_H
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#define HW_ATL_LLH_INTERNAL_H
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/* global microprocessor semaphore  definitions
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 * base address: 0x000003a0
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 * parameter: semaphore {s} | stride size 0x4 | range [0, 15]
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 */
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#define glb_cpu_sem_adr(semaphore)  (0x000003a0u + (semaphore) * 0x4)
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/* register address for bitfield rx dma good octet counter lsw [1f:0] */
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#define stats_rx_dma_good_octet_counterlsw__adr 0x00006808
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/* register address for bitfield rx dma good packet counter lsw [1f:0] */
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#define stats_rx_dma_good_pkt_counterlsw__adr 0x00006800
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/* register address for bitfield tx dma good octet counter lsw [1f:0] */
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#define stats_tx_dma_good_octet_counterlsw__adr 0x00008808
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/* register address for bitfield tx dma good packet counter lsw [1f:0] */
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#define stats_tx_dma_good_pkt_counterlsw__adr 0x00008800
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/* register address for bitfield rx dma good octet counter msw [3f:20] */
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#define stats_rx_dma_good_octet_countermsw__adr 0x0000680c
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/* register address for bitfield rx dma good packet counter msw [3f:20] */
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#define stats_rx_dma_good_pkt_countermsw__adr 0x00006804
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/* register address for bitfield tx dma good octet counter msw [3f:20] */
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#define stats_tx_dma_good_octet_countermsw__adr 0x0000880c
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/* register address for bitfield tx dma good packet counter msw [3f:20] */
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#define stats_tx_dma_good_pkt_countermsw__adr 0x00008804
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/* register address for bitfield rx lro coalesced packet count lsw [1f:0] */
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#define stats_rx_lo_coalesced_pkt_count0__addr 0x00006820u
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/* preprocessor definitions for msm rx errors counter register */
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#define mac_msm_rx_errs_cnt_adr 0x00000120u
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/* preprocessor definitions for msm rx unicast frames counter register */
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#define mac_msm_rx_ucst_frm_cnt_adr 0x000000e0u
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/* preprocessor definitions for msm rx multicast frames counter register */
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#define mac_msm_rx_mcst_frm_cnt_adr 0x000000e8u
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/* preprocessor definitions for msm rx broadcast frames counter register */
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#define mac_msm_rx_bcst_frm_cnt_adr 0x000000f0u
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/* preprocessor definitions for msm rx broadcast octets counter register 1 */
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#define mac_msm_rx_bcst_octets_counter1_adr 0x000001b0u
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/* preprocessor definitions for msm rx broadcast octets counter register 2 */
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#define mac_msm_rx_bcst_octets_counter2_adr 0x000001b4u
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/* preprocessor definitions for msm rx unicast octets counter register 0 */
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#define mac_msm_rx_ucst_octets_counter0_adr 0x000001b8u
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/* preprocessor definitions for rx dma statistics counter 7 */
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#define rx_dma_stat_counter7_adr 0x00006818u
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/* preprocessor definitions for msm tx unicast frames counter register */
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#define mac_msm_tx_ucst_frm_cnt_adr 0x00000108u
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/* preprocessor definitions for msm tx multicast frames counter register */
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#define mac_msm_tx_mcst_frm_cnt_adr 0x00000110u
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/*!  @name Global FW Image Identification 1 Definitions
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*
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*   Preprocessor definitions for Global FW Image Identification 1
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*   Address: 0x00000018
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@{*/
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#define glb_fw_image_id1_adr 0x00000018u
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/*@}*/
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/* preprocessor definitions for global mif identification */
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#define glb_mif_id_adr 0x0000001cu
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/* register address for bitfield iamr_lsw[1f:0] */
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#define itr_iamrlsw_adr 0x00002090
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/* register address for bitfield rx dma drop packet counter [1f:0] */
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#define rpb_rx_dma_drop_pkt_cnt_adr 0x00006818
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/* register address for bitfield imcr_lsw[1f:0] */
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#define itr_imcrlsw_adr 0x00002070
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/* register address for bitfield imsr_lsw[1f:0] */
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#define itr_imsrlsw_adr 0x00002060
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/* register address for bitfield itr_reg_res_dsbl */
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#define itr_reg_res_dsbl_adr 0x00002300
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/* bitmask for bitfield itr_reg_res_dsbl */
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#define itr_reg_res_dsbl_msk 0x20000000
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/* lower bit position of bitfield itr_reg_res_dsbl */
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#define itr_reg_res_dsbl_shift 29
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/* register address for bitfield iscr_lsw[1f:0] */
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#define itr_iscrlsw_adr 0x00002050
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/* register address for bitfield isr_lsw[1f:0] */
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#define itr_isrlsw_adr 0x00002000
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/* register address for bitfield itr_reset */
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#define itr_res_adr 0x00002300
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/* bitmask for bitfield itr_reset */
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#define itr_res_msk 0x80000000
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/* lower bit position of bitfield itr_reset */
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#define itr_res_shift 31
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/* register address for bitfield dca{d}_cpuid[7:0] */
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#define rdm_dcadcpuid_adr(dca) (0x00006100 + (dca) * 0x4)
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/* bitmask for bitfield dca{d}_cpuid[7:0] */
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#define rdm_dcadcpuid_msk 0x000000ff
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/* lower bit position of bitfield dca{d}_cpuid[7:0] */
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#define rdm_dcadcpuid_shift 0
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/* register address for bitfield dca_en */
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#define rdm_dca_en_adr 0x00006180
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/*!  @name MIF Power Gating Enable Control Definitions
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*   Preprocessor definitions for MIF Power Gating Enable Control
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*   Address: 0x000032A8
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@{*/
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#define mif_power_gating_enable_control_adr 0x000032A8u
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/*@}*/
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/*!  @name Global General Provisioning 9 Definitions
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*
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*   Preprocessor definitions for Global General Provisioning 9
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*   Address: 0x00000520
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@{*/
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#define glb_general_provisioning9_adr 0x00000520u
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/*@}*/
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/*!  @name Global NVR Provisioning 2 Definitions
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*
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*   Preprocessor definitions for Global NVR Provisioning 2
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*   Address: 0x00000534
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@{*/
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#define glb_nvr_provisioning2_adr 0x00000534u
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/*@}*/
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/*!  @name Global NVR Interface 1 Definitions
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*
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*   Preprocessor definitions for Global NVR Interface 1
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*   Address: 0x00000100
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@{*/
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#define glb_nvr_interface1_adr 0x00000100u
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/*@}*/
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/* rx dca_en bitfield definitions
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 * preprocessor definitions for the bitfield "dca_en".
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 * port="pif_rdm_dca_en_i"
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 */
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/* register address for bitfield dca_en */
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#define rdm_dca_en_adr 0x00006180
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/* bitmask for bitfield dca_en */
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#define rdm_dca_en_msk 0x80000000
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/* inverted bitmask for bitfield dca_en */
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#define rdm_dca_en_mskn 0x7fffffff
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/* lower bit position of bitfield dca_en */
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#define rdm_dca_en_shift 31
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/* width of bitfield dca_en */
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#define rdm_dca_en_width 1
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/* default value of bitfield dca_en */
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#define rdm_dca_en_default 0x1
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/*! @name MAC_PHY MPI register reset disable Bitfield Definitions
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*   Preprocessor definitions for the bitfield "MPI register reset disable".
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*   PORT="pif_mpi_reg_reset_dsbl_i"
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@{ */
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/*! \brief Register address for bitfield MPI register reset disable */
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#define mpi_tx_reg_res_dis_adr 0x00004000
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/*! \brief Bitmask for bitfield MPI register reset disable */
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#define mpi_tx_reg_res_dis_msk 0x20000000
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/*! \brief Inverted bitmask for bitfield MPI register reset disable */
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#define mpi_tx_reg_res_dis_mskn 0xDFFFFFFF
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/*! \brief Lower bit position of bitfield MPI register reset disable */
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#define mpi_tx_reg_res_dis_shift 29
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/*! \brief Width of bitfield MPI register reset disable */
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#define mpi_tx_reg_res_dis_width 1
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/*! \brief Default value of bitfield MPI register reset disable */
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#define mpi_tx_reg_res_dis_default 0x1
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/*@}*/
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/* rx dca_mode[3:0] bitfield definitions
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 * preprocessor definitions for the bitfield "dca_mode[3:0]".
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 * port="pif_rdm_dca_mode_i[3:0]"
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 */
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/* register address for bitfield dca_mode[3:0] */
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#define rdm_dca_mode_adr 0x00006180
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/* bitmask for bitfield dca_mode[3:0] */
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#define rdm_dca_mode_msk 0x0000000f
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/* inverted bitmask for bitfield dca_mode[3:0] */
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#define rdm_dca_mode_mskn 0xfffffff0
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/* lower bit position of bitfield dca_mode[3:0] */
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#define rdm_dca_mode_shift 0
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/* width of bitfield dca_mode[3:0] */
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#define rdm_dca_mode_width 4
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/* default value of bitfield dca_mode[3:0] */
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#define rdm_dca_mode_default 0x0
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/* rx desc{d}_data_size[4:0] bitfield definitions
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 * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]".
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 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
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 * port="pif_rdm_desc0_data_size_i[4:0]"
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 */
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/* register address for bitfield desc{d}_data_size[4:0] */
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#define rdm_descddata_size_adr(descriptor) (0x00005b18 + (descriptor) * 0x20)
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/* bitmask for bitfield desc{d}_data_size[4:0] */
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#define rdm_descddata_size_msk 0x0000001f
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/* inverted bitmask for bitfield desc{d}_data_size[4:0] */
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#define rdm_descddata_size_mskn 0xffffffe0
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/* lower bit position of bitfield desc{d}_data_size[4:0] */
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#define rdm_descddata_size_shift 0
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/* width of bitfield desc{d}_data_size[4:0] */
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#define rdm_descddata_size_width 5
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/* default value of bitfield desc{d}_data_size[4:0] */
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#define rdm_descddata_size_default 0x0
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/* rx dca{d}_desc_en bitfield definitions
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 * preprocessor definitions for the bitfield "dca{d}_desc_en".
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 * parameter: dca {d} | stride size 0x4 | range [0, 31]
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 * port="pif_rdm_dca_desc_en_i[0]"
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 */
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/* register address for bitfield dca{d}_desc_en */
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#define rdm_dcaddesc_en_adr(dca) (0x00006100 + (dca) * 0x4)
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/* bitmask for bitfield dca{d}_desc_en */
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#define rdm_dcaddesc_en_msk 0x80000000
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/* inverted bitmask for bitfield dca{d}_desc_en */
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#define rdm_dcaddesc_en_mskn 0x7fffffff
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/* lower bit position of bitfield dca{d}_desc_en */
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#define rdm_dcaddesc_en_shift 31
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/* width of bitfield dca{d}_desc_en */
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#define rdm_dcaddesc_en_width 1
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/* default value of bitfield dca{d}_desc_en */
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#define rdm_dcaddesc_en_default 0x0
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/* rx desc{d}_en bitfield definitions
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 * preprocessor definitions for the bitfield "desc{d}_en".
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 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
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 * port="pif_rdm_desc_en_i[0]"
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 */
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/* register address for bitfield desc{d}_en */
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#define rdm_descden_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
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/* bitmask for bitfield desc{d}_en */
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#define rdm_descden_msk 0x80000000
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/* inverted bitmask for bitfield desc{d}_en */
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#define rdm_descden_mskn 0x7fffffff
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/* lower bit position of bitfield desc{d}_en */
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#define rdm_descden_shift 31
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/* width of bitfield desc{d}_en */
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#define rdm_descden_width 1
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/* default value of bitfield desc{d}_en */
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#define rdm_descden_default 0x0
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/* rx desc{d}_hdr_size[4:0] bitfield definitions
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 * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]".
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 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
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 * port="pif_rdm_desc0_hdr_size_i[4:0]"
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 */
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/* register address for bitfield desc{d}_hdr_size[4:0] */
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#define rdm_descdhdr_size_adr(descriptor) (0x00005b18 + (descriptor) * 0x20)
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/* bitmask for bitfield desc{d}_hdr_size[4:0] */
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#define rdm_descdhdr_size_msk 0x00001f00
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/* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */
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#define rdm_descdhdr_size_mskn 0xffffe0ff
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/* lower bit position of bitfield desc{d}_hdr_size[4:0] */
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#define rdm_descdhdr_size_shift 8
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/* width of bitfield desc{d}_hdr_size[4:0] */
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#define rdm_descdhdr_size_width 5
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/* default value of bitfield desc{d}_hdr_size[4:0] */
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#define rdm_descdhdr_size_default 0x0
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/* rx desc{d}_hdr_split bitfield definitions
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 * preprocessor definitions for the bitfield "desc{d}_hdr_split".
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 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
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 * port="pif_rdm_desc_hdr_split_i[0]"
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 */
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/* register address for bitfield desc{d}_hdr_split */
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#define rdm_descdhdr_split_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
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/* bitmask for bitfield desc{d}_hdr_split */
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#define rdm_descdhdr_split_msk 0x10000000
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/* inverted bitmask for bitfield desc{d}_hdr_split */
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#define rdm_descdhdr_split_mskn 0xefffffff
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/* lower bit position of bitfield desc{d}_hdr_split */
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#define rdm_descdhdr_split_shift 28
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/* width of bitfield desc{d}_hdr_split */
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#define rdm_descdhdr_split_width 1
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/* default value of bitfield desc{d}_hdr_split */
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#define rdm_descdhdr_split_default 0x0
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/* rx desc{d}_hd[c:0] bitfield definitions
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 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]".
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 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
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 * port="rdm_pif_desc0_hd_o[12:0]"
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 */
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/* register address for bitfield desc{d}_hd[c:0] */
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#define rdm_descdhd_adr(descriptor) (0x00005b0c + (descriptor) * 0x20)
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/* bitmask for bitfield desc{d}_hd[c:0] */
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#define rdm_descdhd_msk 0x00001fff
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/* inverted bitmask for bitfield desc{d}_hd[c:0] */
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#define rdm_descdhd_mskn 0xffffe000
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/* lower bit position of bitfield desc{d}_hd[c:0] */
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#define rdm_descdhd_shift 0
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/* width of bitfield desc{d}_hd[c:0] */
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#define rdm_descdhd_width 13
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/* rx desc{d}_len[9:0] bitfield definitions
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 * preprocessor definitions for the bitfield "desc{d}_len[9:0]".
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 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
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 * port="pif_rdm_desc0_len_i[9:0]"
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 */
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/* register address for bitfield desc{d}_len[9:0] */
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#define rdm_descdlen_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
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/* bitmask for bitfield desc{d}_len[9:0] */
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#define rdm_descdlen_msk 0x00001ff8
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/* inverted bitmask for bitfield desc{d}_len[9:0] */
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#define rdm_descdlen_mskn 0xffffe007
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/* lower bit position of bitfield desc{d}_len[9:0] */
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#define rdm_descdlen_shift 3
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/* width of bitfield desc{d}_len[9:0] */
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#define rdm_descdlen_width 10
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/* default value of bitfield desc{d}_len[9:0] */
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#define rdm_descdlen_default 0x0
360

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/* rx desc{d}_reset bitfield definitions
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 * preprocessor definitions for the bitfield "desc{d}_reset".
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 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
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 * port="pif_rdm_q_pf_res_i[0]"
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 */
366

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/* register address for bitfield desc{d}_reset */
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#define rdm_descdreset_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
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/* bitmask for bitfield desc{d}_reset */
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#define rdm_descdreset_msk 0x02000000
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/* inverted bitmask for bitfield desc{d}_reset */
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#define rdm_descdreset_mskn 0xfdffffff
373
/* lower bit position of bitfield desc{d}_reset */
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#define rdm_descdreset_shift 25
375
/* width of bitfield desc{d}_reset */
376
#define rdm_descdreset_width 1
377
/* default value of bitfield desc{d}_reset */
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#define rdm_descdreset_default 0x0
379

380
/* rdm_desc_init_i bitfield definitions
381
 * preprocessor definitions for the bitfield rdm_desc_init_i.
382
 * port="pif_rdm_desc_init_i"
383
 */
384

385
/* register address for bitfield rdm_desc_init_i */
386
#define rdm_rx_dma_desc_cache_init_adr 0x00005a00
387
/* bitmask for bitfield rdm_desc_init_i */
388
#define rdm_rx_dma_desc_cache_init_msk 0x00000001
389
/* inverted bitmask for bitfield rdm_desc_init_i */
390
#define rdm_rx_dma_desc_cache_init_mskn 0xfffffffe
391
/* lower bit position of bitfield  rdm_desc_init_i */
392
#define rdm_rx_dma_desc_cache_init_shift 0
393
/* width of bitfield rdm_desc_init_i */
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#define rdm_rx_dma_desc_cache_init_width 1
395
/* default value of bitfield rdm_desc_init_i */
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#define rdm_rx_dma_desc_cache_init_defaulT 0x0
397

398
/* rx int_desc_wrb_en bitfield definitions
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 * preprocessor definitions for the bitfield "int_desc_wrb_en".
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 * port="pif_rdm_int_desc_wrb_en_i"
401
 */
402

403
/* register address for bitfield int_desc_wrb_en */
404
#define rdm_int_desc_wrb_en_adr 0x00005a30
405
/* bitmask for bitfield int_desc_wrb_en */
406
#define rdm_int_desc_wrb_en_msk 0x00000004
407
/* inverted bitmask for bitfield int_desc_wrb_en */
408
#define rdm_int_desc_wrb_en_mskn 0xfffffffb
409
/* lower bit position of bitfield int_desc_wrb_en */
410
#define rdm_int_desc_wrb_en_shift 2
411
/* width of bitfield int_desc_wrb_en */
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#define rdm_int_desc_wrb_en_width 1
413
/* default value of bitfield int_desc_wrb_en */
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#define rdm_int_desc_wrb_en_default 0x0
415

416
/* rx dca{d}_hdr_en bitfield definitions
417
 * preprocessor definitions for the bitfield "dca{d}_hdr_en".
418
 * parameter: dca {d} | stride size 0x4 | range [0, 31]
419
 * port="pif_rdm_dca_hdr_en_i[0]"
420
 */
421

422
/* register address for bitfield dca{d}_hdr_en */
423
#define rdm_dcadhdr_en_adr(dca) (0x00006100 + (dca) * 0x4)
424
/* bitmask for bitfield dca{d}_hdr_en */
425
#define rdm_dcadhdr_en_msk 0x40000000
426
/* inverted bitmask for bitfield dca{d}_hdr_en */
427
#define rdm_dcadhdr_en_mskn 0xbfffffff
428
/* lower bit position of bitfield dca{d}_hdr_en */
429
#define rdm_dcadhdr_en_shift 30
430
/* width of bitfield dca{d}_hdr_en */
431
#define rdm_dcadhdr_en_width 1
432
/* default value of bitfield dca{d}_hdr_en */
433
#define rdm_dcadhdr_en_default 0x0
434

435
/* rx dca{d}_pay_en bitfield definitions
436
 * preprocessor definitions for the bitfield "dca{d}_pay_en".
437
 * parameter: dca {d} | stride size 0x4 | range [0, 31]
438
 * port="pif_rdm_dca_pay_en_i[0]"
439
 */
440

441
/* register address for bitfield dca{d}_pay_en */
442
#define rdm_dcadpay_en_adr(dca) (0x00006100 + (dca) * 0x4)
443
/* bitmask for bitfield dca{d}_pay_en */
444
#define rdm_dcadpay_en_msk 0x20000000
445
/* inverted bitmask for bitfield dca{d}_pay_en */
446
#define rdm_dcadpay_en_mskn 0xdfffffff
447
/* lower bit position of bitfield dca{d}_pay_en */
448
#define rdm_dcadpay_en_shift 29
449
/* width of bitfield dca{d}_pay_en */
450
#define rdm_dcadpay_en_width 1
451
/* default value of bitfield dca{d}_pay_en */
452
#define rdm_dcadpay_en_default 0x0
453

454
/* RX rdm_int_rim_en Bitfield Definitions
455
 * Preprocessor definitions for the bitfield "rdm_int_rim_en".
456
 * PORT="pif_rdm_int_rim_en_i"
457
 */
458

459
/* Register address for bitfield rdm_int_rim_en */
460
#define rdm_int_rim_en_adr 0x00005A30
461
/* Bitmask for bitfield rdm_int_rim_en */
462
#define rdm_int_rim_en_msk 0x00000008
463
/* Inverted bitmask for bitfield rdm_int_rim_en */
464
#define rdm_int_rim_en_mskn 0xFFFFFFF7
465
/* Lower bit position of bitfield rdm_int_rim_en */
466
#define rdm_int_rim_en_shift 3
467
/* Width of bitfield rdm_int_rim_en */
468
#define rdm_int_rim_en_width 1
469
/* Default value of bitfield rdm_int_rim_en */
470
#define rdm_int_rim_en_default 0x0
471

472
/* general interrupt mapping register definitions
473
 * preprocessor definitions for general interrupt mapping register
474
 * base address: 0x00002180
475
 * parameter: regidx {f} | stride size 0x4 | range [0, 3]
476
 */
477
#define gen_intr_map_adr(regidx) (0x00002180u + (regidx) * 0x4)
478

479
/* general interrupt status register definitions
480
 * preprocessor definitions for general interrupt status register
481
 * address: 0x000021A0
482
 */
483

484
#define gen_intr_stat_adr 0x000021A4U
485

486
/* interrupt global control register  definitions
487
 * preprocessor definitions for interrupt global control register
488
 * address: 0x00002300
489
 */
490
#define intr_glb_ctl_adr 0x00002300u
491

492
/* interrupt throttle register definitions
493
 * preprocessor definitions for interrupt throttle register
494
 * base address: 0x00002800
495
 * parameter: throttle {t} | stride size 0x4 | range [0, 31]
496
 */
497
#define intr_thr_adr(throttle) (0x00002800u + (throttle) * 0x4)
498

499
/* Register address for bitfield imr_link_en */
500
#define itrImrLinkEn_ADR 0x00002180
501
/* Bitmask for bitfield imr_link_en */
502
#define itrImrLinkEn_MSK 0x00008000
503
/* Inverted bitmask for bitfield imr_link_en */
504
#define itrImrLinkEn_MSKN 0xFFFF7FFF
505
/* Lower bit position of bitfield imr_link_en */
506
#define itrImrLinkEn_SHIFT 15
507
/* Width of bitfield imr_link_en */
508
#define itrImrLinkEn_WIDTH 1
509
/* Default value of bitfield imr_link_en */
510
#define itrImrLinkEn_DEFAULT 0x0
511

512
/* Register address for bitfield imr_link[4:0] */
513
#define itrImrLink_ADR 0x00002180
514
/* Bitmask for bitfield imr_link[4:0] */
515
#define itrImrLink_MSK 0x00001F00
516
/* Inverted bitmask for bitfield imr_link[4:0] */
517
#define itrImrLink_MSKN 0xFFFFE0FF
518
/* Lower bit position of bitfield imr_link[4:0] */
519
#define itrImrLink_SHIFT 8
520
/* Width of bitfield imr_link[4:0] */
521
#define itrImrLink_WIDTH 5
522
/* Default value of bitfield imr_link[4:0] */
523
#define itrImrLink_DEFAULT 0x0
524

525

526
/* INTR imr_mif{M}_en Bitfield Definitions
527
*  Preprocessor definitions for the bitfield "imr_mif{M}_en".
528
*  Parameter: MIF {M} | bit-level stride | range [0, 3]
529
*  PORT="pif_itr_map_mif_en_i[0]"
530
*/
531
/* Register address for bitfield imr_mif{M}_en */
532
#define itrImrMifMEn_ADR(MIF) \
533
	(((MIF) == 0) ? 0x0000218C : \
534
	(((MIF) == 1) ? 0x0000218C : \
535
	(((MIF) == 2) ? 0x0000218C : \
536
	(((MIF) == 3) ? 0x0000218C : \
537
	0))))
538
/* Bitmask for bitfield imr_mif{M}_en */
539
#define itrImrMifMEn_MSK(MIF) \
540
	(((MIF) == 0) ? 0x80000000 : \
541
	(((MIF) == 1) ? 0x00800000 : \
542
	(((MIF) == 2) ? 0x00008000 : \
543
	(((MIF) == 3) ? 0x00000080 : \
544
	0))))
545
/* Inverted bitmask for bitfield imr_mif{M}_en */
546
#define itrImrMifMEn_MSKN(MIF) \
547
	(((MIF) == 0) ? 0x7FFFFFFF : \
548
	(((MIF) == 1) ? 0xFF7FFFFF : \
549
	(((MIF) == 2) ? 0xFFFF7FFF : \
550
	(((MIF) == 3) ? 0xFFFFFF7F : \
551
	0))))
552
/* Lower bit position of bitfield imr_mif{M}_en */
553
#define itrImrMifMEn_SHIFT(MIF) \
554
	(((MIF) == 0) ? 31 : \
555
	(((MIF) == 1) ? 23 : \
556
	(((MIF) == 2) ? 15 : \
557
	(((MIF) == 3) ? 7 : \
558
	0))))
559
/* Width of bitfield imr_mif{M}_en */
560
#define itrImrMifMEn_WIDTH 1
561
/* Default value of bitfield imr_mif{M}_en */
562
#define itrImrMifMEn_DEFAULT 0x0
563

564
/* INTR imr_mif{M}[4:0] Bitfield Definitions
565
*   Preprocessor definitions for the bitfield "imr_mif{M}[4:0]".
566
*   Parameter: MIF {M} | bit-level stride | range [0, 3]
567
*   PORT="pif_itr_map_mif0_i[4:0]"
568
*/
569
/* Register address for bitfield imr_mif{M}[4:0] */
570
#define itrImrMifM_ADR(MIF) \
571
	(((MIF) == 0) ? 0x0000218C : \
572
	(((MIF) == 1) ? 0x0000218C : \
573
	(((MIF) == 2) ? 0x0000218C : \
574
	(((MIF) == 3) ? 0x0000218C : \
575
	0))))
576
/* Bitmask for bitfield imr_mif{M}[4:0] */
577
#define itrImrMifM_MSK(MIF) \
578
	(((MIF) == 0) ? 0x1F000000 : \
579
	(((MIF) == 1) ? 0x001F0000 : \
580
	(((MIF) == 2) ? 0x00001F00 : \
581
	(((MIF) == 3) ? 0x0000001F : \
582
	0))))
583
/* Inverted bitmask for bitfield imr_mif{M}[4:0] */
584
#define itrImrMifM_MSKN(MIF) \
585
	(((MIF) == 0) ? 0xE0FFFFFF : \
586
	(((MIF) == 1) ? 0xFFE0FFFF : \
587
	(((MIF) == 2) ? 0xFFFFE0FF : \
588
	(((MIF) == 3) ? 0xFFFFFFE0 : \
589
	0))))
590
/* Lower bit position of bitfield imr_mif{M}[4:0] */
591
#define itrImrMifM_SHIFT(MIF) \
592
	(((MIF) == 0) ? 24 : \
593
	(((MIF) == 1) ? 16 : \
594
	(((MIF) == 2) ? 8 : \
595
	(((MIF) == 3) ? 0 : \
596
	0))))
597
/* Width of bitfield imr_mif{M}[4:0] */
598
#define itrImrMifM_WIDTH 5
599
/* Default value of bitfield imr_mif{M}[4:0] */
600
#define itrImrMifM_DEFAULT 0x0
601

602

603
/* Register address for bitfield int_mode[1:0] */
604
#define itrIntMode_ADR 0x00002300
605
/* Bitmask for bitfield int_mode[1:0] */
606
#define itrIntMode_MSK 0x00000003
607
/* Inverted bitmask for bitfield int_mode[1:0] */
608
#define itrIntMode_MSKN 0xFFFFFFFC
609
/* Lower bit position of bitfield int_mode[1:0] */
610
#define itrIntMode_SHIFT 0
611
/*f Width of bitfield int_mode[1:0] */
612
#define itrIntMode_WIDTH 2
613
/* Default value of bitfield int_mode[1:0] */
614
#define itrIntMode_DEFAULT 0x0
615

616
/* Register address for bitfield isr_cor_en */
617
#define itrIsrCorEn_ADR 0x00002300
618
/* Bitmask for bitfield isr_cor_en */
619
#define itrIsrCorEn_MSK 0x00000080
620
/* Inverted bitmask for bitfield isr_cor_en */
621
#define itrIsrCorEn_MSKN 0xFFFFFF7F
622
/* Lower bit position of bitfield isr_cor_en */
623
#define itrIsrCorEn_SHIFT 7
624
/* Width of bitfield isr_cor_en */
625
#define itrIsrCorEn_WIDTH 1
626
/* Default value of bitfield isr_cor_en */
627
#define itrIsrCorEn_DEFAULT 0x0
628
/*@}*/
629

630
/* Register address for bitfield iamr_clr_en */
631
#define itrIamrClrEn_ADR 0x00002300
632
/* Bitmask for bitfield iamr_clr_en */
633
#define itrIamrClrEn_MSK 0x00000020
634
/* Inverted bitmask for bitfield iamr_clr_en */
635
#define itrIamrClrEn_MSKN 0xFFFFFFDF
636
/* Lower bit position of bitfield iamr_clr_en */
637
#define itrIamrClrEn_SHIFT 5
638
/* Width of bitfield iamr_clr_en */
639
#define itrIamrClrEn_WIDTH 1
640
/* Default value of bitfield iamr_clr_en */
641
#define itrIamrClrEn_DEFAULT 0x0
642

643
/* rx dma descriptor base address lsw definitions
644
 * preprocessor definitions for rx dma descriptor base address lsw
645
 * base address: 0x00005b00
646
 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
647
 */
648
#define rx_dma_desc_base_addrlsw_adr(descriptor) \
649
(0x00005b00u + (descriptor) * 0x20)
650

651
/* rx dma descriptor base address msw definitions
652
 * preprocessor definitions for rx dma descriptor base address msw
653
 * base address: 0x00005b04
654
 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
655
 */
656
#define rx_dma_desc_base_addrmsw_adr(descriptor) \
657
(0x00005b04u + (descriptor) * 0x20)
658

659
/* rx dma descriptor status register definitions
660
 * preprocessor definitions for rx dma descriptor status register
661
 * base address: 0x00005b14
662
 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
663
 */
664
#define rx_dma_desc_stat_adr(descriptor) (0x00005b14u + (descriptor) * 0x20)
665

666
/* rx dma descriptor tail pointer register definitions
667
 * preprocessor definitions for rx dma descriptor tail pointer register
668
 * base address: 0x00005b10
669
 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
670
 */
671
#define rx_dma_desc_tail_ptr_adr(descriptor) (0x00005b10u + (descriptor) * 0x20)
672

673
/* rx interrupt moderation control register definitions
674
 * Preprocessor definitions for RX Interrupt Moderation Control Register
675
 * Base Address: 0x00005A40
676
 * Parameter: RIM {R} | stride size 0x4 | range [0, 31]
677
 */
678
#define rx_intr_moderation_ctl_adr(rim) (0x00005A40u + (rim) * 0x4)
679

680
/* rx filter multicast filter mask register definitions
681
 * preprocessor definitions for rx filter multicast filter mask register
682
 * address: 0x00005270
683
 */
684
#define rx_flr_mcst_flr_msk_adr 0x00005270u
685

686
/* rx filter multicast filter register definitions
687
 * preprocessor definitions for rx filter multicast filter register
688
 * base address: 0x00005250
689
 * parameter: filter {f} | stride size 0x4 | range [0, 7]
690
 */
691
#define rx_flr_mcst_flr_adr(filter) (0x00005250u + (filter) * 0x4)
692

693
/* RX Filter RSS Control Register 1 Definitions
694
 * Preprocessor definitions for RX Filter RSS Control Register 1
695
 * Address: 0x000054C0
696
 */
697
#define rx_flr_rss_control1_adr 0x000054C0u
698

699
/* RX Filter Control Register 2 Definitions
700
 * Preprocessor definitions for RX Filter Control Register 2
701
 * Address: 0x00005104
702
 */
703
#define rx_flr_control2_adr 0x00005104u
704

705
/* tx tx dma debug control [1f:0] bitfield definitions
706
 * preprocessor definitions for the bitfield "tx dma debug control [1f:0]".
707
 * port="pif_tdm_debug_cntl_i[31:0]"
708
 */
709

710
/* register address for bitfield tx dma debug control [1f:0] */
711
#define tdm_tx_dma_debug_ctl_adr 0x00008920
712
/* bitmask for bitfield tx dma debug control [1f:0] */
713
#define tdm_tx_dma_debug_ctl_msk 0xffffffff
714
/* inverted bitmask for bitfield tx dma debug control [1f:0] */
715
#define tdm_tx_dma_debug_ctl_mskn 0x00000000
716
/* lower bit position of bitfield tx dma debug control [1f:0] */
717
#define tdm_tx_dma_debug_ctl_shift 0
718
/* width of bitfield tx dma debug control [1f:0] */
719
#define tdm_tx_dma_debug_ctl_width 32
720
/* default value of bitfield tx dma debug control [1f:0] */
721
#define tdm_tx_dma_debug_ctl_default 0x0
722

723
/* tx dma descriptor base address lsw definitions
724
 * preprocessor definitions for tx dma descriptor base address lsw
725
 * base address: 0x00007c00
726
 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
727
 */
728
#define tx_dma_desc_base_addrlsw_adr(descriptor) \
729
	(0x00007c00u + (descriptor) * 0x40)
730

731
/* tx dma descriptor tail pointer register definitions
732
 * preprocessor definitions for tx dma descriptor tail pointer register
733
 * base address: 0x00007c10
734
 *  parameter: descriptor {d} | stride size 0x40 | range [0, 31]
735
 */
736
#define tx_dma_desc_tail_ptr_adr(descriptor) (0x00007c10u + (descriptor) * 0x40)
737

738
/* rx dma_sys_loopback bitfield definitions
739
 * preprocessor definitions for the bitfield "dma_sys_loopback".
740
 * port="pif_rpb_dma_sys_lbk_i"
741
 */
742

743
/* register address for bitfield dma_sys_loopback */
744
#define rpb_dma_sys_lbk_adr 0x00005000
745
/* bitmask for bitfield dma_sys_loopback */
746
#define rpb_dma_sys_lbk_msk 0x00000040
747
/* inverted bitmask for bitfield dma_sys_loopback */
748
#define rpb_dma_sys_lbk_mskn 0xffffffbf
749
/* lower bit position of bitfield dma_sys_loopback */
750
#define rpb_dma_sys_lbk_shift 6
751
/* width of bitfield dma_sys_loopback */
752
#define rpb_dma_sys_lbk_width 1
753
/* default value of bitfield dma_sys_loopback */
754
#define rpb_dma_sys_lbk_default 0x0
755

756
/* rx rx_tc_mode bitfield definitions
757
 * preprocessor definitions for the bitfield "rx_tc_mode".
758
 * port="pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i"
759
 */
760

761
/* register address for bitfield rx_tc_mode */
762
#define rpb_rpf_rx_tc_mode_adr 0x00005700
763
/* bitmask for bitfield rx_tc_mode */
764
#define rpb_rpf_rx_tc_mode_msk 0x00000100
765
/* inverted bitmask for bitfield rx_tc_mode */
766
#define rpb_rpf_rx_tc_mode_mskn 0xfffffeff
767
/* lower bit position of bitfield rx_tc_mode */
768
#define rpb_rpf_rx_tc_mode_shift 8
769
/* width of bitfield rx_tc_mode */
770
#define rpb_rpf_rx_tc_mode_width 1
771
/* default value of bitfield rx_tc_mode */
772
#define rpb_rpf_rx_tc_mode_default 0x0
773

774
/* rx rx_buf_en bitfield definitions
775
 * preprocessor definitions for the bitfield "rx_buf_en".
776
 * port="pif_rpb_rx_buf_en_i"
777
 */
778

779
/* register address for bitfield rx_buf_en */
780
#define rpb_rx_buf_en_adr 0x00005700
781
/* bitmask for bitfield rx_buf_en */
782
#define rpb_rx_buf_en_msk 0x00000001
783
/* inverted bitmask for bitfield rx_buf_en */
784
#define rpb_rx_buf_en_mskn 0xfffffffe
785
/* lower bit position of bitfield rx_buf_en */
786
#define rpb_rx_buf_en_shift 0
787
/* width of bitfield rx_buf_en */
788
#define rpb_rx_buf_en_width 1
789
/* default value of bitfield rx_buf_en */
790
#define rpb_rx_buf_en_default 0x0
791

792
/* rx rx{b}_hi_thresh[d:0] bitfield definitions
793
 * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]".
794
 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
795
 * port="pif_rpb_rx0_hi_thresh_i[13:0]"
796
 */
797

798
/* register address for bitfield rx{b}_hi_thresh[d:0] */
799
#define rpb_rxbhi_thresh_adr(buffer) (0x00005714 + (buffer) * 0x10)
800
/* bitmask for bitfield rx{b}_hi_thresh[d:0] */
801
#define rpb_rxbhi_thresh_msk 0x3fff0000
802
/* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */
803
#define rpb_rxbhi_thresh_mskn 0xc000ffff
804
/* lower bit position of bitfield rx{b}_hi_thresh[d:0] */
805
#define rpb_rxbhi_thresh_shift 16
806
/* width of bitfield rx{b}_hi_thresh[d:0] */
807
#define rpb_rxbhi_thresh_width 14
808
/* default value of bitfield rx{b}_hi_thresh[d:0] */
809
#define rpb_rxbhi_thresh_default 0x0
810

811
/* rx rx{b}_lo_thresh[d:0] bitfield definitions
812
 * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]".
813
 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
814
 * port="pif_rpb_rx0_lo_thresh_i[13:0]"
815
 */
816

817
/* register address for bitfield rx{b}_lo_thresh[d:0] */
818
#define rpb_rxblo_thresh_adr(buffer) (0x00005714 + (buffer) * 0x10)
819
/* bitmask for bitfield rx{b}_lo_thresh[d:0] */
820
#define rpb_rxblo_thresh_msk 0x00003fff
821
/* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */
822
#define rpb_rxblo_thresh_mskn 0xffffc000
823
/* lower bit position of bitfield rx{b}_lo_thresh[d:0] */
824
#define rpb_rxblo_thresh_shift 0
825
/* width of bitfield rx{b}_lo_thresh[d:0] */
826
#define rpb_rxblo_thresh_width 14
827
/* default value of bitfield rx{b}_lo_thresh[d:0] */
828
#define rpb_rxblo_thresh_default 0x0
829

830
/* rx rx_fc_mode[1:0] bitfield definitions
831
 * preprocessor definitions for the bitfield "rx_fc_mode[1:0]".
832
 * port="pif_rpb_rx_fc_mode_i[1:0]"
833
 */
834

835
/* register address for bitfield rx_fc_mode[1:0] */
836
#define rpb_rx_fc_mode_adr 0x00005700
837
/* bitmask for bitfield rx_fc_mode[1:0] */
838
#define rpb_rx_fc_mode_msk 0x00000030
839
/* inverted bitmask for bitfield rx_fc_mode[1:0] */
840
#define rpb_rx_fc_mode_mskn 0xffffffcf
841
/* lower bit position of bitfield rx_fc_mode[1:0] */
842
#define rpb_rx_fc_mode_shift 4
843
/* width of bitfield rx_fc_mode[1:0] */
844
#define rpb_rx_fc_mode_width 2
845
/* default value of bitfield rx_fc_mode[1:0] */
846
#define rpb_rx_fc_mode_default 0x0
847

848
/* rx rx{b}_buf_size[8:0] bitfield definitions
849
 * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]".
850
 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
851
 * port="pif_rpb_rx0_buf_size_i[8:0]"
852
 */
853

854
/* register address for bitfield rx{b}_buf_size[8:0] */
855
#define rpb_rxbbuf_size_adr(buffer) (0x00005710 + (buffer) * 0x10)
856
/* bitmask for bitfield rx{b}_buf_size[8:0] */
857
#define rpb_rxbbuf_size_msk 0x000001ff
858
/* inverted bitmask for bitfield rx{b}_buf_size[8:0] */
859
#define rpb_rxbbuf_size_mskn 0xfffffe00
860
/* lower bit position of bitfield rx{b}_buf_size[8:0] */
861
#define rpb_rxbbuf_size_shift 0
862
/* width of bitfield rx{b}_buf_size[8:0] */
863
#define rpb_rxbbuf_size_width 9
864
/* default value of bitfield rx{b}_buf_size[8:0] */
865
#define rpb_rxbbuf_size_default 0x0
866

867
/* rx rx{b}_xoff_en bitfield definitions
868
 * preprocessor definitions for the bitfield "rx{b}_xoff_en".
869
 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
870
 * port="pif_rpb_rx_xoff_en_i[0]"
871
 */
872

873
/* register address for bitfield rx{b}_xoff_en */
874
#define rpb_rxbxoff_en_adr(buffer) (0x00005714 + (buffer) * 0x10)
875
/* bitmask for bitfield rx{b}_xoff_en */
876
#define rpb_rxbxoff_en_msk 0x80000000
877
/* inverted bitmask for bitfield rx{b}_xoff_en */
878
#define rpb_rxbxoff_en_mskn 0x7fffffff
879
/* lower bit position of bitfield rx{b}_xoff_en */
880
#define rpb_rxbxoff_en_shift 31
881
/* width of bitfield rx{b}_xoff_en */
882
#define rpb_rxbxoff_en_width 1
883
/* default value of bitfield rx{b}_xoff_en */
884
#define rpb_rxbxoff_en_default 0x0
885

886
/* rx l2_bc_thresh[f:0] bitfield definitions
887
 * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]".
888
 * port="pif_rpf_l2_bc_thresh_i[15:0]"
889
 */
890

891
/* register address for bitfield l2_bc_thresh[f:0] */
892
#define rpfl2bc_thresh_adr 0x00005100
893
/* bitmask for bitfield l2_bc_thresh[f:0] */
894
#define rpfl2bc_thresh_msk 0xffff0000
895
/* inverted bitmask for bitfield l2_bc_thresh[f:0] */
896
#define rpfl2bc_thresh_mskn 0x0000ffff
897
/* lower bit position of bitfield l2_bc_thresh[f:0] */
898
#define rpfl2bc_thresh_shift 16
899
/* width of bitfield l2_bc_thresh[f:0] */
900
#define rpfl2bc_thresh_width 16
901
/* default value of bitfield l2_bc_thresh[f:0] */
902
#define rpfl2bc_thresh_default 0x0
903

904
/* rx l2_bc_en bitfield definitions
905
 * preprocessor definitions for the bitfield "l2_bc_en".
906
 * port="pif_rpf_l2_bc_en_i"
907
 */
908

909
/* register address for bitfield l2_bc_en */
910
#define rpfl2bc_en_adr 0x00005100
911
/* bitmask for bitfield l2_bc_en */
912
#define rpfl2bc_en_msk 0x00000001
913
/* inverted bitmask for bitfield l2_bc_en */
914
#define rpfl2bc_en_mskn 0xfffffffe
915
/* lower bit position of bitfield l2_bc_en */
916
#define rpfl2bc_en_shift 0
917
/* width of bitfield l2_bc_en */
918
#define rpfl2bc_en_width 1
919
/* default value of bitfield l2_bc_en */
920
#define rpfl2bc_en_default 0x0
921

922
/* rx l2_bc_act[2:0] bitfield definitions
923
 * preprocessor definitions for the bitfield "l2_bc_act[2:0]".
924
 * port="pif_rpf_l2_bc_act_i[2:0]"
925
 */
926

927
/* register address for bitfield l2_bc_act[2:0] */
928
#define rpfl2bc_act_adr 0x00005100
929
/* bitmask for bitfield l2_bc_act[2:0] */
930
#define rpfl2bc_act_msk 0x00007000
931
/* inverted bitmask for bitfield l2_bc_act[2:0] */
932
#define rpfl2bc_act_mskn 0xffff8fff
933
/* lower bit position of bitfield l2_bc_act[2:0] */
934
#define rpfl2bc_act_shift 12
935
/* width of bitfield l2_bc_act[2:0] */
936
#define rpfl2bc_act_width 3
937
/* default value of bitfield l2_bc_act[2:0] */
938
#define rpfl2bc_act_default 0x0
939

940
/* rx l2_mc_en{f} bitfield definitions
941
 * preprocessor definitions for the bitfield "l2_mc_en{f}".
942
 * parameter: filter {f} | stride size 0x4 | range [0, 7]
943
 * port="pif_rpf_l2_mc_en_i[0]"
944
 */
945

946
/* register address for bitfield l2_mc_en{f} */
947
#define rpfl2mc_enf_adr(filter) (0x00005250 + (filter) * 0x4)
948
/* bitmask for bitfield l2_mc_en{f} */
949
#define rpfl2mc_enf_msk 0x80000000
950
/* inverted bitmask for bitfield l2_mc_en{f} */
951
#define rpfl2mc_enf_mskn 0x7fffffff
952
/* lower bit position of bitfield l2_mc_en{f} */
953
#define rpfl2mc_enf_shift 31
954
/* width of bitfield l2_mc_en{f} */
955
#define rpfl2mc_enf_width 1
956
/* default value of bitfield l2_mc_en{f} */
957
#define rpfl2mc_enf_default 0x0
958

959
/* rx l2_promis_mode bitfield definitions
960
 * preprocessor definitions for the bitfield "l2_promis_mode".
961
 * port="pif_rpf_l2_promis_mode_i"
962
 */
963

964
/* register address for bitfield l2_promis_mode */
965
#define rpfl2promis_mode_adr 0x00005100
966
/* bitmask for bitfield l2_promis_mode */
967
#define rpfl2promis_mode_msk 0x00000008
968
/* inverted bitmask for bitfield l2_promis_mode */
969
#define rpfl2promis_mode_mskn 0xfffffff7
970
/* lower bit position of bitfield l2_promis_mode */
971
#define rpfl2promis_mode_shift 3
972
/* width of bitfield l2_promis_mode */
973
#define rpfl2promis_mode_width 1
974
/* default value of bitfield l2_promis_mode */
975
#define rpfl2promis_mode_default 0x0
976

977
/* rx l2_uc_act{f}[2:0] bitfield definitions
978
 * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]".
979
 * parameter: filter {f} | stride size 0x8 | range [0, 37]
980
 * port="pif_rpf_l2_uc_act0_i[2:0]"
981
 */
982

983
/* register address for bitfield l2_uc_act{f}[2:0] */
984
#define rpfl2uc_actf_adr(filter) (0x00005114 + (filter) * 0x8)
985
/* bitmask for bitfield l2_uc_act{f}[2:0] */
986
#define rpfl2uc_actf_msk 0x00070000
987
/* inverted bitmask for bitfield l2_uc_act{f}[2:0] */
988
#define rpfl2uc_actf_mskn 0xfff8ffff
989
/* lower bit position of bitfield l2_uc_act{f}[2:0] */
990
#define rpfl2uc_actf_shift 16
991
/* width of bitfield l2_uc_act{f}[2:0] */
992
#define rpfl2uc_actf_width 3
993
/* default value of bitfield l2_uc_act{f}[2:0] */
994
#define rpfl2uc_actf_default 0x0
995

996
/* rx l2_uc_en{f} bitfield definitions
997
 * preprocessor definitions for the bitfield "l2_uc_en{f}".
998
 * parameter: filter {f} | stride size 0x8 | range [0, 37]
999
 * port="pif_rpf_l2_uc_en_i[0]"
1000
 */
1001

1002
/* register address for bitfield l2_uc_en{f} */
1003
#define rpfl2uc_enf_adr(filter) (0x00005114 + (filter) * 0x8)
1004
/* bitmask for bitfield l2_uc_en{f} */
1005
#define rpfl2uc_enf_msk 0x80000000
1006
/* inverted bitmask for bitfield l2_uc_en{f} */
1007
#define rpfl2uc_enf_mskn 0x7fffffff
1008
/* lower bit position of bitfield l2_uc_en{f} */
1009
#define rpfl2uc_enf_shift 31
1010
/* width of bitfield l2_uc_en{f} */
1011
#define rpfl2uc_enf_width 1
1012
/* default value of bitfield l2_uc_en{f} */
1013
#define rpfl2uc_enf_default 0x0
1014

1015
/* register address for bitfield l2_uc_da{f}_lsw[1f:0] */
1016
#define rpfl2uc_daflsw_adr(filter) (0x00005110 + (filter) * 0x8)
1017
/* register address for bitfield l2_uc_da{f}_msw[f:0] */
1018
#define rpfl2uc_dafmsw_adr(filter) (0x00005114 + (filter) * 0x8)
1019
/* bitmask for bitfield l2_uc_da{f}_msw[f:0] */
1020
#define rpfl2uc_dafmsw_msk 0x0000ffff
1021
/* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */
1022
#define rpfl2uc_dafmsw_shift 0
1023

1024
/* rx l2_mc_accept_all bitfield definitions
1025
 * Preprocessor definitions for the bitfield "l2_mc_accept_all".
1026
 * PORT="pif_rpf_l2_mc_all_accept_i"
1027
 */
1028

1029
/* Register address for bitfield l2_mc_accept_all */
1030
#define rpfl2mc_accept_all_adr 0x00005270
1031
/* Bitmask for bitfield l2_mc_accept_all */
1032
#define rpfl2mc_accept_all_msk 0x00004000
1033
/* Inverted bitmask for bitfield l2_mc_accept_all */
1034
#define rpfl2mc_accept_all_mskn 0xFFFFBFFF
1035
/* Lower bit position of bitfield l2_mc_accept_all */
1036
#define rpfl2mc_accept_all_shift 14
1037
/* Width of bitfield l2_mc_accept_all */
1038
#define rpfl2mc_accept_all_width 1
1039
/* Default value of bitfield l2_mc_accept_all */
1040
#define rpfl2mc_accept_all_default 0x0
1041

1042
/* width of bitfield rx_tc_up{t}[2:0] */
1043
#define rpf_rpb_rx_tc_upt_width 3
1044
/* default value of bitfield rx_tc_up{t}[2:0] */
1045
#define rpf_rpb_rx_tc_upt_default 0x0
1046

1047
/* rx rss_key_addr[4:0] bitfield definitions
1048
 * preprocessor definitions for the bitfield "rss_key_addr[4:0]".
1049
 * port="pif_rpf_rss_key_addr_i[4:0]"
1050
 */
1051

1052
/* register address for bitfield rss_key_addr[4:0] */
1053
#define rpf_rss_key_addr_adr 0x000054d0
1054
/* bitmask for bitfield rss_key_addr[4:0] */
1055
#define rpf_rss_key_addr_msk 0x0000001f
1056
/* inverted bitmask for bitfield rss_key_addr[4:0] */
1057
#define rpf_rss_key_addr_mskn 0xffffffe0
1058
/* lower bit position of bitfield rss_key_addr[4:0] */
1059
#define rpf_rss_key_addr_shift 0
1060
/* width of bitfield rss_key_addr[4:0] */
1061
#define rpf_rss_key_addr_width 5
1062
/* default value of bitfield rss_key_addr[4:0] */
1063
#define rpf_rss_key_addr_default 0x0
1064

1065
/* rx rss_key_wr_data[1f:0] bitfield definitions
1066
 * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]".
1067
 * port="pif_rpf_rss_key_wr_data_i[31:0]"
1068
 */
1069

1070
/* register address for bitfield rss_key_wr_data[1f:0] */
1071
#define rpf_rss_key_wr_data_adr 0x000054d4
1072
/* bitmask for bitfield rss_key_wr_data[1f:0] */
1073
#define rpf_rss_key_wr_data_msk 0xffffffff
1074
/* inverted bitmask for bitfield rss_key_wr_data[1f:0] */
1075
#define rpf_rss_key_wr_data_mskn 0x00000000
1076
/* lower bit position of bitfield rss_key_wr_data[1f:0] */
1077
#define rpf_rss_key_wr_data_shift 0
1078
/* width of bitfield rss_key_wr_data[1f:0] */
1079
#define rpf_rss_key_wr_data_width 32
1080
/* default value of bitfield rss_key_wr_data[1f:0] */
1081
#define rpf_rss_key_wr_data_default 0x0
1082

1083
/* rx rss_key_rd_data[1f:0] bitfield definitions
1084
 * preprocessor definitions for the bitfield "rss_key_rd_data[1f:0]".
1085
 * port="pif_rpf_rss_key_wr_data_i[31:0]"
1086
 */
1087

1088
/* register address for bitfield rss_key_rd_data[1f:0] */
1089
#define rpf_rss_key_rd_data_adr 0x000054d8
1090
/* bitmask for bitfield rss_key_rd_data[1f:0] */
1091
#define rpf_rss_key_rd_data_msk 0xffffffff
1092
/* inverted bitmask for bitfield rss_key_rd_data[1f:0] */
1093
#define rpf_rss_key_rd_data_mskn 0x00000000
1094
/* lower bit position of bitfield rss_key_rd_data[1f:0] */
1095
#define rpf_rss_key_rd_data_shift 0
1096
/* width of bitfield rss_key_rd_data[1f:0] */
1097
#define rpf_rss_key_rd_data_width 32
1098
/* default value of bitfield rss_key_rd_data[1f:0] */
1099
#define rpf_rss_key_rd_data_default 0x0
1100

1101
/* rx rss_key_wr_en_i bitfield definitions
1102
 * preprocessor definitions for the bitfield "rss_key_wr_en_i".
1103
 * port="pif_rpf_rss_key_wr_en_i"
1104
 */
1105

1106
/* register address for bitfield rss_key_wr_en_i */
1107
#define rpf_rss_key_wr_eni_adr 0x000054d0
1108
/* bitmask for bitfield rss_key_wr_en_i */
1109
#define rpf_rss_key_wr_eni_msk 0x00000020
1110
/* inverted bitmask for bitfield rss_key_wr_en_i */
1111
#define rpf_rss_key_wr_eni_mskn 0xffffffdf
1112
/* lower bit position of bitfield rss_key_wr_en_i */
1113
#define rpf_rss_key_wr_eni_shift 5
1114
/* width of bitfield rss_key_wr_en_i */
1115
#define rpf_rss_key_wr_eni_width 1
1116
/* default value of bitfield rss_key_wr_en_i */
1117
#define rpf_rss_key_wr_eni_default 0x0
1118

1119
/* rx rss_redir_addr[3:0] bitfield definitions
1120
 * preprocessor definitions for the bitfield "rss_redir_addr[3:0]".
1121
 * port="pif_rpf_rss_redir_addr_i[3:0]"
1122
 */
1123

1124
/* register address for bitfield rss_redir_addr[3:0] */
1125
#define rpf_rss_redir_addr_adr 0x000054e0
1126
/* bitmask for bitfield rss_redir_addr[3:0] */
1127
#define rpf_rss_redir_addr_msk 0x0000000f
1128
/* inverted bitmask for bitfield rss_redir_addr[3:0] */
1129
#define rpf_rss_redir_addr_mskn 0xfffffff0
1130
/* lower bit position of bitfield rss_redir_addr[3:0] */
1131
#define rpf_rss_redir_addr_shift 0
1132
/* width of bitfield rss_redir_addr[3:0] */
1133
#define rpf_rss_redir_addr_width 4
1134
/* default value of bitfield rss_redir_addr[3:0] */
1135
#define rpf_rss_redir_addr_default 0x0
1136

1137
/* rx rss_redir_wr_data[f:0] bitfield definitions
1138
 * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]".
1139
 * port="pif_rpf_rss_redir_wr_data_i[15:0]"
1140
 */
1141

1142
/* register address for bitfield rss_redir_wr_data[f:0] */
1143
#define rpf_rss_redir_wr_data_adr 0x000054e4
1144
/* bitmask for bitfield rss_redir_wr_data[f:0] */
1145
#define rpf_rss_redir_wr_data_msk 0x0000ffff
1146
/* inverted bitmask for bitfield rss_redir_wr_data[f:0] */
1147
#define rpf_rss_redir_wr_data_mskn 0xffff0000
1148
/* lower bit position of bitfield rss_redir_wr_data[f:0] */
1149
#define rpf_rss_redir_wr_data_shift 0
1150
/* width of bitfield rss_redir_wr_data[f:0] */
1151
#define rpf_rss_redir_wr_data_width 16
1152
/* default value of bitfield rss_redir_wr_data[f:0] */
1153
#define rpf_rss_redir_wr_data_default 0x0
1154

1155
/* rx rss_redir_wr_en_i bitfield definitions
1156
 * preprocessor definitions for the bitfield "rss_redir_wr_en_i".
1157
 * port="pif_rpf_rss_redir_wr_en_i"
1158
 */
1159

1160
/* register address for bitfield rss_redir_wr_en_i */
1161
#define rpf_rss_redir_wr_eni_adr 0x000054e0
1162
/* bitmask for bitfield rss_redir_wr_en_i */
1163
#define rpf_rss_redir_wr_eni_msk 0x00000010
1164
/* inverted bitmask for bitfield rss_redir_wr_en_i */
1165
#define rpf_rss_redir_wr_eni_mskn 0xffffffef
1166
/* lower bit position of bitfield rss_redir_wr_en_i */
1167
#define rpf_rss_redir_wr_eni_shift 4
1168
/* width of bitfield rss_redir_wr_en_i */
1169
#define rpf_rss_redir_wr_eni_width 1
1170
/* default value of bitfield rss_redir_wr_en_i */
1171
#define rpf_rss_redir_wr_eni_default 0x0
1172

1173
/* rx tpo_rpf_sys_loopback bitfield definitions
1174
 * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback".
1175
 * port="pif_rpf_tpo_pkt_sys_lbk_i"
1176
 */
1177

1178
/* register address for bitfield tpo_rpf_sys_loopback */
1179
#define rpf_tpo_rpf_sys_lbk_adr 0x00005000
1180
/* bitmask for bitfield tpo_rpf_sys_loopback */
1181
#define rpf_tpo_rpf_sys_lbk_msk 0x00000100
1182
/* inverted bitmask for bitfield tpo_rpf_sys_loopback */
1183
#define rpf_tpo_rpf_sys_lbk_mskn 0xfffffeff
1184
/* lower bit position of bitfield tpo_rpf_sys_loopback */
1185
#define rpf_tpo_rpf_sys_lbk_shift 8
1186
/* width of bitfield tpo_rpf_sys_loopback */
1187
#define rpf_tpo_rpf_sys_lbk_width 1
1188
/* default value of bitfield tpo_rpf_sys_loopback */
1189
#define rpf_tpo_rpf_sys_lbk_default 0x0
1190

1191
/* rx vl_inner_tpid[f:0] bitfield definitions
1192
 * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]".
1193
 * port="pif_rpf_vl_inner_tpid_i[15:0]"
1194
 */
1195

1196
/* register address for bitfield vl_inner_tpid[f:0] */
1197
#define rpf_vl_inner_tpid_adr 0x00005284
1198
/* bitmask for bitfield vl_inner_tpid[f:0] */
1199
#define rpf_vl_inner_tpid_msk 0x0000ffff
1200
/* inverted bitmask for bitfield vl_inner_tpid[f:0] */
1201
#define rpf_vl_inner_tpid_mskn 0xffff0000
1202
/* lower bit position of bitfield vl_inner_tpid[f:0] */
1203
#define rpf_vl_inner_tpid_shift 0
1204
/* width of bitfield vl_inner_tpid[f:0] */
1205
#define rpf_vl_inner_tpid_width 16
1206
/* default value of bitfield vl_inner_tpid[f:0] */
1207
#define rpf_vl_inner_tpid_default 0x8100
1208

1209
/* rx vl_outer_tpid[f:0] bitfield definitions
1210
 * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]".
1211
 * port="pif_rpf_vl_outer_tpid_i[15:0]"
1212
 */
1213

1214
/* register address for bitfield vl_outer_tpid[f:0] */
1215
#define rpf_vl_outer_tpid_adr 0x00005284
1216
/* bitmask for bitfield vl_outer_tpid[f:0] */
1217
#define rpf_vl_outer_tpid_msk 0xffff0000
1218
/* inverted bitmask for bitfield vl_outer_tpid[f:0] */
1219
#define rpf_vl_outer_tpid_mskn 0x0000ffff
1220
/* lower bit position of bitfield vl_outer_tpid[f:0] */
1221
#define rpf_vl_outer_tpid_shift 16
1222
/* width of bitfield vl_outer_tpid[f:0] */
1223
#define rpf_vl_outer_tpid_width 16
1224
/* default value of bitfield vl_outer_tpid[f:0] */
1225
#define rpf_vl_outer_tpid_default 0x88a8
1226

1227
/* rx vl_promis_mode bitfield definitions
1228
 * preprocessor definitions for the bitfield "vl_promis_mode".
1229
 * port="pif_rpf_vl_promis_mode_i"
1230
 */
1231

1232
/* register address for bitfield vl_promis_mode */
1233
#define rpf_vl_promis_mode_adr 0x00005280
1234
/* bitmask for bitfield vl_promis_mode */
1235
#define rpf_vl_promis_mode_msk 0x00000002
1236
/* inverted bitmask for bitfield vl_promis_mode */
1237
#define rpf_vl_promis_mode_mskn 0xfffffffd
1238
/* lower bit position of bitfield vl_promis_mode */
1239
#define rpf_vl_promis_mode_shift 1
1240
/* width of bitfield vl_promis_mode */
1241
#define rpf_vl_promis_mode_width 1
1242
/* default value of bitfield vl_promis_mode */
1243
#define rpf_vl_promis_mode_default 0x0
1244

1245
/* RX vl_accept_untagged_mode Bitfield Definitions
1246
 * Preprocessor definitions for the bitfield "vl_accept_untagged_mode".
1247
 * PORT="pif_rpf_vl_accept_untagged_i"
1248
 */
1249

1250
/* Register address for bitfield vl_accept_untagged_mode */
1251
#define rpf_vl_accept_untagged_mode_adr 0x00005280
1252
/* Bitmask for bitfield vl_accept_untagged_mode */
1253
#define rpf_vl_accept_untagged_mode_msk 0x00000004
1254
/* Inverted bitmask for bitfield vl_accept_untagged_mode */
1255
#define rpf_vl_accept_untagged_mode_mskn 0xFFFFFFFB
1256
/* Lower bit position of bitfield vl_accept_untagged_mode */
1257
#define rpf_vl_accept_untagged_mode_shift 2
1258
/* Width of bitfield vl_accept_untagged_mode */
1259
#define rpf_vl_accept_untagged_mode_width 1
1260
/* Default value of bitfield vl_accept_untagged_mode */
1261
#define rpf_vl_accept_untagged_mode_default 0x0
1262

1263
/* rX vl_untagged_act[2:0] Bitfield Definitions
1264
 * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]".
1265
 * PORT="pif_rpf_vl_untagged_act_i[2:0]"
1266
 */
1267

1268
/* Register address for bitfield vl_untagged_act[2:0] */
1269
#define rpf_vl_untagged_act_adr 0x00005280
1270
/* Bitmask for bitfield vl_untagged_act[2:0] */
1271
#define rpf_vl_untagged_act_msk 0x00000038
1272
/* Inverted bitmask for bitfield vl_untagged_act[2:0] */
1273
#define rpf_vl_untagged_act_mskn 0xFFFFFFC7
1274
/* Lower bit position of bitfield vl_untagged_act[2:0] */
1275
#define rpf_vl_untagged_act_shift 3
1276
/* Width of bitfield vl_untagged_act[2:0] */
1277
#define rpf_vl_untagged_act_width 3
1278
/* Default value of bitfield vl_untagged_act[2:0] */
1279
#define rpf_vl_untagged_act_default 0x0
1280

1281
/* RX vl_en{F} Bitfield Definitions
1282
 * Preprocessor definitions for the bitfield "vl_en{F}".
1283
 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1284
 * PORT="pif_rpf_vl_en_i[0]"
1285
 */
1286

1287
/* Register address for bitfield vl_en{F} */
1288
#define rpf_vl_en_f_adr(filter) (0x00005290 + (filter) * 0x4)
1289
/* Bitmask for bitfield vl_en{F} */
1290
#define rpf_vl_en_f_msk 0x80000000
1291
/* Inverted bitmask for bitfield vl_en{F} */
1292
#define rpf_vl_en_f_mskn 0x7FFFFFFF
1293
/* Lower bit position of bitfield vl_en{F} */
1294
#define rpf_vl_en_f_shift 31
1295
/* Width of bitfield vl_en{F} */
1296
#define rpf_vl_en_f_width 1
1297
/* Default value of bitfield vl_en{F} */
1298
#define rpf_vl_en_f_default 0x0
1299

1300
/* RX vl_act{F}[2:0] Bitfield Definitions
1301
 * Preprocessor definitions for the bitfield "vl_act{F}[2:0]".
1302
 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1303
 * PORT="pif_rpf_vl_act0_i[2:0]"
1304
 */
1305

1306
/* Register address for bitfield vl_act{F}[2:0] */
1307
#define rpf_vl_act_f_adr(filter) (0x00005290 + (filter) * 0x4)
1308
/* Bitmask for bitfield vl_act{F}[2:0] */
1309
#define rpf_vl_act_f_msk 0x00070000
1310
/* Inverted bitmask for bitfield vl_act{F}[2:0] */
1311
#define rpf_vl_act_f_mskn 0xFFF8FFFF
1312
/* Lower bit position of bitfield vl_act{F}[2:0] */
1313
#define rpf_vl_act_f_shift 16
1314
/* Width of bitfield vl_act{F}[2:0] */
1315
#define rpf_vl_act_f_width 3
1316
/* Default value of bitfield vl_act{F}[2:0] */
1317
#define rpf_vl_act_f_default 0x0
1318

1319
/* RX vl_id{F}[B:0] Bitfield Definitions
1320
 * Preprocessor definitions for the bitfield "vl_id{F}[B:0]".
1321
 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1322
 * PORT="pif_rpf_vl_id0_i[11:0]"
1323
 */
1324

1325
/* Register address for bitfield vl_id{F}[B:0] */
1326
#define rpf_vl_id_f_adr(filter) (0x00005290 + (filter) * 0x4)
1327
/* Bitmask for bitfield vl_id{F}[B:0] */
1328
#define rpf_vl_id_f_msk 0x00000FFF
1329
/* Inverted bitmask for bitfield vl_id{F}[B:0] */
1330
#define rpf_vl_id_f_mskn 0xFFFFF000
1331
/* Lower bit position of bitfield vl_id{F}[B:0] */
1332
#define rpf_vl_id_f_shift 0
1333
/* Width of bitfield vl_id{F}[B:0] */
1334
#define rpf_vl_id_f_width 12
1335
/* Default value of bitfield vl_id{F}[B:0] */
1336
#define rpf_vl_id_f_default 0x0
1337

1338
/* RX et_en{F} Bitfield Definitions
1339
 * Preprocessor definitions for the bitfield "et_en{F}".
1340
 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1341
 * PORT="pif_rpf_et_en_i[0]"
1342
 */
1343

1344
/* Register address for bitfield et_en{F} */
1345
#define rpf_et_en_f_adr(filter) (0x00005300 + (filter) * 0x4)
1346
/* Bitmask for bitfield et_en{F} */
1347
#define rpf_et_en_f_msk 0x80000000
1348
/* Inverted bitmask for bitfield et_en{F} */
1349
#define rpf_et_en_f_mskn 0x7FFFFFFF
1350
/* Lower bit position of bitfield et_en{F} */
1351
#define rpf_et_en_f_shift 31
1352
/* Width of bitfield et_en{F} */
1353
#define rpf_et_en_f_width 1
1354
/* Default value of bitfield et_en{F} */
1355
#define rpf_et_en_f_default 0x0
1356

1357
/* rx et_en{f} bitfield definitions
1358
 * preprocessor definitions for the bitfield "et_en{f}".
1359
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1360
 * port="pif_rpf_et_en_i[0]"
1361
 */
1362

1363
/* register address for bitfield et_en{f} */
1364
#define rpf_et_enf_adr(filter) (0x00005300 + (filter) * 0x4)
1365
/* bitmask for bitfield et_en{f} */
1366
#define rpf_et_enf_msk 0x80000000
1367
/* inverted bitmask for bitfield et_en{f} */
1368
#define rpf_et_enf_mskn 0x7fffffff
1369
/* lower bit position of bitfield et_en{f} */
1370
#define rpf_et_enf_shift 31
1371
/* width of bitfield et_en{f} */
1372
#define rpf_et_enf_width 1
1373
/* default value of bitfield et_en{f} */
1374
#define rpf_et_enf_default 0x0
1375

1376
/* rx et_up{f}_en bitfield definitions
1377
 * preprocessor definitions for the bitfield "et_up{f}_en".
1378
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1379
 * port="pif_rpf_et_up_en_i[0]"
1380
 */
1381

1382
/* register address for bitfield et_up{f}_en */
1383
#define rpf_et_upfen_adr(filter) (0x00005300 + (filter) * 0x4)
1384
/* bitmask for bitfield et_up{f}_en */
1385
#define rpf_et_upfen_msk 0x40000000
1386
/* inverted bitmask for bitfield et_up{f}_en */
1387
#define rpf_et_upfen_mskn 0xbfffffff
1388
/* lower bit position of bitfield et_up{f}_en */
1389
#define rpf_et_upfen_shift 30
1390
/* width of bitfield et_up{f}_en */
1391
#define rpf_et_upfen_width 1
1392
/* default value of bitfield et_up{f}_en */
1393
#define rpf_et_upfen_default 0x0
1394

1395
/* rx et_rxq{f}_en bitfield definitions
1396
 * preprocessor definitions for the bitfield "et_rxq{f}_en".
1397
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1398
 * port="pif_rpf_et_rxq_en_i[0]"
1399
 */
1400

1401
/* register address for bitfield et_rxq{f}_en */
1402
#define rpf_et_rxqfen_adr(filter) (0x00005300 + (filter) * 0x4)
1403
/* bitmask for bitfield et_rxq{f}_en */
1404
#define rpf_et_rxqfen_msk 0x20000000
1405
/* inverted bitmask for bitfield et_rxq{f}_en */
1406
#define rpf_et_rxqfen_mskn 0xdfffffff
1407
/* lower bit position of bitfield et_rxq{f}_en */
1408
#define rpf_et_rxqfen_shift 29
1409
/* width of bitfield et_rxq{f}_en */
1410
#define rpf_et_rxqfen_width 1
1411
/* default value of bitfield et_rxq{f}_en */
1412
#define rpf_et_rxqfen_default 0x0
1413

1414
/* rx et_up{f}[2:0] bitfield definitions
1415
 * preprocessor definitions for the bitfield "et_up{f}[2:0]".
1416
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1417
 * port="pif_rpf_et_up0_i[2:0]"
1418
 */
1419

1420
/* register address for bitfield et_up{f}[2:0] */
1421
#define rpf_et_upf_adr(filter) (0x00005300 + (filter) * 0x4)
1422
/* bitmask for bitfield et_up{f}[2:0] */
1423
#define rpf_et_upf_msk 0x1c000000
1424
/* inverted bitmask for bitfield et_up{f}[2:0] */
1425
#define rpf_et_upf_mskn 0xe3ffffff
1426
/* lower bit position of bitfield et_up{f}[2:0] */
1427
#define rpf_et_upf_shift 26
1428
/* width of bitfield et_up{f}[2:0] */
1429
#define rpf_et_upf_width 3
1430
/* default value of bitfield et_up{f}[2:0] */
1431
#define rpf_et_upf_default 0x0
1432

1433
/* rx et_rxq{f}[4:0] bitfield definitions
1434
 * preprocessor definitions for the bitfield "et_rxq{f}[4:0]".
1435
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1436
 * port="pif_rpf_et_rxq0_i[4:0]"
1437
 */
1438

1439
/* register address for bitfield et_rxq{f}[4:0] */
1440
#define rpf_et_rxqf_adr(filter) (0x00005300 + (filter) * 0x4)
1441
/* bitmask for bitfield et_rxq{f}[4:0] */
1442
#define rpf_et_rxqf_msk 0x01f00000
1443
/* inverted bitmask for bitfield et_rxq{f}[4:0] */
1444
#define rpf_et_rxqf_mskn 0xfe0fffff
1445
/* lower bit position of bitfield et_rxq{f}[4:0] */
1446
#define rpf_et_rxqf_shift 20
1447
/* width of bitfield et_rxq{f}[4:0] */
1448
#define rpf_et_rxqf_width 5
1449
/* default value of bitfield et_rxq{f}[4:0] */
1450
#define rpf_et_rxqf_default 0x0
1451

1452
/* rx et_mng_rxq{f} bitfield definitions
1453
 * preprocessor definitions for the bitfield "et_mng_rxq{f}".
1454
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1455
 * port="pif_rpf_et_mng_rxq_i[0]"
1456
 */
1457

1458
/* register address for bitfield et_mng_rxq{f} */
1459
#define rpf_et_mng_rxqf_adr(filter) (0x00005300 + (filter) * 0x4)
1460
/* bitmask for bitfield et_mng_rxq{f} */
1461
#define rpf_et_mng_rxqf_msk 0x00080000
1462
/* inverted bitmask for bitfield et_mng_rxq{f} */
1463
#define rpf_et_mng_rxqf_mskn 0xfff7ffff
1464
/* lower bit position of bitfield et_mng_rxq{f} */
1465
#define rpf_et_mng_rxqf_shift 19
1466
/* width of bitfield et_mng_rxq{f} */
1467
#define rpf_et_mng_rxqf_width 1
1468
/* default value of bitfield et_mng_rxq{f} */
1469
#define rpf_et_mng_rxqf_default 0x0
1470

1471
/* rx et_act{f}[2:0] bitfield definitions
1472
 * preprocessor definitions for the bitfield "et_act{f}[2:0]".
1473
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1474
 * port="pif_rpf_et_act0_i[2:0]"
1475
 */
1476

1477
/* register address for bitfield et_act{f}[2:0] */
1478
#define rpf_et_actf_adr(filter) (0x00005300 + (filter) * 0x4)
1479
/* bitmask for bitfield et_act{f}[2:0] */
1480
#define rpf_et_actf_msk 0x00070000
1481
/* inverted bitmask for bitfield et_act{f}[2:0] */
1482
#define rpf_et_actf_mskn 0xfff8ffff
1483
/* lower bit position of bitfield et_act{f}[2:0] */
1484
#define rpf_et_actf_shift 16
1485
/* width of bitfield et_act{f}[2:0] */
1486
#define rpf_et_actf_width 3
1487
/* default value of bitfield et_act{f}[2:0] */
1488
#define rpf_et_actf_default 0x0
1489

1490
/* rx et_val{f}[f:0] bitfield definitions
1491
 * preprocessor definitions for the bitfield "et_val{f}[f:0]".
1492
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1493
 * port="pif_rpf_et_val0_i[15:0]"
1494
 */
1495

1496
/* register address for bitfield et_val{f}[f:0] */
1497
#define rpf_et_valf_adr(filter) (0x00005300 + (filter) * 0x4)
1498
/* bitmask for bitfield et_val{f}[f:0] */
1499
#define rpf_et_valf_msk 0x0000ffff
1500
/* inverted bitmask for bitfield et_val{f}[f:0] */
1501
#define rpf_et_valf_mskn 0xffff0000
1502
/* lower bit position of bitfield et_val{f}[f:0] */
1503
#define rpf_et_valf_shift 0
1504
/* width of bitfield et_val{f}[f:0] */
1505
#define rpf_et_valf_width 16
1506
/* default value of bitfield et_val{f}[f:0] */
1507
#define rpf_et_valf_default 0x0
1508

1509
/* rx vl_inner_tpid[f:0] bitfield definitions
1510
 * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]".
1511
 * port="pif_rpf_vl_inner_tpid_i[15:0]"
1512
 */
1513

1514
/* register address for bitfield vl_inner_tpid[f:0] */
1515
#define HW_ATL_RPF_VL_INNER_TPID_ADR 0x00005284
1516
/* bitmask for bitfield vl_inner_tpid[f:0] */
1517
#define HW_ATL_RPF_VL_INNER_TPID_MSK 0x0000ffff
1518
/* inverted bitmask for bitfield vl_inner_tpid[f:0] */
1519
#define HW_ATL_RPF_VL_INNER_TPID_MSKN 0xffff0000
1520
/* lower bit position of bitfield vl_inner_tpid[f:0] */
1521
#define HW_ATL_RPF_VL_INNER_TPID_SHIFT 0
1522
/* width of bitfield vl_inner_tpid[f:0] */
1523
#define HW_ATL_RPF_VL_INNER_TPID_WIDTH 16
1524
/* default value of bitfield vl_inner_tpid[f:0] */
1525
#define HW_ATL_RPF_VL_INNER_TPID_DEFAULT 0x8100
1526

1527
/* rx vl_outer_tpid[f:0] bitfield definitions
1528
 * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]".
1529
 * port="pif_rpf_vl_outer_tpid_i[15:0]"
1530
 */
1531

1532
/* register address for bitfield vl_outer_tpid[f:0] */
1533
#define HW_ATL_RPF_VL_OUTER_TPID_ADR 0x00005284
1534
/* bitmask for bitfield vl_outer_tpid[f:0] */
1535
#define HW_ATL_RPF_VL_OUTER_TPID_MSK 0xffff0000
1536
/* inverted bitmask for bitfield vl_outer_tpid[f:0] */
1537
#define HW_ATL_RPF_VL_OUTER_TPID_MSKN 0x0000ffff
1538
/* lower bit position of bitfield vl_outer_tpid[f:0] */
1539
#define HW_ATL_RPF_VL_OUTER_TPID_SHIFT 16
1540
/* width of bitfield vl_outer_tpid[f:0] */
1541
#define HW_ATL_RPF_VL_OUTER_TPID_WIDTH 16
1542
/* default value of bitfield vl_outer_tpid[f:0] */
1543
#define HW_ATL_RPF_VL_OUTER_TPID_DEFAULT 0x88a8
1544

1545
/* rx vl_promis_mode bitfield definitions
1546
 * preprocessor definitions for the bitfield "vl_promis_mode".
1547
 * port="pif_rpf_vl_promis_mode_i"
1548
 */
1549

1550
/* register address for bitfield vl_promis_mode */
1551
#define HW_ATL_RPF_VL_PROMIS_MODE_ADR 0x00005280
1552
/* bitmask for bitfield vl_promis_mode */
1553
#define HW_ATL_RPF_VL_PROMIS_MODE_MSK 0x00000002
1554
/* inverted bitmask for bitfield vl_promis_mode */
1555
#define HW_ATL_RPF_VL_PROMIS_MODE_MSKN 0xfffffffd
1556
/* lower bit position of bitfield vl_promis_mode */
1557
#define HW_ATL_RPF_VL_PROMIS_MODE_SHIFT 1
1558
/* width of bitfield vl_promis_mode */
1559
#define HW_ATL_RPF_VL_PROMIS_MODE_WIDTH 1
1560
/* default value of bitfield vl_promis_mode */
1561
#define HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT 0x0
1562

1563
/* RX vl_accept_untagged_mode Bitfield Definitions
1564
 * Preprocessor definitions for the bitfield "vl_accept_untagged_mode".
1565
 * PORT="pif_rpf_vl_accept_untagged_i"
1566
 */
1567

1568
/* Register address for bitfield vl_accept_untagged_mode */
1569
#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR 0x00005280
1570
/* Bitmask for bitfield vl_accept_untagged_mode */
1571
#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK 0x00000004
1572
/* Inverted bitmask for bitfield vl_accept_untagged_mode */
1573
#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN 0xFFFFFFFB
1574
/* Lower bit position of bitfield vl_accept_untagged_mode */
1575
#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT 2
1576
/* Width of bitfield vl_accept_untagged_mode */
1577
#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH 1
1578
/* Default value of bitfield vl_accept_untagged_mode */
1579
#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT 0x0
1580

1581
/* rX vl_untagged_act[2:0] Bitfield Definitions
1582
 * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]".
1583
 * PORT="pif_rpf_vl_untagged_act_i[2:0]"
1584
 */
1585

1586
/* Register address for bitfield vl_untagged_act[2:0] */
1587
#define HW_ATL_RPF_VL_UNTAGGED_ACT_ADR 0x00005280
1588
/* Bitmask for bitfield vl_untagged_act[2:0] */
1589
#define HW_ATL_RPF_VL_UNTAGGED_ACT_MSK 0x00000038
1590
/* Inverted bitmask for bitfield vl_untagged_act[2:0] */
1591
#define HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN 0xFFFFFFC7
1592
/* Lower bit position of bitfield vl_untagged_act[2:0] */
1593
#define HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT 3
1594
/* Width of bitfield vl_untagged_act[2:0] */
1595
#define HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH 3
1596
/* Default value of bitfield vl_untagged_act[2:0] */
1597
#define HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT 0x0
1598

1599
/* RX vl_en{F} Bitfield Definitions
1600
 * Preprocessor definitions for the bitfield "vl_en{F}".
1601
 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1602
 * PORT="pif_rpf_vl_en_i[0]"
1603
 */
1604

1605
/* Register address for bitfield vl_en{F} */
1606
#define HW_ATL_RPF_VL_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1607
/* Bitmask for bitfield vl_en{F} */
1608
#define HW_ATL_RPF_VL_EN_F_MSK 0x80000000
1609
/* Inverted bitmask for bitfield vl_en{F} */
1610
#define HW_ATL_RPF_VL_EN_F_MSKN 0x7FFFFFFF
1611
/* Lower bit position of bitfield vl_en{F} */
1612
#define HW_ATL_RPF_VL_EN_F_SHIFT 31
1613
/* Width of bitfield vl_en{F} */
1614
#define HW_ATL_RPF_VL_EN_F_WIDTH 1
1615
/* Default value of bitfield vl_en{F} */
1616
#define HW_ATL_RPF_VL_EN_F_DEFAULT 0x0
1617

1618
/* RX vl_act{F}[2:0] Bitfield Definitions
1619
 * Preprocessor definitions for the bitfield "vl_act{F}[2:0]".
1620
 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1621
 * PORT="pif_rpf_vl_act0_i[2:0]"
1622
 */
1623

1624
/* Register address for bitfield vl_act{F}[2:0] */
1625
#define HW_ATL_RPF_VL_ACT_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1626
/* Bitmask for bitfield vl_act{F}[2:0] */
1627
#define HW_ATL_RPF_VL_ACT_F_MSK 0x00070000
1628
/* Inverted bitmask for bitfield vl_act{F}[2:0] */
1629
#define HW_ATL_RPF_VL_ACT_F_MSKN 0xFFF8FFFF
1630
/* Lower bit position of bitfield vl_act{F}[2:0] */
1631
#define HW_ATL_RPF_VL_ACT_F_SHIFT 16
1632
/* Width of bitfield vl_act{F}[2:0] */
1633
#define HW_ATL_RPF_VL_ACT_F_WIDTH 3
1634
/* Default value of bitfield vl_act{F}[2:0] */
1635
#define HW_ATL_RPF_VL_ACT_F_DEFAULT 0x0
1636

1637
/* RX vl_id{F}[B:0] Bitfield Definitions
1638
 * Preprocessor definitions for the bitfield "vl_id{F}[B:0]".
1639
 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1640
 * PORT="pif_rpf_vl_id0_i[11:0]"
1641
 */
1642

1643
/* Register address for bitfield vl_id{F}[B:0] */
1644
#define HW_ATL_RPF_VL_ID_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1645
/* Bitmask for bitfield vl_id{F}[B:0] */
1646
#define HW_ATL_RPF_VL_ID_F_MSK 0x00000FFF
1647
/* Inverted bitmask for bitfield vl_id{F}[B:0] */
1648
#define HW_ATL_RPF_VL_ID_F_MSKN 0xFFFFF000
1649
/* Lower bit position of bitfield vl_id{F}[B:0] */
1650
#define HW_ATL_RPF_VL_ID_F_SHIFT 0
1651
/* Width of bitfield vl_id{F}[B:0] */
1652
#define HW_ATL_RPF_VL_ID_F_WIDTH 12
1653
/* Default value of bitfield vl_id{F}[B:0] */
1654
#define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0
1655

1656
/* RX vl_rxq_en{F} Bitfield Definitions
1657
 * Preprocessor definitions for the bitfield "vl_rxq{F}".
1658
 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1659
 * PORT="pif_rpf_vl_rxq_en_i"
1660
 */
1661

1662
/* Register address for bitfield vl_rxq_en{F} */
1663
#define HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1664
/* Bitmask for bitfield vl_rxq_en{F} */
1665
#define HW_ATL_RPF_VL_RXQ_EN_F_MSK 0x10000000
1666
/* Inverted bitmask for bitfield vl_rxq_en{F}[ */
1667
#define HW_ATL_RPF_VL_RXQ_EN_F_MSKN 0xEFFFFFFF
1668
/* Lower bit position of bitfield vl_rxq_en{F} */
1669
#define HW_ATL_RPF_VL_RXQ_EN_F_SHIFT 28
1670
/* Width of bitfield vl_rxq_en{F} */
1671
#define HW_ATL_RPF_VL_RXQ_EN_F_WIDTH 1
1672
/* Default value of bitfield vl_rxq_en{F} */
1673
#define HW_ATL_RPF_VL_RXQ_EN_F_DEFAULT 0x0
1674

1675
/* RX vl_rxq{F}[4:0] Bitfield Definitions
1676
 * Preprocessor definitions for the bitfield "vl_rxq{F}[4:0]".
1677
 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1678
 * PORT="pif_rpf_vl_rxq0_i[4:0]"
1679
 */
1680

1681
/* Register address for bitfield vl_rxq{F}[4:0] */
1682
#define HW_ATL_RPF_VL_RXQ_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1683
/* Bitmask for bitfield vl_rxq{F}[4:0] */
1684
#define HW_ATL_RPF_VL_RXQ_F_MSK 0x01F00000
1685
/* Inverted bitmask for bitfield vl_rxq{F}[4:0] */
1686
#define HW_ATL_RPF_VL_RXQ_F_MSKN 0xFE0FFFFF
1687
/* Lower bit position of bitfield vl_rxq{F}[4:0] */
1688
#define HW_ATL_RPF_VL_RXQ_F_SHIFT 20
1689
/* Width of bitfield vl_rxw{F}[4:0] */
1690
#define HW_ATL_RPF_VL_RXQ_F_WIDTH 5
1691
/* Default value of bitfield vl_rxq{F}[4:0] */
1692
#define HW_ATL_RPF_VL_RXQ_F_DEFAULT 0x0
1693

1694
/* rx et_en{f} bitfield definitions
1695
 * preprocessor definitions for the bitfield "et_en{f}".
1696
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1697
 * port="pif_rpf_et_en_i[0]"
1698
 */
1699

1700
/* register address for bitfield et_en{f} */
1701
#define HW_ATL_RPF_ET_ENF_ADR(filter) (0x00005300 + (filter) * 0x4)
1702
/* bitmask for bitfield et_en{f} */
1703
#define HW_ATL_RPF_ET_ENF_MSK 0x80000000
1704
/* inverted bitmask for bitfield et_en{f} */
1705
#define HW_ATL_RPF_ET_ENF_MSKN 0x7fffffff
1706
/* lower bit position of bitfield et_en{f} */
1707
#define HW_ATL_RPF_ET_ENF_SHIFT 31
1708
/* width of bitfield et_en{f} */
1709
#define HW_ATL_RPF_ET_ENF_WIDTH 1
1710
/* default value of bitfield et_en{f} */
1711
#define HW_ATL_RPF_ET_ENF_DEFAULT 0x0
1712

1713
/* rx et_up{f}_en bitfield definitions
1714
 * preprocessor definitions for the bitfield "et_up{f}_en".
1715
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1716
 * port="pif_rpf_et_up_en_i[0]"
1717
 */
1718

1719
/* register address for bitfield et_up{f}_en */
1720
#define HW_ATL_RPF_ET_UPFEN_ADR(filter) (0x00005300 + (filter) * 0x4)
1721
/* bitmask for bitfield et_up{f}_en */
1722
#define HW_ATL_RPF_ET_UPFEN_MSK 0x40000000
1723
/* inverted bitmask for bitfield et_up{f}_en */
1724
#define HW_ATL_RPF_ET_UPFEN_MSKN 0xbfffffff
1725
/* lower bit position of bitfield et_up{f}_en */
1726
#define HW_ATL_RPF_ET_UPFEN_SHIFT 30
1727
/* width of bitfield et_up{f}_en */
1728
#define HW_ATL_RPF_ET_UPFEN_WIDTH 1
1729
/* default value of bitfield et_up{f}_en */
1730
#define HW_ATL_RPF_ET_UPFEN_DEFAULT 0x0
1731

1732
/* rx et_rxq{f}_en bitfield definitions
1733
 * preprocessor definitions for the bitfield "et_rxq{f}_en".
1734
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1735
 * port="pif_rpf_et_rxq_en_i[0]"
1736
 */
1737

1738
/* register address for bitfield et_rxq{f}_en */
1739
#define HW_ATL_RPF_ET_RXQFEN_ADR(filter) (0x00005300 + (filter) * 0x4)
1740
/* bitmask for bitfield et_rxq{f}_en */
1741
#define HW_ATL_RPF_ET_RXQFEN_MSK 0x20000000
1742
/* inverted bitmask for bitfield et_rxq{f}_en */
1743
#define HW_ATL_RPF_ET_RXQFEN_MSKN 0xdfffffff
1744
/* lower bit position of bitfield et_rxq{f}_en */
1745
#define HW_ATL_RPF_ET_RXQFEN_SHIFT 29
1746
/* width of bitfield et_rxq{f}_en */
1747
#define HW_ATL_RPF_ET_RXQFEN_WIDTH 1
1748
/* default value of bitfield et_rxq{f}_en */
1749
#define HW_ATL_RPF_ET_RXQFEN_DEFAULT 0x0
1750

1751
/* rx et_up{f}[2:0] bitfield definitions
1752
 * preprocessor definitions for the bitfield "et_up{f}[2:0]".
1753
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1754
 * port="pif_rpf_et_up0_i[2:0]"
1755
 */
1756

1757
/* register address for bitfield et_up{f}[2:0] */
1758
#define HW_ATL_RPF_ET_UPF_ADR(filter) (0x00005300 + (filter) * 0x4)
1759
/* bitmask for bitfield et_up{f}[2:0] */
1760
#define HW_ATL_RPF_ET_UPF_MSK 0x1c000000
1761
/* inverted bitmask for bitfield et_up{f}[2:0] */
1762
#define HW_ATL_RPF_ET_UPF_MSKN 0xe3ffffff
1763
/* lower bit position of bitfield et_up{f}[2:0] */
1764
#define HW_ATL_RPF_ET_UPF_SHIFT 26
1765
/* width of bitfield et_up{f}[2:0] */
1766
#define HW_ATL_RPF_ET_UPF_WIDTH 3
1767
/* default value of bitfield et_up{f}[2:0] */
1768
#define HW_ATL_RPF_ET_UPF_DEFAULT 0x0
1769

1770
/* rx et_rxq{f}[4:0] bitfield definitions
1771
 * preprocessor definitions for the bitfield "et_rxq{f}[4:0]".
1772
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1773
 * port="pif_rpf_et_rxq0_i[4:0]"
1774
 */
1775

1776
/* register address for bitfield et_rxq{f}[4:0] */
1777
#define HW_ATL_RPF_ET_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4)
1778
/* bitmask for bitfield et_rxq{f}[4:0] */
1779
#define HW_ATL_RPF_ET_RXQF_MSK 0x01f00000
1780
/* inverted bitmask for bitfield et_rxq{f}[4:0] */
1781
#define HW_ATL_RPF_ET_RXQF_MSKN 0xfe0fffff
1782
/* lower bit position of bitfield et_rxq{f}[4:0] */
1783
#define HW_ATL_RPF_ET_RXQF_SHIFT 20
1784
/* width of bitfield et_rxq{f}[4:0] */
1785
#define HW_ATL_RPF_ET_RXQF_WIDTH 5
1786
/* default value of bitfield et_rxq{f}[4:0] */
1787
#define HW_ATL_RPF_ET_RXQF_DEFAULT 0x0
1788

1789
/* rx et_mng_rxq{f} bitfield definitions
1790
 * preprocessor definitions for the bitfield "et_mng_rxq{f}".
1791
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1792
 * port="pif_rpf_et_mng_rxq_i[0]"
1793
 */
1794

1795
/* register address for bitfield et_mng_rxq{f} */
1796
#define HW_ATL_RPF_ET_MNG_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4)
1797
/* bitmask for bitfield et_mng_rxq{f} */
1798
#define HW_ATL_RPF_ET_MNG_RXQF_MSK 0x00080000
1799
/* inverted bitmask for bitfield et_mng_rxq{f} */
1800
#define HW_ATL_RPF_ET_MNG_RXQF_MSKN 0xfff7ffff
1801
/* lower bit position of bitfield et_mng_rxq{f} */
1802
#define HW_ATL_RPF_ET_MNG_RXQF_SHIFT 19
1803
/* width of bitfield et_mng_rxq{f} */
1804
#define HW_ATL_RPF_ET_MNG_RXQF_WIDTH 1
1805
/* default value of bitfield et_mng_rxq{f} */
1806
#define HW_ATL_RPF_ET_MNG_RXQF_DEFAULT 0x0
1807

1808
/* rx et_act{f}[2:0] bitfield definitions
1809
 * preprocessor definitions for the bitfield "et_act{f}[2:0]".
1810
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1811
 * port="pif_rpf_et_act0_i[2:0]"
1812
 */
1813

1814
/* register address for bitfield et_act{f}[2:0] */
1815
#define HW_ATL_RPF_ET_ACTF_ADR(filter) (0x00005300 + (filter) * 0x4)
1816
/* bitmask for bitfield et_act{f}[2:0] */
1817
#define HW_ATL_RPF_ET_ACTF_MSK 0x00070000
1818
/* inverted bitmask for bitfield et_act{f}[2:0] */
1819
#define HW_ATL_RPF_ET_ACTF_MSKN 0xfff8ffff
1820
/* lower bit position of bitfield et_act{f}[2:0] */
1821
#define HW_ATL_RPF_ET_ACTF_SHIFT 16
1822
/* width of bitfield et_act{f}[2:0] */
1823
#define HW_ATL_RPF_ET_ACTF_WIDTH 3
1824
/* default value of bitfield et_act{f}[2:0] */
1825
#define HW_ATL_RPF_ET_ACTF_DEFAULT 0x0
1826

1827
/* rx et_val{f}[f:0] bitfield definitions
1828
 * preprocessor definitions for the bitfield "et_val{f}[f:0]".
1829
 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1830
 * port="pif_rpf_et_val0_i[15:0]"
1831
 */
1832

1833
/* register address for bitfield et_val{f}[f:0] */
1834
#define HW_ATL_RPF_ET_VALF_ADR(filter) (0x00005300 + (filter) * 0x4)
1835
/* bitmask for bitfield et_val{f}[f:0] */
1836
#define HW_ATL_RPF_ET_VALF_MSK 0x0000ffff
1837
/* inverted bitmask for bitfield et_val{f}[f:0] */
1838
#define HW_ATL_RPF_ET_VALF_MSKN 0xffff0000
1839
/* lower bit position of bitfield et_val{f}[f:0] */
1840
#define HW_ATL_RPF_ET_VALF_SHIFT 0
1841
/* width of bitfield et_val{f}[f:0] */
1842
#define HW_ATL_RPF_ET_VALF_WIDTH 16
1843
/* default value of bitfield et_val{f}[f:0] */
1844
#define HW_ATL_RPF_ET_VALF_DEFAULT 0x0
1845

1846
/* RX l3_l4_en{F} Bitfield Definitions
1847
 * Preprocessor definitions for the bitfield "l3_l4_en{F}".
1848
 * Parameter: filter {F} | stride size 0x4 | range [0, 7]
1849
 * PORT="pif_rpf_l3_l4_en_i[0]"
1850
 */
1851

1852
/* Register address for bitfield l3_l4_en{F} */
1853
#define HW_ATL_RPF_L3_L4_ENF_ADR(filter) (0x00005380u + (filter) * 0x4)
1854
/* Bitmask for bitfield l3_l4_en{F} */
1855
#define HW_ATL_RPF_L3_L4_ENF_MSK 0x80000000u
1856
/* Inverted bitmask for bitfield l3_l4_en{F} */
1857
#define HW_ATL_RPF_L3_L4_ENF_MSKN 0x7FFFFFFFu
1858
/* Lower bit position of bitfield l3_l4_en{F} */
1859
#define HW_ATL_RPF_L3_L4_ENF_SHIFT 31
1860
/* Width of bitfield l3_l4_en{F} */
1861
#define HW_ATL_RPF_L3_L4_ENF_WIDTH 1
1862
/* Default value of bitfield l3_l4_en{F} */
1863
#define HW_ATL_RPF_L3_L4_ENF_DEFAULT 0x0
1864

1865
/* RX l3_v6_en{F} Bitfield Definitions
1866
 * Preprocessor definitions for the bitfield "l3_v6_en{F}".
1867
 * Parameter: filter {F} | stride size 0x4 | range [0, 7]
1868
 * PORT="pif_rpf_l3_v6_en_i[0]"
1869
 */
1870
/* Register address for bitfield l3_v6_en{F} */
1871
#define HW_ATL_RPF_L3_V6_ENF_ADR(filter) (0x00005380u + (filter) * 0x4)
1872
/* Bitmask for bitfield l3_v6_en{F} */
1873
#define HW_ATL_RPF_L3_V6_ENF_MSK 0x40000000u
1874
/* Inverted bitmask for bitfield l3_v6_en{F} */
1875
#define HW_ATL_RPF_L3_V6_ENF_MSKN 0xBFFFFFFFu
1876
/* Lower bit position of bitfield l3_v6_en{F} */
1877
#define HW_ATL_RPF_L3_V6_ENF_SHIFT 30
1878
/* Width of bitfield l3_v6_en{F} */
1879
#define HW_ATL_RPF_L3_V6_ENF_WIDTH 1
1880
/* Default value of bitfield l3_v6_en{F} */
1881
#define HW_ATL_RPF_L3_V6_ENF_DEFAULT 0x0
1882

1883
/* RX l3_sa{F}_en Bitfield Definitions
1884
 * Preprocessor definitions for the bitfield "l3_sa{F}_en".
1885
 * Parameter: filter {F} | stride size 0x4 | range [0, 7]
1886
 * PORT="pif_rpf_l3_sa_en_i[0]"
1887
 */
1888

1889
/* Register address for bitfield l3_sa{F}_en */
1890
#define HW_ATL_RPF_L3_SAF_EN_ADR(filter) (0x00005380u + (filter) * 0x4)
1891
/* Bitmask for bitfield l3_sa{F}_en */
1892
#define HW_ATL_RPF_L3_SAF_EN_MSK 0x20000000u
1893
/* Inverted bitmask for bitfield l3_sa{F}_en */
1894
#define HW_ATL_RPF_L3_SAF_EN_MSKN 0xDFFFFFFFu
1895
/* Lower bit position of bitfield l3_sa{F}_en */
1896
#define HW_ATL_RPF_L3_SAF_EN_SHIFT 29
1897
/* Width of bitfield l3_sa{F}_en */
1898
#define HW_ATL_RPF_L3_SAF_EN_WIDTH 1
1899
/* Default value of bitfield l3_sa{F}_en */
1900
#define HW_ATL_RPF_L3_SAF_EN_DEFAULT 0x0
1901

1902
/* RX l3_da{F}_en Bitfield Definitions
1903
 * Preprocessor definitions for the bitfield "l3_da{F}_en".
1904
 * Parameter: filter {F} | stride size 0x4 | range [0, 7]
1905
 * PORT="pif_rpf_l3_da_en_i[0]"
1906
 */
1907

1908
/* Register address for bitfield l3_da{F}_en */
1909
#define HW_ATL_RPF_L3_DAF_EN_ADR(filter) (0x00005380u + (filter) * 0x4)
1910
/* Bitmask for bitfield l3_da{F}_en */
1911
#define HW_ATL_RPF_L3_DAF_EN_MSK 0x10000000u
1912
/* Inverted bitmask for bitfield l3_da{F}_en */
1913
#define HW_ATL_RPF_L3_DAF_EN_MSKN 0xEFFFFFFFu
1914
/* Lower bit position of bitfield l3_da{F}_en */
1915
#define HW_ATL_RPF_L3_DAF_EN_SHIFT 28
1916
/* Width of bitfield l3_da{F}_en */
1917
#define HW_ATL_RPF_L3_DAF_EN_WIDTH 1
1918
/* Default value of bitfield l3_da{F}_en */
1919
#define HW_ATL_RPF_L3_DAF_EN_DEFAULT 0x0
1920

1921
/* RX l4_sp{F}_en Bitfield Definitions
1922
 * Preprocessor definitions for the bitfield "l4_sp{F}_en".
1923
 * Parameter: filter {F} | stride size 0x4 | range [0, 7]
1924
 * PORT="pif_rpf_l4_sp_en_i[0]"
1925
 */
1926

1927
/* Register address for bitfield l4_sp{F}_en */
1928
#define HW_ATL_RPF_L4_SPF_EN_ADR(filter) (0x00005380u + (filter) * 0x4)
1929
/* Bitmask for bitfield l4_sp{F}_en */
1930
#define HW_ATL_RPF_L4_SPF_EN_MSK 0x08000000u
1931
/* Inverted bitmask for bitfield l4_sp{F}_en */
1932
#define HW_ATL_RPF_L4_SPF_EN_MSKN 0xF7FFFFFFu
1933
/* Lower bit position of bitfield l4_sp{F}_en */
1934
#define HW_ATL_RPF_L4_SPF_EN_SHIFT 27
1935
/* Width of bitfield l4_sp{F}_en */
1936
#define HW_ATL_RPF_L4_SPF_EN_WIDTH 1
1937
/* Default value of bitfield l4_sp{F}_en */
1938
#define HW_ATL_RPF_L4_SPF_EN_DEFAULT 0x0
1939

1940
/* RX l4_dp{F}_en Bitfield Definitions
1941
 * Preprocessor definitions for the bitfield "l4_dp{F}_en".
1942
 * Parameter: filter {F} | stride size 0x4 | range [0, 7]
1943
 * PORT="pif_rpf_l4_dp_en_i[0]"
1944
 */
1945

1946
/* Register address for bitfield l4_dp{F}_en */
1947
#define HW_ATL_RPF_L4_DPF_EN_ADR(filter) (0x00005380u + (filter) * 0x4)
1948
/* Bitmask for bitfield l4_dp{F}_en */
1949
#define HW_ATL_RPF_L4_DPF_EN_MSK 0x04000000u
1950
/* Inverted bitmask for bitfield l4_dp{F}_en */
1951
#define HW_ATL_RPF_L4_DPF_EN_MSKN 0xFBFFFFFFu
1952
/* Lower bit position of bitfield l4_dp{F}_en */
1953
#define HW_ATL_RPF_L4_DPF_EN_SHIFT 26
1954
/* Width of bitfield l4_dp{F}_en */
1955
#define HW_ATL_RPF_L4_DPF_EN_WIDTH 1
1956
/* Default value of bitfield l4_dp{F}_en */
1957
#define HW_ATL_RPF_L4_DPF_EN_DEFAULT 0x0
1958

1959
/* RX l4_prot{F}_en Bitfield Definitions
1960
 * Preprocessor definitions for the bitfield "l4_prot{F}_en".
1961
 * Parameter: filter {F} | stride size 0x4 | range [0, 7]
1962
 * PORT="pif_rpf_l4_prot_en_i[0]"
1963
 */
1964

1965
/* Register address for bitfield l4_prot{F}_en */
1966
#define HW_ATL_RPF_L4_PROTF_EN_ADR(filter) (0x00005380u + (filter) * 0x4)
1967
/* Bitmask for bitfield l4_prot{F}_en */
1968
#define HW_ATL_RPF_L4_PROTF_EN_MSK 0x02000000u
1969
/* Inverted bitmask for bitfield l4_prot{F}_en */
1970
#define HW_ATL_RPF_L4_PROTF_EN_MSKN 0xFDFFFFFFu
1971
/* Lower bit position of bitfield l4_prot{F}_en */
1972
#define HW_ATL_RPF_L4_PROTF_EN_SHIFT 25
1973
/* Width of bitfield l4_prot{F}_en */
1974
#define HW_ATL_RPF_L4_PROTF_EN_WIDTH 1
1975
/* Default value of bitfield l4_prot{F}_en */
1976
#define HW_ATL_RPF_L4_PROTF_EN_DEFAULT 0x0
1977

1978
/* RX l3_arp{F}_en Bitfield Definitions
1979
 * Preprocessor definitions for the bitfield "l3_arp{F}_en".
1980
 * Parameter: filter {F} | stride size 0x4 | range [0, 7]
1981
 * PORT="pif_rpf_l3_arp_en_i[0]"
1982
 */
1983

1984
/* Register address for bitfield l3_arp{F}_en */
1985
#define HW_ATL_RPF_L3_ARPF_EN_ADR(filter) (0x00005380u + (filter) * 0x4)
1986
/* Bitmask for bitfield l3_arp{F}_en */
1987
#define HW_ATL_RPF_L3_ARPF_EN_MSK 0x01000000u
1988
/* Inverted bitmask for bitfield l3_arp{F}_en */
1989
#define HW_ATL_RPF_L3_ARPF_EN_MSKN 0xFEFFFFFFu
1990
/* Lower bit position of bitfield l3_arp{F}_en */
1991
#define HW_ATL_RPF_L3_ARPF_EN_SHIFT 24
1992
/* Width of bitfield l3_arp{F}_en */
1993
#define HW_ATL_RPF_L3_ARPF_EN_WIDTH 1
1994
/* Default value of bitfield l3_arp{F}_en */
1995
#define HW_ATL_RPF_L3_ARPF_EN_DEFAULT 0x0
1996

1997
/* RX l3_l4_rxq{F}_en Bitfield Definitions
1998
 * Preprocessor definitions for the bitfield "l3_l4_rxq{F}_en".
1999
 * Parameter: filter {F} | stride size 0x4 | range [0, 7]
2000
 * PORT="pif_rpf_l3_l4_rxq_en_i[0]"
2001
 */
2002

2003
/* Register address for bitfield l3_l4_RXq{F}_en */
2004
#define HW_ATL_RPF_L3_L4_RXQF_EN_ADR(filter) (0x00005380u + (filter) * 0x4)
2005
/* Bitmask for bitfield l3_l4_RXq{F}_en */
2006
#define HW_ATL_RPF_L3_L4_RXQF_EN_MSK 0x00800000u
2007
/* Inverted bitmask for bitfield l3_l4_RXq{F}_en */
2008
#define HW_ATL_RPF_L3_L4_RXQF_EN_MSKN 0xFF7FFFFFu
2009
/* Lower bit position of bitfield l3_l4_RXq{F}_en */
2010
#define HW_ATL_RPF_L3_L4_RXQF_EN_SHIFT 23
2011
/* Width of bitfield l3_l4_RXq{F}_en */
2012
#define HW_ATL_RPF_L3_L4_RXQF_EN_WIDTH 1
2013
/* Default value of bitfield l3_l4_RXq{F}_en */
2014
#define HW_ATL_RPF_L3_L4_RXQF_EN_DEFAULT 0x0
2015

2016
/* RX l3_l4_mng_RXq{F} Bitfield Definitions
2017
 * Preprocessor definitions for the bitfield "l3_l4_mng_RXq{F}".
2018
 * Parameter: filter {F} | stride size 0x4 | range [0, 7]
2019
 * PORT="pif_rpf_l3_l4_mng_rxq_i[0]"
2020
 */
2021

2022
/* Register address for bitfield l3_l4_mng_rxq{F} */
2023
#define HW_ATL_RPF_L3_L4_MNG_RXQF_ADR(filter) (0x00005380u + (filter) * 0x4)
2024
/* Bitmask for bitfield l3_l4_mng_rxq{F} */
2025
#define HW_ATL_RPF_L3_L4_MNG_RXQF_MSK 0x00400000u
2026
/* Inverted bitmask for bitfield l3_l4_mng_rxq{F} */
2027
#define HW_ATL_RPF_L3_L4_MNG_RXQF_MSKN 0xFFBFFFFFu
2028
/* Lower bit position of bitfield l3_l4_mng_rxq{F} */
2029
#define HW_ATL_RPF_L3_L4_MNG_RXQF_SHIFT 22
2030
/* Width of bitfield l3_l4_mng_rxq{F} */
2031
#define HW_ATL_RPF_L3_L4_MNG_RXQF_WIDTH 1
2032
/* Default value of bitfield l3_l4_mng_rxq{F} */
2033
#define HW_ATL_RPF_L3_L4_MNG_RXQF_DEFAULT 0x0
2034

2035
/* RX l3_l4_act{F}[2:0] Bitfield Definitions
2036
 * Preprocessor definitions for the bitfield "l3_l4_act{F}[2:0]".
2037
 * Parameter: filter {F} | stride size 0x4 | range [0, 7]
2038
 * PORT="pif_rpf_l3_l4_act0_i[2:0]"
2039
 */
2040

2041
/* Register address for bitfield l3_l4_act{F}[2:0] */
2042
#define HW_ATL_RPF_L3_L4_ACTF_ADR(filter) (0x00005380u + (filter) * 0x4)
2043
/* Bitmask for bitfield l3_l4_act{F}[2:0] */
2044
#define HW_ATL_RPF_L3_L4_ACTF_MSK 0x00070000u
2045
/* Inverted bitmask for bitfield l3_l4_act{F}[2:0] */
2046
#define HW_ATL_RPF_L3_L4_ACTF_MSKN 0xFFF8FFFFu
2047
/* Lower bit position of bitfield l3_l4_act{F}[2:0] */
2048
#define HW_ATL_RPF_L3_L4_ACTF_SHIFT 16
2049
/* Width of bitfield l3_l4_act{F}[2:0] */
2050
#define HW_ATL_RPF_L3_L4_ACTF_WIDTH 3
2051
/* Default value of bitfield l3_l4_act{F}[2:0] */
2052
#define HW_ATL_RPF_L3_L4_ACTF_DEFAULT 0x0
2053

2054
/* RX l3_l4_rxq{F}[4:0] Bitfield Definitions
2055
 * Preprocessor definitions for the bitfield "l3_l4_rxq{F}[4:0]".
2056
 * Parameter: filter {F} | stride size 0x4 | range [0, 7]
2057
 * PORT="pif_rpf_l3_l4_rxq0_i[4:0]"
2058
 */
2059

2060
/* Register address for bitfield l3_l4_rxq{F}[4:0] */
2061
#define HW_ATL_RPF_L3_L4_RXQF_ADR(filter) (0x00005380u + (filter) * 0x4)
2062
/* Bitmask for bitfield l3_l4_rxq{F}[4:0] */
2063
#define HW_ATL_RPF_L3_L4_RXQF_MSK 0x00001F00u
2064
/* Inverted bitmask for bitfield l3_l4_rxq{F}[4:0] */
2065
#define HW_ATL_RPF_L3_L4_RXQF_MSKN 0xFFFFE0FFu
2066
/* Lower bit position of bitfield l3_l4_rxq{F}[4:0] */
2067
#define HW_ATL_RPF_L3_L4_RXQF_SHIFT 8
2068
/* Width of bitfield l3_l4_rxq{F}[4:0] */
2069
#define HW_ATL_RPF_L3_L4_RXQF_WIDTH 5
2070
/* Default value of bitfield l3_l4_rxq{F}[4:0] */
2071
#define HW_ATL_RPF_L3_L4_RXQF_DEFAULT 0x0
2072

2073
/* RX l4_prot{F}[2:0] Bitfield Definitions
2074
 * Preprocessor definitions for the bitfield "l4_prot{F}[2:0]".
2075
 * Parameter: filter {F} | stride size 0x4 | range [0, 7]
2076
 * PORT="pif_rpf_l4_prot0_i[2:0]"
2077
 */
2078

2079
/* Register address for bitfield l4_prot{F}[2:0] */
2080
#define HW_ATL_RPF_L4_PROTF_ADR(filter) (0x00005380u + (filter) * 0x4)
2081
/* Bitmask for bitfield l4_prot{F}[2:0] */
2082
#define HW_ATL_RPF_L4_PROTF_MSK 0x00000007u
2083
/* Inverted bitmask for bitfield l4_prot{F}[2:0] */
2084
#define HW_ATL_RPF_L4_PROTF_MSKN 0xFFFFFFF8u
2085
/* Lower bit position of bitfield l4_prot{F}[2:0] */
2086
#define HW_ATL_RPF_L4_PROTF_SHIFT 0
2087
/* Width of bitfield l4_prot{F}[2:0] */
2088
#define HW_ATL_RPF_L4_PROTF_WIDTH 3
2089
/* Default value of bitfield l4_prot{F}[2:0] */
2090
#define HW_ATL_RPF_L4_PROTF_DEFAULT 0x0
2091

2092
/* RX l4_sp{D}[F:0] Bitfield Definitions
2093
 * Preprocessor definitions for the bitfield "l4_sp{D}[F:0]".
2094
 * Parameter: srcport {D} | stride size 0x4 | range [0, 7]
2095
 * PORT="pif_rpf_l4_sp0_i[15:0]"
2096
 */
2097

2098
/* Register address for bitfield l4_sp{D}[F:0] */
2099
#define HW_ATL_RPF_L4_SPD_ADR(srcport) (0x00005400u + (srcport) * 0x4)
2100
/* Bitmask for bitfield l4_sp{D}[F:0] */
2101
#define HW_ATL_RPF_L4_SPD_MSK 0x0000FFFFu
2102
/* Inverted bitmask for bitfield l4_sp{D}[F:0] */
2103
#define HW_ATL_RPF_L4_SPD_MSKN 0xFFFF0000u
2104
/* Lower bit position of bitfield l4_sp{D}[F:0] */
2105
#define HW_ATL_RPF_L4_SPD_SHIFT 0
2106
/* Width of bitfield l4_sp{D}[F:0] */
2107
#define HW_ATL_RPF_L4_SPD_WIDTH 16
2108
/* Default value of bitfield l4_sp{D}[F:0] */
2109
#define HW_ATL_RPF_L4_SPD_DEFAULT 0x0
2110

2111
/* RX l4_dp{D}[F:0] Bitfield Definitions
2112
 * Preprocessor definitions for the bitfield "l4_dp{D}[F:0]".
2113
 * Parameter: destport {D} | stride size 0x4 | range [0, 7]
2114
 * PORT="pif_rpf_l4_dp0_i[15:0]"
2115
 */
2116

2117
/* Register address for bitfield l4_dp{D}[F:0] */
2118
#define HW_ATL_RPF_L4_DPD_ADR(destport) (0x00005420u + (destport) * 0x4)
2119
/* Bitmask for bitfield l4_dp{D}[F:0] */
2120
#define HW_ATL_RPF_L4_DPD_MSK 0x0000FFFFu
2121
/* Inverted bitmask for bitfield l4_dp{D}[F:0] */
2122
#define HW_ATL_RPF_L4_DPD_MSKN 0xFFFF0000u
2123
/* Lower bit position of bitfield l4_dp{D}[F:0] */
2124
#define HW_ATL_RPF_L4_DPD_SHIFT 0
2125
/* Width of bitfield l4_dp{D}[F:0] */
2126
#define HW_ATL_RPF_L4_DPD_WIDTH 16
2127
/* Default value of bitfield l4_dp{D}[F:0] */
2128
#define HW_ATL_RPF_L4_DPD_DEFAULT 0x0
2129

2130
/* rx ipv4_chk_en bitfield definitions
2131
 * preprocessor definitions for the bitfield "ipv4_chk_en".
2132
 * port="pif_rpo_ipv4_chk_en_i"
2133
 */
2134

2135
/* register address for bitfield ipv4_chk_en */
2136
#define rpo_ipv4chk_en_adr 0x00005580
2137
/* bitmask for bitfield ipv4_chk_en */
2138
#define rpo_ipv4chk_en_msk 0x00000002
2139
/* inverted bitmask for bitfield ipv4_chk_en */
2140
#define rpo_ipv4chk_en_mskn 0xfffffffd
2141
/* lower bit position of bitfield ipv4_chk_en */
2142
#define rpo_ipv4chk_en_shift 1
2143
/* width of bitfield ipv4_chk_en */
2144
#define rpo_ipv4chk_en_width 1
2145
/* default value of bitfield ipv4_chk_en */
2146
#define rpo_ipv4chk_en_default 0x0
2147

2148
/* rx desc{d}_vl_strip bitfield definitions
2149
 * preprocessor definitions for the bitfield "desc{d}_vl_strip".
2150
 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
2151
 * port="pif_rpo_desc_vl_strip_i[0]"
2152
 */
2153

2154
/* register address for bitfield desc{d}_vl_strip */
2155
#define rpo_descdvl_strip_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
2156
/* bitmask for bitfield desc{d}_vl_strip */
2157
#define rpo_descdvl_strip_msk 0x20000000
2158
/* inverted bitmask for bitfield desc{d}_vl_strip */
2159
#define rpo_descdvl_strip_mskn 0xdfffffff
2160
/* lower bit position of bitfield desc{d}_vl_strip */
2161
#define rpo_descdvl_strip_shift 29
2162
/* width of bitfield desc{d}_vl_strip */
2163
#define rpo_descdvl_strip_width 1
2164
/* default value of bitfield desc{d}_vl_strip */
2165
#define rpo_descdvl_strip_default 0x0
2166

2167
/* rx l4_chk_en bitfield definitions
2168
 * preprocessor definitions for the bitfield "l4_chk_en".
2169
 * port="pif_rpo_l4_chk_en_i"
2170
 */
2171

2172
/* register address for bitfield l4_chk_en */
2173
#define rpol4chk_en_adr 0x00005580
2174
/* bitmask for bitfield l4_chk_en */
2175
#define rpol4chk_en_msk 0x00000001
2176
/* inverted bitmask for bitfield l4_chk_en */
2177
#define rpol4chk_en_mskn 0xfffffffe
2178
/* lower bit position of bitfield l4_chk_en */
2179
#define rpol4chk_en_shift 0
2180
/* width of bitfield l4_chk_en */
2181
#define rpol4chk_en_width 1
2182
/* default value of bitfield l4_chk_en */
2183
#define rpol4chk_en_default 0x0
2184

2185
/* rx reg_res_dsbl bitfield definitions
2186
 * preprocessor definitions for the bitfield "reg_res_dsbl".
2187
 * port="pif_rx_reg_res_dsbl_i"
2188
 */
2189

2190
/* register address for bitfield reg_res_dsbl */
2191
#define rx_reg_res_dsbl_adr 0x00005000
2192
/* bitmask for bitfield reg_res_dsbl */
2193
#define rx_reg_res_dsbl_msk 0x20000000
2194
/* inverted bitmask for bitfield reg_res_dsbl */
2195
#define rx_reg_res_dsbl_mskn 0xdfffffff
2196
/* lower bit position of bitfield reg_res_dsbl */
2197
#define rx_reg_res_dsbl_shift 29
2198
/* width of bitfield reg_res_dsbl */
2199
#define rx_reg_res_dsbl_width 1
2200
/* default value of bitfield reg_res_dsbl */
2201
#define rx_reg_res_dsbl_default 0x1
2202

2203
/* tx dca{d}_cpuid[7:0] bitfield definitions
2204
 * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]".
2205
 * parameter: dca {d} | stride size 0x4 | range [0, 31]
2206
 * port="pif_tdm_dca0_cpuid_i[7:0]"
2207
 */
2208

2209
/* register address for bitfield dca{d}_cpuid[7:0] */
2210
#define tdm_dcadcpuid_adr(dca) (0x00008400 + (dca) * 0x4)
2211
/* bitmask for bitfield dca{d}_cpuid[7:0] */
2212
#define tdm_dcadcpuid_msk 0x000000ff
2213
/* inverted bitmask for bitfield dca{d}_cpuid[7:0] */
2214
#define tdm_dcadcpuid_mskn 0xffffff00
2215
/* lower bit position of bitfield dca{d}_cpuid[7:0] */
2216
#define tdm_dcadcpuid_shift 0
2217
/* width of bitfield dca{d}_cpuid[7:0] */
2218
#define tdm_dcadcpuid_width 8
2219
/* default value of bitfield dca{d}_cpuid[7:0] */
2220
#define tdm_dcadcpuid_default 0x0
2221

2222
/* tx lso_en[1f:0] bitfield definitions
2223
 * preprocessor definitions for the bitfield "lso_en[1f:0]".
2224
 * port="pif_tdm_lso_en_i[31:0]"
2225
 */
2226

2227
/* register address for bitfield lso_en[1f:0] */
2228
#define tdm_lso_en_adr 0x00007810
2229
/* bitmask for bitfield lso_en[1f:0] */
2230
#define tdm_lso_en_msk 0xffffffff
2231
/* inverted bitmask for bitfield lso_en[1f:0] */
2232
#define tdm_lso_en_mskn 0x00000000
2233
/* lower bit position of bitfield lso_en[1f:0] */
2234
#define tdm_lso_en_shift 0
2235
/* width of bitfield lso_en[1f:0] */
2236
#define tdm_lso_en_width 32
2237
/* default value of bitfield lso_en[1f:0] */
2238
#define tdm_lso_en_default 0x0
2239

2240
/* tx dca_en bitfield definitions
2241
 * preprocessor definitions for the bitfield "dca_en".
2242
 * port="pif_tdm_dca_en_i"
2243
 */
2244

2245
/* register address for bitfield dca_en */
2246
#define tdm_dca_en_adr 0x00008480
2247
/* bitmask for bitfield dca_en */
2248
#define tdm_dca_en_msk 0x80000000
2249
/* inverted bitmask for bitfield dca_en */
2250
#define tdm_dca_en_mskn 0x7fffffff
2251
/* lower bit position of bitfield dca_en */
2252
#define tdm_dca_en_shift 31
2253
/* width of bitfield dca_en */
2254
#define tdm_dca_en_width 1
2255
/* default value of bitfield dca_en */
2256
#define tdm_dca_en_default 0x1
2257

2258
/* tx dca_mode[3:0] bitfield definitions
2259
 * preprocessor definitions for the bitfield "dca_mode[3:0]".
2260
 * port="pif_tdm_dca_mode_i[3:0]"
2261
 */
2262

2263
/* register address for bitfield dca_mode[3:0] */
2264
#define tdm_dca_mode_adr 0x00008480
2265
/* bitmask for bitfield dca_mode[3:0] */
2266
#define tdm_dca_mode_msk 0x0000000f
2267
/* inverted bitmask for bitfield dca_mode[3:0] */
2268
#define tdm_dca_mode_mskn 0xfffffff0
2269
/* lower bit position of bitfield dca_mode[3:0] */
2270
#define tdm_dca_mode_shift 0
2271
/* width of bitfield dca_mode[3:0] */
2272
#define tdm_dca_mode_width 4
2273
/* default value of bitfield dca_mode[3:0] */
2274
#define tdm_dca_mode_default 0x0
2275

2276
/* tx dca{d}_desc_en bitfield definitions
2277
 * preprocessor definitions for the bitfield "dca{d}_desc_en".
2278
 * parameter: dca {d} | stride size 0x4 | range [0, 31]
2279
 * port="pif_tdm_dca_desc_en_i[0]"
2280
 */
2281

2282
/* register address for bitfield dca{d}_desc_en */
2283
#define tdm_dcaddesc_en_adr(dca) (0x00008400 + (dca) * 0x4)
2284
/* bitmask for bitfield dca{d}_desc_en */
2285
#define tdm_dcaddesc_en_msk 0x80000000
2286
/* inverted bitmask for bitfield dca{d}_desc_en */
2287
#define tdm_dcaddesc_en_mskn 0x7fffffff
2288
/* lower bit position of bitfield dca{d}_desc_en */
2289
#define tdm_dcaddesc_en_shift 31
2290
/* width of bitfield dca{d}_desc_en */
2291
#define tdm_dcaddesc_en_width 1
2292
/* default value of bitfield dca{d}_desc_en */
2293
#define tdm_dcaddesc_en_default 0x0
2294

2295
/* tx desc{d}_en bitfield definitions
2296
 * preprocessor definitions for the bitfield "desc{d}_en".
2297
 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
2298
 * port="pif_tdm_desc_en_i[0]"
2299
 */
2300

2301
/* register address for bitfield desc{d}_en */
2302
#define tdm_descden_adr(descriptor) (0x00007c08 + (descriptor) * 0x40)
2303
/* bitmask for bitfield desc{d}_en */
2304
#define tdm_descden_msk 0x80000000
2305
/* inverted bitmask for bitfield desc{d}_en */
2306
#define tdm_descden_mskn 0x7fffffff
2307
/* lower bit position of bitfield desc{d}_en */
2308
#define tdm_descden_shift 31
2309
/* width of bitfield desc{d}_en */
2310
#define tdm_descden_width 1
2311
/* default value of bitfield desc{d}_en */
2312
#define tdm_descden_default 0x0
2313

2314
/* tx desc{d}_hd[c:0] bitfield definitions
2315
 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]".
2316
 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
2317
 * port="tdm_pif_desc0_hd_o[12:0]"
2318
 */
2319

2320
/* register address for bitfield desc{d}_hd[c:0] */
2321
#define tdm_descdhd_adr(descriptor) (0x00007c0c + (descriptor) * 0x40)
2322
/* bitmask for bitfield desc{d}_hd[c:0] */
2323
#define tdm_descdhd_msk 0x00001fff
2324
/* inverted bitmask for bitfield desc{d}_hd[c:0] */
2325
#define tdm_descdhd_mskn 0xffffe000
2326
/* lower bit position of bitfield desc{d}_hd[c:0] */
2327
#define tdm_descdhd_shift 0
2328
/* width of bitfield desc{d}_hd[c:0] */
2329
#define tdm_descdhd_width 13
2330

2331
/* tx desc{d}_len[9:0] bitfield definitions
2332
 * preprocessor definitions for the bitfield "desc{d}_len[9:0]".
2333
 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
2334
 * port="pif_tdm_desc0_len_i[9:0]"
2335
 */
2336

2337
/* register address for bitfield desc{d}_len[9:0] */
2338
#define tdm_descdlen_adr(descriptor) (0x00007c08 + (descriptor) * 0x40)
2339
/* bitmask for bitfield desc{d}_len[9:0] */
2340
#define tdm_descdlen_msk 0x00001ff8
2341
/* inverted bitmask for bitfield desc{d}_len[9:0] */
2342
#define tdm_descdlen_mskn 0xffffe007
2343
/* lower bit position of bitfield desc{d}_len[9:0] */
2344
#define tdm_descdlen_shift 3
2345
/* width of bitfield desc{d}_len[9:0] */
2346
#define tdm_descdlen_width 10
2347
/* default value of bitfield desc{d}_len[9:0] */
2348
#define tdm_descdlen_default 0x0
2349

2350
/* tx int_desc_wrb_en bitfield definitions
2351
 * preprocessor definitions for the bitfield "int_desc_wrb_en".
2352
 * port="pif_tdm_int_desc_wrb_en_i"
2353
 */
2354

2355
/* register address for bitfield int_desc_wrb_en */
2356
#define tdm_int_desc_wrb_en_adr 0x00007b40
2357
/* bitmask for bitfield int_desc_wrb_en */
2358
#define tdm_int_desc_wrb_en_msk 0x00000002
2359
/* inverted bitmask for bitfield int_desc_wrb_en */
2360
#define tdm_int_desc_wrb_en_mskn 0xfffffffd
2361
/* lower bit position of bitfield int_desc_wrb_en */
2362
#define tdm_int_desc_wrb_en_shift 1
2363
/* width of bitfield int_desc_wrb_en */
2364
#define tdm_int_desc_wrb_en_width 1
2365
/* default value of bitfield int_desc_wrb_en */
2366
#define tdm_int_desc_wrb_en_default 0x0
2367

2368
/* tx desc{d}_wrb_thresh[6:0] bitfield definitions
2369
 * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]".
2370
 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
2371
 * port="pif_tdm_desc0_wrb_thresh_i[6:0]"
2372
 */
2373

2374
/* register address for bitfield desc{d}_wrb_thresh[6:0] */
2375
#define tdm_descdwrb_thresh_adr(descriptor) (0x00007c18 + (descriptor) * 0x40)
2376
/* bitmask for bitfield desc{d}_wrb_thresh[6:0] */
2377
#define tdm_descdwrb_thresh_msk 0x00007f00
2378
/* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */
2379
#define tdm_descdwrb_thresh_mskn 0xffff80ff
2380
/* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */
2381
#define tdm_descdwrb_thresh_shift 8
2382
/* width of bitfield desc{d}_wrb_thresh[6:0] */
2383
#define tdm_descdwrb_thresh_width 7
2384
/* default value of bitfield desc{d}_wrb_thresh[6:0] */
2385
#define tdm_descdwrb_thresh_default 0x0
2386

2387
/* tx lso_tcp_flag_first[b:0] bitfield definitions
2388
 * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]".
2389
 * port="pif_thm_lso_tcp_flag_first_i[11:0]"
2390
 */
2391

2392
/* register address for bitfield lso_tcp_flag_first[b:0] */
2393
#define thm_lso_tcp_flag_first_adr 0x00007820
2394
/* bitmask for bitfield lso_tcp_flag_first[b:0] */
2395
#define thm_lso_tcp_flag_first_msk 0x00000fff
2396
/* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */
2397
#define thm_lso_tcp_flag_first_mskn 0xfffff000
2398
/* lower bit position of bitfield lso_tcp_flag_first[b:0] */
2399
#define thm_lso_tcp_flag_first_shift 0
2400
/* width of bitfield lso_tcp_flag_first[b:0] */
2401
#define thm_lso_tcp_flag_first_width 12
2402
/* default value of bitfield lso_tcp_flag_first[b:0] */
2403
#define thm_lso_tcp_flag_first_default 0x0
2404

2405
/* tx lso_tcp_flag_last[b:0] bitfield definitions
2406
 * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]".
2407
 * port="pif_thm_lso_tcp_flag_last_i[11:0]"
2408
 */
2409

2410
/* register address for bitfield lso_tcp_flag_last[b:0] */
2411
#define thm_lso_tcp_flag_last_adr 0x00007824
2412
/* bitmask for bitfield lso_tcp_flag_last[b:0] */
2413
#define thm_lso_tcp_flag_last_msk 0x00000fff
2414
/* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */
2415
#define thm_lso_tcp_flag_last_mskn 0xfffff000
2416
/* lower bit position of bitfield lso_tcp_flag_last[b:0] */
2417
#define thm_lso_tcp_flag_last_shift 0
2418
/* width of bitfield lso_tcp_flag_last[b:0] */
2419
#define thm_lso_tcp_flag_last_width 12
2420
/* default value of bitfield lso_tcp_flag_last[b:0] */
2421
#define thm_lso_tcp_flag_last_default 0x0
2422

2423
/* tx lso_tcp_flag_mid[b:0] bitfield definitions
2424
 * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]".
2425
 * port="pif_thm_lso_tcp_flag_mid_i[11:0]"
2426
 */
2427

2428
/* Register address for bitfield lro_rsc_max[1F:0] */
2429
#define rpo_lro_rsc_max_adr 0x00005598
2430
/* Bitmask for bitfield lro_rsc_max[1F:0] */
2431
#define rpo_lro_rsc_max_msk 0xFFFFFFFF
2432
/* Inverted bitmask for bitfield lro_rsc_max[1F:0] */
2433
#define rpo_lro_rsc_max_mskn 0x00000000
2434
/* Lower bit position of bitfield lro_rsc_max[1F:0] */
2435
#define rpo_lro_rsc_max_shift 0
2436
/* Width of bitfield lro_rsc_max[1F:0] */
2437
#define rpo_lro_rsc_max_width 32
2438
/* Default value of bitfield lro_rsc_max[1F:0] */
2439
#define rpo_lro_rsc_max_default 0x0
2440

2441
/* RX lro_en[1F:0] Bitfield Definitions
2442
 * Preprocessor definitions for the bitfield "lro_en[1F:0]".
2443
 * PORT="pif_rpo_lro_en_i[31:0]"
2444
 */
2445

2446
/* Register address for bitfield lro_en[1F:0] */
2447
#define rpo_lro_en_adr 0x00005590
2448
/* Bitmask for bitfield lro_en[1F:0] */
2449
#define rpo_lro_en_msk 0xFFFFFFFF
2450
/* Inverted bitmask for bitfield lro_en[1F:0] */
2451
#define rpo_lro_en_mskn 0x00000000
2452
/* Lower bit position of bitfield lro_en[1F:0] */
2453
#define rpo_lro_en_shift 0
2454
/* Width of bitfield lro_en[1F:0] */
2455
#define rpo_lro_en_width 32
2456
/* Default value of bitfield lro_en[1F:0] */
2457
#define rpo_lro_en_default 0x0
2458

2459
/* RX lro_ptopt_en Bitfield Definitions
2460
 * Preprocessor definitions for the bitfield "lro_ptopt_en".
2461
 * PORT="pif_rpo_lro_ptopt_en_i"
2462
 */
2463

2464
/* Register address for bitfield lro_ptopt_en */
2465
#define rpo_lro_ptopt_en_adr 0x00005594
2466
/* Bitmask for bitfield lro_ptopt_en */
2467
#define rpo_lro_ptopt_en_msk 0x00008000
2468
/* Inverted bitmask for bitfield lro_ptopt_en */
2469
#define rpo_lro_ptopt_en_mskn 0xFFFF7FFF
2470
/* Lower bit position of bitfield lro_ptopt_en */
2471
#define rpo_lro_ptopt_en_shift 15
2472
/* Width of bitfield lro_ptopt_en */
2473
#define rpo_lro_ptopt_en_width 1
2474
/* Default value of bitfield lro_ptopt_en */
2475
#define rpo_lro_ptopt_en_defalt 0x1
2476

2477
/* RX lro_q_ses_lmt Bitfield Definitions
2478
 * Preprocessor definitions for the bitfield "lro_q_ses_lmt".
2479
 * PORT="pif_rpo_lro_q_ses_lmt_i[1:0]"
2480
 */
2481

2482
/* Register address for bitfield lro_q_ses_lmt */
2483
#define rpo_lro_qses_lmt_adr 0x00005594
2484
/* Bitmask for bitfield lro_q_ses_lmt */
2485
#define rpo_lro_qses_lmt_msk 0x00003000
2486
/* Inverted bitmask for bitfield lro_q_ses_lmt */
2487
#define rpo_lro_qses_lmt_mskn 0xFFFFCFFF
2488
/* Lower bit position of bitfield lro_q_ses_lmt */
2489
#define rpo_lro_qses_lmt_shift 12
2490
/* Width of bitfield lro_q_ses_lmt */
2491
#define rpo_lro_qses_lmt_width 2
2492
/* Default value of bitfield lro_q_ses_lmt */
2493
#define rpo_lro_qses_lmt_default 0x1
2494

2495
/* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions
2496
 * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]".
2497
 * PORT="pif_rpo_lro_tot_dsc_lmt_i[1:0]"
2498
 */
2499

2500
/* Register address for bitfield lro_tot_dsc_lmt[1:0] */
2501
#define rpo_lro_tot_dsc_lmt_adr 0x00005594
2502
/* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */
2503
#define rpo_lro_tot_dsc_lmt_msk 0x00000060
2504
/* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */
2505
#define rpo_lro_tot_dsc_lmt_mskn 0xFFFFFF9F
2506
/* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */
2507
#define rpo_lro_tot_dsc_lmt_shift 5
2508
/* Width of bitfield lro_tot_dsc_lmt[1:0] */
2509
#define rpo_lro_tot_dsc_lmt_width 2
2510
/* Default value of bitfield lro_tot_dsc_lmt[1:0] */
2511
#define rpo_lro_tot_dsc_lmt_defalt 0x1
2512

2513
/* RX lro_pkt_min[4:0] Bitfield Definitions
2514
 * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]".
2515
 * PORT="pif_rpo_lro_pkt_min_i[4:0]"
2516
 */
2517

2518
/* Register address for bitfield lro_pkt_min[4:0] */
2519
#define rpo_lro_pkt_min_adr 0x00005594
2520
/* Bitmask for bitfield lro_pkt_min[4:0] */
2521
#define rpo_lro_pkt_min_msk 0x0000001F
2522
/* Inverted bitmask for bitfield lro_pkt_min[4:0] */
2523
#define rpo_lro_pkt_min_mskn 0xFFFFFFE0
2524
/* Lower bit position of bitfield lro_pkt_min[4:0] */
2525
#define rpo_lro_pkt_min_shift 0
2526
/* Width of bitfield lro_pkt_min[4:0] */
2527
#define rpo_lro_pkt_min_width 5
2528
/* Default value of bitfield lro_pkt_min[4:0] */
2529
#define rpo_lro_pkt_min_default 0x8
2530

2531
/* Width of bitfield lro{L}_des_max[1:0] */
2532
#define rpo_lro_ldes_max_width 2
2533
/* Default value of bitfield lro{L}_des_max[1:0] */
2534
#define rpo_lro_ldes_max_default 0x0
2535

2536
/* RX lro_tb_div[11:0] Bitfield Definitions
2537
 * Preprocessor definitions for the bitfield "lro_tb_div[11:0]".
2538
 * PORT="pif_rpo_lro_tb_div_i[11:0]"
2539
 */
2540

2541
/* Register address for bitfield lro_tb_div[11:0] */
2542
#define rpo_lro_tb_div_adr 0x00005620
2543
/* Bitmask for bitfield lro_tb_div[11:0] */
2544
#define rpo_lro_tb_div_msk 0xFFF00000
2545
/* Inverted bitmask for bitfield lro_tb_div[11:0] */
2546
#define rpo_lro_tb_div_mskn 0x000FFFFF
2547
/* Lower bit position of bitfield lro_tb_div[11:0] */
2548
#define rpo_lro_tb_div_shift 20
2549
/* Width of bitfield lro_tb_div[11:0] */
2550
#define rpo_lro_tb_div_width 12
2551
/* Default value of bitfield lro_tb_div[11:0] */
2552
#define rpo_lro_tb_div_default 0xC35
2553

2554
/* RX lro_ina_ival[9:0] Bitfield Definitions
2555
 *   Preprocessor definitions for the bitfield "lro_ina_ival[9:0]".
2556
 *   PORT="pif_rpo_lro_ina_ival_i[9:0]"
2557
 */
2558

2559
/* Register address for bitfield lro_ina_ival[9:0] */
2560
#define rpo_lro_ina_ival_adr 0x00005620
2561
/* Bitmask for bitfield lro_ina_ival[9:0] */
2562
#define rpo_lro_ina_ival_msk 0x000FFC00
2563
/* Inverted bitmask for bitfield lro_ina_ival[9:0] */
2564
#define rpo_lro_ina_ival_mskn 0xFFF003FF
2565
/* Lower bit position of bitfield lro_ina_ival[9:0] */
2566
#define rpo_lro_ina_ival_shift 10
2567
/* Width of bitfield lro_ina_ival[9:0] */
2568
#define rpo_lro_ina_ival_width 10
2569
/* Default value of bitfield lro_ina_ival[9:0] */
2570
#define rpo_lro_ina_ival_default 0xA
2571

2572
/* RX lro_max_ival[9:0] Bitfield Definitions
2573
 * Preprocessor definitions for the bitfield "lro_max_ival[9:0]".
2574
 * PORT="pif_rpo_lro_max_ival_i[9:0]"
2575
 */
2576

2577
/* Register address for bitfield lro_max_ival[9:0] */
2578
#define rpo_lro_max_ival_adr 0x00005620
2579
/* Bitmask for bitfield lro_max_ival[9:0] */
2580
#define rpo_lro_max_ival_msk 0x000003FF
2581
/* Inverted bitmask for bitfield lro_max_ival[9:0] */
2582
#define rpo_lro_max_ival_mskn 0xFFFFFC00
2583
/* Lower bit position of bitfield lro_max_ival[9:0] */
2584
#define rpo_lro_max_ival_shift 0
2585
/* Width of bitfield lro_max_ival[9:0] */
2586
#define rpo_lro_max_ival_width 10
2587
/* Default value of bitfield lro_max_ival[9:0] */
2588
#define rpo_lro_max_ival_default 0x19
2589

2590
/* TX dca{D}_cpuid[7:0] Bitfield Definitions
2591
 * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]".
2592
 * Parameter: DCA {D} | stride size 0x4 | range [0, 31]
2593
 * PORT="pif_tdm_dca0_cpuid_i[7:0]"
2594
 */
2595

2596
/* Register address for bitfield dca{D}_cpuid[7:0] */
2597
#define tdm_dca_dcpuid_adr(dca) (0x00008400 + (dca) * 0x4)
2598
/* Bitmask for bitfield dca{D}_cpuid[7:0] */
2599
#define tdm_dca_dcpuid_msk 0x000000FF
2600
/* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */
2601
#define tdm_dca_dcpuid_mskn 0xFFFFFF00
2602
/* Lower bit position of bitfield dca{D}_cpuid[7:0] */
2603
#define tdm_dca_dcpuid_shift 0
2604
/* Width of bitfield dca{D}_cpuid[7:0] */
2605
#define tdm_dca_dcpuid_width 8
2606
/* Default value of bitfield dca{D}_cpuid[7:0] */
2607
#define tdm_dca_dcpuid_default 0x0
2608

2609
/* TX dca{D}_desc_en Bitfield Definitions
2610
 * Preprocessor definitions for the bitfield "dca{D}_desc_en".
2611
 * Parameter: DCA {D} | stride size 0x4 | range [0, 31]
2612
 * PORT="pif_tdm_dca_desc_en_i[0]"
2613
 */
2614

2615
/* Register address for bitfield dca{D}_desc_en */
2616
#define tdm_dca_ddesc_en_adr(dca) (0x00008400 + (dca) * 0x4)
2617
/* Bitmask for bitfield dca{D}_desc_en */
2618
#define tdm_dca_ddesc_en_msk 0x80000000
2619
/* Inverted bitmask for bitfield dca{D}_desc_en */
2620
#define tdm_dca_ddesc_en_mskn 0x7FFFFFFF
2621
/* Lower bit position of bitfield dca{D}_desc_en */
2622
#define tdm_dca_ddesc_en_shift 31
2623
/* Width of bitfield dca{D}_desc_en */
2624
#define tdm_dca_ddesc_en_width 1
2625
/* Default value of bitfield dca{D}_desc_en */
2626
#define tdm_dca_ddesc_en_default 0x0
2627

2628
/* TX desc{D}_en Bitfield Definitions
2629
 * Preprocessor definitions for the bitfield "desc{D}_en".
2630
 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]
2631
 * PORT="pif_tdm_desc_en_i[0]"
2632
 */
2633

2634
/* Register address for bitfield desc{D}_en */
2635
#define tdm_desc_den_adr(descriptor) (0x00007C08 + (descriptor) * 0x40)
2636
/* Bitmask for bitfield desc{D}_en */
2637
#define tdm_desc_den_msk 0x80000000
2638
/* Inverted bitmask for bitfield desc{D}_en */
2639
#define tdm_desc_den_mskn 0x7FFFFFFF
2640
/* Lower bit position of bitfield desc{D}_en */
2641
#define tdm_desc_den_shift 31
2642
/* Width of bitfield desc{D}_en */
2643
#define tdm_desc_den_width 1
2644
/* Default value of bitfield desc{D}_en */
2645
#define tdm_desc_den_default 0x0
2646

2647
/* TX desc{D}_hd[C:0] Bitfield Definitions
2648
 * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]".
2649
 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]
2650
 * PORT="tdm_pif_desc0_hd_o[12:0]"
2651
 */
2652

2653
/* Register address for bitfield desc{D}_hd[C:0] */
2654
#define tdm_desc_dhd_adr(descriptor) (0x00007C0C + (descriptor) * 0x40)
2655
/* Bitmask for bitfield desc{D}_hd[C:0] */
2656
#define tdm_desc_dhd_msk 0x00001FFF
2657
/* Inverted bitmask for bitfield desc{D}_hd[C:0] */
2658
#define tdm_desc_dhd_mskn 0xFFFFE000
2659
/* Lower bit position of bitfield desc{D}_hd[C:0] */
2660
#define tdm_desc_dhd_shift 0
2661
/* Width of bitfield desc{D}_hd[C:0] */
2662
#define tdm_desc_dhd_width 13
2663

2664
/* TX desc{D}_len[9:0] Bitfield Definitions
2665
 * Preprocessor definitions for the bitfield "desc{D}_len[9:0]".
2666
 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]
2667
 * PORT="pif_tdm_desc0_len_i[9:0]"
2668
 */
2669

2670
/* Register address for bitfield desc{D}_len[9:0] */
2671
#define tdm_desc_dlen_adr(descriptor) (0x00007C08 + (descriptor) * 0x40)
2672
/* Bitmask for bitfield desc{D}_len[9:0] */
2673
#define tdm_desc_dlen_msk 0x00001FF8
2674
/* Inverted bitmask for bitfield desc{D}_len[9:0] */
2675
#define tdm_desc_dlen_mskn 0xFFFFE007
2676
/* Lower bit position of bitfield desc{D}_len[9:0] */
2677
#define tdm_desc_dlen_shift 3
2678
/* Width of bitfield desc{D}_len[9:0] */
2679
#define tdm_desc_dlen_width 10
2680
/* Default value of bitfield desc{D}_len[9:0] */
2681
#define tdm_desc_dlen_default 0x0
2682

2683
/* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions
2684
 * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]".
2685
 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]
2686
 * PORT="pif_tdm_desc0_wrb_thresh_i[6:0]"
2687
 */
2688

2689
/* Register address for bitfield desc{D}_wrb_thresh[6:0] */
2690
#define tdm_desc_dwrb_thresh_adr(descriptor) \
2691
	(0x00007C18 + (descriptor) * 0x40)
2692
/* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */
2693
#define tdm_desc_dwrb_thresh_msk 0x00007F00
2694
/* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */
2695
#define tdm_desc_dwrb_thresh_mskn 0xFFFF80FF
2696
/* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */
2697
#define tdm_desc_dwrb_thresh_shift 8
2698
/* Width of bitfield desc{D}_wrb_thresh[6:0] */
2699
#define tdm_desc_dwrb_thresh_width 7
2700
/* Default value of bitfield desc{D}_wrb_thresh[6:0] */
2701
#define tdm_desc_dwrb_thresh_default 0x0
2702

2703
/* TX tdm_int_mod_en Bitfield Definitions
2704
 * Preprocessor definitions for the bitfield "tdm_int_mod_en".
2705
 * PORT="pif_tdm_int_mod_en_i"
2706
 */
2707

2708
/* Register address for bitfield tdm_int_mod_en */
2709
#define tdm_int_mod_en_adr 0x00007B40
2710
/* Bitmask for bitfield tdm_int_mod_en */
2711
#define tdm_int_mod_en_msk 0x00000010
2712
/* Inverted bitmask for bitfield tdm_int_mod_en */
2713
#define tdm_int_mod_en_mskn 0xFFFFFFEF
2714
/* Lower bit position of bitfield tdm_int_mod_en */
2715
#define tdm_int_mod_en_shift 4
2716
/* Width of bitfield tdm_int_mod_en */
2717
#define tdm_int_mod_en_width 1
2718
/* Default value of bitfield tdm_int_mod_en */
2719
#define tdm_int_mod_en_default 0x0
2720

2721
/* TX lso_tcp_flag_mid[B:0] Bitfield Definitions
2722
 * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]".
2723
 * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]"
2724
 */
2725
/* register address for bitfield lso_tcp_flag_mid[b:0] */
2726
#define thm_lso_tcp_flag_mid_adr 0x00007820
2727
/* bitmask for bitfield lso_tcp_flag_mid[b:0] */
2728
#define thm_lso_tcp_flag_mid_msk 0x0fff0000
2729
/* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */
2730
#define thm_lso_tcp_flag_mid_mskn 0xf000ffff
2731
/* lower bit position of bitfield lso_tcp_flag_mid[b:0] */
2732
#define thm_lso_tcp_flag_mid_shift 16
2733
/* width of bitfield lso_tcp_flag_mid[b:0] */
2734
#define thm_lso_tcp_flag_mid_width 12
2735
/* default value of bitfield lso_tcp_flag_mid[b:0] */
2736
#define thm_lso_tcp_flag_mid_default 0x0
2737

2738
/* tx tx_buf_en bitfield definitions
2739
 * preprocessor definitions for the bitfield "tx_buf_en".
2740
 * port="pif_tpb_tx_buf_en_i"
2741
 */
2742

2743
/* register address for bitfield tx_buf_en */
2744
#define tpb_tx_buf_en_adr 0x00007900
2745
/* bitmask for bitfield tx_buf_en */
2746
#define tpb_tx_buf_en_msk 0x00000001
2747
/* inverted bitmask for bitfield tx_buf_en */
2748
#define tpb_tx_buf_en_mskn 0xfffffffe
2749
/* lower bit position of bitfield tx_buf_en */
2750
#define tpb_tx_buf_en_shift 0
2751
/* width of bitfield tx_buf_en */
2752
#define tpb_tx_buf_en_width 1
2753
/* default value of bitfield tx_buf_en */
2754
#define tpb_tx_buf_en_default 0x0
2755

2756
/* tx tx_tc_mode bitfield definitions
2757
 * preprocessor definitions for the bitfield "tx_tc_mode".
2758
 * port="pif_tpb_tx_tc_mode_i"
2759
 */
2760

2761
/* register address for bitfield tx_tc_mode */
2762
#define tpb_tx_tc_mode_adr 0x00007900
2763
/* bitmask for bitfield tx_tc_mode */
2764
#define tpb_tx_tc_mode_msk 0x00000100
2765
/* inverted bitmask for bitfield tx_tc_mode */
2766
#define tpb_tx_tc_mode_mskn 0xfffffeff
2767
/* lower bit position of bitfield tx_tc_mode */
2768
#define tpb_tx_tc_mode_shift 8
2769
/* width of bitfield tx_tc_mode */
2770
#define tpb_tx_tc_mode_width 1
2771
/* default value of bitfield tx_tc_mode */
2772
#define tpb_tx_tc_mode_default 0x0
2773

2774

2775
/* tx tx{b}_hi_thresh[c:0] bitfield definitions
2776
 * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]".
2777
 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
2778
 * port="pif_tpb_tx0_hi_thresh_i[12:0]"
2779
 */
2780

2781
/* register address for bitfield tx{b}_hi_thresh[c:0] */
2782
#define tpb_txbhi_thresh_adr(buffer) (0x00007914 + (buffer) * 0x10)
2783
/* bitmask for bitfield tx{b}_hi_thresh[c:0] */
2784
#define tpb_txbhi_thresh_msk 0x1fff0000
2785
/* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */
2786
#define tpb_txbhi_thresh_mskn 0xe000ffff
2787
/* lower bit position of bitfield tx{b}_hi_thresh[c:0] */
2788
#define tpb_txbhi_thresh_shift 16
2789
/* width of bitfield tx{b}_hi_thresh[c:0] */
2790
#define tpb_txbhi_thresh_width 13
2791
/* default value of bitfield tx{b}_hi_thresh[c:0] */
2792
#define tpb_txbhi_thresh_default 0x0
2793

2794
/* tx tx{b}_lo_thresh[c:0] bitfield definitions
2795
 * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]".
2796
 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
2797
 * port="pif_tpb_tx0_lo_thresh_i[12:0]"
2798
 */
2799

2800
/* register address for bitfield tx{b}_lo_thresh[c:0] */
2801
#define tpb_txblo_thresh_adr(buffer) (0x00007914 + (buffer) * 0x10)
2802
/* bitmask for bitfield tx{b}_lo_thresh[c:0] */
2803
#define tpb_txblo_thresh_msk 0x00001fff
2804
/* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */
2805
#define tpb_txblo_thresh_mskn 0xffffe000
2806
/* lower bit position of bitfield tx{b}_lo_thresh[c:0] */
2807
#define tpb_txblo_thresh_shift 0
2808
/* width of bitfield tx{b}_lo_thresh[c:0] */
2809
#define tpb_txblo_thresh_width 13
2810
/* default value of bitfield tx{b}_lo_thresh[c:0] */
2811
#define tpb_txblo_thresh_default 0x0
2812

2813
/* tx dma_sys_loopback bitfield definitions
2814
 * preprocessor definitions for the bitfield "dma_sys_loopback".
2815
 * port="pif_tpb_dma_sys_lbk_i"
2816
 */
2817

2818
/* register address for bitfield dma_sys_loopback */
2819
#define tpb_dma_sys_lbk_adr 0x00007000
2820
/* bitmask for bitfield dma_sys_loopback */
2821
#define tpb_dma_sys_lbk_msk 0x00000040
2822
/* inverted bitmask for bitfield dma_sys_loopback */
2823
#define tpb_dma_sys_lbk_mskn 0xffffffbf
2824
/* lower bit position of bitfield dma_sys_loopback */
2825
#define tpb_dma_sys_lbk_shift 6
2826
/* width of bitfield dma_sys_loopback */
2827
#define tpb_dma_sys_lbk_width 1
2828
/* default value of bitfield dma_sys_loopback */
2829
#define tpb_dma_sys_lbk_default 0x0
2830

2831
/* tx tx{b}_buf_size[7:0] bitfield definitions
2832
 * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]".
2833
 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
2834
 * port="pif_tpb_tx0_buf_size_i[7:0]"
2835
 */
2836

2837
/* register address for bitfield tx{b}_buf_size[7:0] */
2838
#define tpb_txbbuf_size_adr(buffer) (0x00007910 + (buffer) * 0x10)
2839
/* bitmask for bitfield tx{b}_buf_size[7:0] */
2840
#define tpb_txbbuf_size_msk 0x000000ff
2841
/* inverted bitmask for bitfield tx{b}_buf_size[7:0] */
2842
#define tpb_txbbuf_size_mskn 0xffffff00
2843
/* lower bit position of bitfield tx{b}_buf_size[7:0] */
2844
#define tpb_txbbuf_size_shift 0
2845
/* width of bitfield tx{b}_buf_size[7:0] */
2846
#define tpb_txbbuf_size_width 8
2847
/* default value of bitfield tx{b}_buf_size[7:0] */
2848
#define tpb_txbbuf_size_default 0x0
2849

2850
/* tx tx_scp_ins_en bitfield definitions
2851
 * preprocessor definitions for the bitfield "tx_scp_ins_en".
2852
 * port="pif_tpb_scp_ins_en_i"
2853
 */
2854

2855
/* register address for bitfield tx_scp_ins_en */
2856
#define tpb_tx_scp_ins_en_adr 0x00007900
2857
/* bitmask for bitfield tx_scp_ins_en */
2858
#define tpb_tx_scp_ins_en_msk 0x00000004
2859
/* inverted bitmask for bitfield tx_scp_ins_en */
2860
#define tpb_tx_scp_ins_en_mskn 0xfffffffb
2861
/* lower bit position of bitfield tx_scp_ins_en */
2862
#define tpb_tx_scp_ins_en_shift 2
2863
/* width of bitfield tx_scp_ins_en */
2864
#define tpb_tx_scp_ins_en_width 1
2865
/* default value of bitfield tx_scp_ins_en */
2866
#define tpb_tx_scp_ins_en_default 0x0
2867

2868
/* tx ipv4_chk_en bitfield definitions
2869
 * preprocessor definitions for the bitfield "ipv4_chk_en".
2870
 * port="pif_tpo_ipv4_chk_en_i"
2871
 */
2872

2873
/* register address for bitfield ipv4_chk_en */
2874
#define tpo_ipv4chk_en_adr 0x00007800
2875
/* bitmask for bitfield ipv4_chk_en */
2876
#define tpo_ipv4chk_en_msk 0x00000002
2877
/* inverted bitmask for bitfield ipv4_chk_en */
2878
#define tpo_ipv4chk_en_mskn 0xfffffffd
2879
/* lower bit position of bitfield ipv4_chk_en */
2880
#define tpo_ipv4chk_en_shift 1
2881
/* width of bitfield ipv4_chk_en */
2882
#define tpo_ipv4chk_en_width 1
2883
/* default value of bitfield ipv4_chk_en */
2884
#define tpo_ipv4chk_en_default 0x0
2885

2886
/* tx l4_chk_en bitfield definitions
2887
 * preprocessor definitions for the bitfield "l4_chk_en".
2888
 * port="pif_tpo_l4_chk_en_i"
2889
 */
2890

2891
/* register address for bitfield l4_chk_en */
2892
#define tpol4chk_en_adr 0x00007800
2893
/* bitmask for bitfield l4_chk_en */
2894
#define tpol4chk_en_msk 0x00000001
2895
/* inverted bitmask for bitfield l4_chk_en */
2896
#define tpol4chk_en_mskn 0xfffffffe
2897
/* lower bit position of bitfield l4_chk_en */
2898
#define tpol4chk_en_shift 0
2899
/* width of bitfield l4_chk_en */
2900
#define tpol4chk_en_width 1
2901
/* default value of bitfield l4_chk_en */
2902
#define tpol4chk_en_default 0x0
2903

2904
/* tx pkt_sys_loopback bitfield definitions
2905
 * preprocessor definitions for the bitfield "pkt_sys_loopback".
2906
 * port="pif_tpo_pkt_sys_lbk_i"
2907
 */
2908

2909
/* register address for bitfield pkt_sys_loopback */
2910
#define tpo_pkt_sys_lbk_adr 0x00007000
2911
/* bitmask for bitfield pkt_sys_loopback */
2912
#define tpo_pkt_sys_lbk_msk 0x00000080
2913
/* inverted bitmask for bitfield pkt_sys_loopback */
2914
#define tpo_pkt_sys_lbk_mskn 0xffffff7f
2915
/* lower bit position of bitfield pkt_sys_loopback */
2916
#define tpo_pkt_sys_lbk_shift 7
2917
/* width of bitfield pkt_sys_loopback */
2918
#define tpo_pkt_sys_lbk_width 1
2919
/* default value of bitfield pkt_sys_loopback */
2920
#define tpo_pkt_sys_lbk_default 0x0
2921

2922
/* tx data_tc_arb_mode bitfield definitions
2923
 * preprocessor definitions for the bitfield "data_tc_arb_mode".
2924
 * port="pif_tps_data_tc_arb_mode_i"
2925
 */
2926

2927
/* register address for bitfield data_tc_arb_mode */
2928
#define tps_data_tc_arb_mode_adr 0x00007100
2929
/* bitmask for bitfield data_tc_arb_mode */
2930
#define tps_data_tc_arb_mode_msk 0x00000001
2931
/* inverted bitmask for bitfield data_tc_arb_mode */
2932
#define tps_data_tc_arb_mode_mskn 0xfffffffe
2933
/* lower bit position of bitfield data_tc_arb_mode */
2934
#define tps_data_tc_arb_mode_shift 0
2935
/* width of bitfield data_tc_arb_mode */
2936
#define tps_data_tc_arb_mode_width 1
2937
/* default value of bitfield data_tc_arb_mode */
2938
#define tps_data_tc_arb_mode_default 0x0
2939

2940
/* tx desc_rate_ta_rst bitfield definitions
2941
 * preprocessor definitions for the bitfield "desc_rate_ta_rst".
2942
 * port="pif_tps_desc_rate_ta_rst_i"
2943
 */
2944

2945
/* register address for bitfield desc_rate_ta_rst */
2946
#define tps_desc_rate_ta_rst_adr 0x00007310
2947
/* bitmask for bitfield desc_rate_ta_rst */
2948
#define tps_desc_rate_ta_rst_msk 0x80000000
2949
/* inverted bitmask for bitfield desc_rate_ta_rst */
2950
#define tps_desc_rate_ta_rst_mskn 0x7fffffff
2951
/* lower bit position of bitfield desc_rate_ta_rst */
2952
#define tps_desc_rate_ta_rst_shift 31
2953
/* width of bitfield desc_rate_ta_rst */
2954
#define tps_desc_rate_ta_rst_width 1
2955
/* default value of bitfield desc_rate_ta_rst */
2956
#define tps_desc_rate_ta_rst_default 0x0
2957

2958
/* tx desc_rate_limit[a:0] bitfield definitions
2959
 * preprocessor definitions for the bitfield "desc_rate_limit[a:0]".
2960
 * port="pif_tps_desc_rate_lim_i[10:0]"
2961
 */
2962

2963
/* register address for bitfield desc_rate_limit[a:0] */
2964
#define tps_desc_rate_lim_adr 0x00007310
2965
/* bitmask for bitfield desc_rate_limit[a:0] */
2966
#define tps_desc_rate_lim_msk 0x000007ff
2967
/* inverted bitmask for bitfield desc_rate_limit[a:0] */
2968
#define tps_desc_rate_lim_mskn 0xfffff800
2969
/* lower bit position of bitfield desc_rate_limit[a:0] */
2970
#define tps_desc_rate_lim_shift 0
2971
/* width of bitfield desc_rate_limit[a:0] */
2972
#define tps_desc_rate_lim_width 11
2973
/* default value of bitfield desc_rate_limit[a:0] */
2974
#define tps_desc_rate_lim_default 0x0
2975

2976
/* tx desc_tc_arb_mode[1:0] bitfield definitions
2977
 * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]".
2978
 * port="pif_tps_desc_tc_arb_mode_i[1:0]"
2979
 */
2980

2981
/* register address for bitfield desc_tc_arb_mode[1:0] */
2982
#define tps_desc_tc_arb_mode_adr 0x00007200
2983
/* bitmask for bitfield desc_tc_arb_mode[1:0] */
2984
#define tps_desc_tc_arb_mode_msk 0x00000003
2985
/* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */
2986
#define tps_desc_tc_arb_mode_mskn 0xfffffffc
2987
/* lower bit position of bitfield desc_tc_arb_mode[1:0] */
2988
#define tps_desc_tc_arb_mode_shift 0
2989
/* width of bitfield desc_tc_arb_mode[1:0] */
2990
#define tps_desc_tc_arb_mode_width 2
2991
/* default value of bitfield desc_tc_arb_mode[1:0] */
2992
#define tps_desc_tc_arb_mode_default 0x0
2993

2994
/* tx desc_tc{t}_credit_max[b:0] bitfield definitions
2995
 * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]".
2996
 * parameter: tc {t} | stride size 0x4 | range [0, 7]
2997
 * port="pif_tps_desc_tc0_credit_max_i[11:0]"
2998
 */
2999

3000
/* register address for bitfield desc_tc{t}_credit_max[b:0] */
3001
#define tps_desc_tctcredit_max_adr(tc) (0x00007210 + (tc) * 0x4)
3002
/* bitmask for bitfield desc_tc{t}_credit_max[b:0] */
3003
#define tps_desc_tctcredit_max_msk 0x0fff0000
3004
/* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */
3005
#define tps_desc_tctcredit_max_mskn 0xf000ffff
3006
/* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */
3007
#define tps_desc_tctcredit_max_shift 16
3008
/* width of bitfield desc_tc{t}_credit_max[b:0] */
3009
#define tps_desc_tctcredit_max_width 12
3010
/* default value of bitfield desc_tc{t}_credit_max[b:0] */
3011
#define tps_desc_tctcredit_max_default 0x0
3012

3013
/* tx desc_tc{t}_weight[8:0] bitfield definitions
3014
 * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]".
3015
 * parameter: tc {t} | stride size 0x4 | range [0, 7]
3016
 * port="pif_tps_desc_tc0_weight_i[8:0]"
3017
 */
3018

3019
/* register address for bitfield desc_tc{t}_weight[8:0] */
3020
#define tps_desc_tctweight_adr(tc) (0x00007210 + (tc) * 0x4)
3021
/* bitmask for bitfield desc_tc{t}_weight[8:0] */
3022
#define tps_desc_tctweight_msk 0x000001ff
3023
/* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */
3024
#define tps_desc_tctweight_mskn 0xfffffe00
3025
/* lower bit position of bitfield desc_tc{t}_weight[8:0] */
3026
#define tps_desc_tctweight_shift 0
3027
/* width of bitfield desc_tc{t}_weight[8:0] */
3028
#define tps_desc_tctweight_width 9
3029
/* default value of bitfield desc_tc{t}_weight[8:0] */
3030
#define tps_desc_tctweight_default 0x0
3031

3032
/* tx desc_vm_arb_mode bitfield definitions
3033
 * preprocessor definitions for the bitfield "desc_vm_arb_mode".
3034
 * port="pif_tps_desc_vm_arb_mode_i"
3035
 */
3036

3037
/* register address for bitfield desc_vm_arb_mode */
3038
#define tps_desc_vm_arb_mode_adr 0x00007300
3039
/* bitmask for bitfield desc_vm_arb_mode */
3040
#define tps_desc_vm_arb_mode_msk 0x00000001
3041
/* inverted bitmask for bitfield desc_vm_arb_mode */
3042
#define tps_desc_vm_arb_mode_mskn 0xfffffffe
3043
/* lower bit position of bitfield desc_vm_arb_mode */
3044
#define tps_desc_vm_arb_mode_shift 0
3045
/* width of bitfield desc_vm_arb_mode */
3046
#define tps_desc_vm_arb_mode_width 1
3047
/* default value of bitfield desc_vm_arb_mode */
3048
#define tps_desc_vm_arb_mode_default 0x0
3049

3050
/* tx data_tc{t}_credit_max[b:0] bitfield definitions
3051
 * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]".
3052
 * parameter: tc {t} | stride size 0x4 | range [0, 7]
3053
 * port="pif_tps_data_tc0_credit_max_i[11:0]"
3054
 */
3055

3056
/* register address for bitfield data_tc{t}_credit_max[b:0] */
3057
#define tps_data_tctcredit_max_adr(tc) (0x00007110 + (tc) * 0x4)
3058
/* bitmask for bitfield data_tc{t}_credit_max[b:0] */
3059
#define tps_data_tctcredit_max_msk 0x0fff0000
3060
/* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */
3061
#define tps_data_tctcredit_max_mskn 0xf000ffff
3062
/* lower bit position of bitfield data_tc{t}_credit_max[b:0] */
3063
#define tps_data_tctcredit_max_shift 16
3064
/* width of bitfield data_tc{t}_credit_max[b:0] */
3065
#define tps_data_tctcredit_max_width 12
3066
/* default value of bitfield data_tc{t}_credit_max[b:0] */
3067
#define tps_data_tctcredit_max_default 0x0
3068

3069
/* tx data_tc{t}_weight[8:0] bitfield definitions
3070
 * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]".
3071
 * parameter: tc {t} | stride size 0x4 | range [0, 7]
3072
 * port="pif_tps_data_tc0_weight_i[8:0]"
3073
 */
3074

3075
/* register address for bitfield data_tc{t}_weight[8:0] */
3076
#define tps_data_tctweight_adr(tc) (0x00007110 + (tc) * 0x4)
3077
/* bitmask for bitfield data_tc{t}_weight[8:0] */
3078
#define tps_data_tctweight_msk 0x000001ff
3079
/* inverted bitmask for bitfield data_tc{t}_weight[8:0] */
3080
#define tps_data_tctweight_mskn 0xfffffe00
3081
/* lower bit position of bitfield data_tc{t}_weight[8:0] */
3082
#define tps_data_tctweight_shift 0
3083
/* width of bitfield data_tc{t}_weight[8:0] */
3084
#define tps_data_tctweight_width 9
3085
/* default value of bitfield data_tc{t}_weight[8:0] */
3086
#define tps_data_tctweight_default 0x0
3087

3088
/* tx reg_res_dsbl bitfield definitions
3089
 * preprocessor definitions for the bitfield "reg_res_dsbl".
3090
 * port="pif_tx_reg_res_dsbl_i"
3091
 */
3092

3093
/* register address for bitfield reg_res_dsbl */
3094
#define tx_reg_res_dsbl_adr 0x00007000
3095
/* bitmask for bitfield reg_res_dsbl */
3096
#define tx_reg_res_dsbl_msk 0x20000000
3097
/* inverted bitmask for bitfield reg_res_dsbl */
3098
#define tx_reg_res_dsbl_mskn 0xdfffffff
3099
/* lower bit position of bitfield reg_res_dsbl */
3100
#define tx_reg_res_dsbl_shift 29
3101
/* width of bitfield reg_res_dsbl */
3102
#define tx_reg_res_dsbl_width 1
3103
/* default value of bitfield reg_res_dsbl */
3104
#define tx_reg_res_dsbl_default 0x1
3105

3106
/* mac_phy register access busy bitfield definitions
3107
 * preprocessor definitions for the bitfield "register access busy".
3108
 * port="msm_pif_reg_busy_o"
3109
 */
3110

3111
/* register address for bitfield register access busy */
3112
#define msm_reg_access_busy_adr 0x00004400
3113
/* bitmask for bitfield register access busy */
3114
#define msm_reg_access_busy_msk 0x00001000
3115
/* inverted bitmask for bitfield register access busy */
3116
#define msm_reg_access_busy_mskn 0xffffefff
3117
/* lower bit position of bitfield register access busy */
3118
#define msm_reg_access_busy_shift 12
3119
/* width of bitfield register access busy */
3120
#define msm_reg_access_busy_width 1
3121

3122
/* mac_phy msm register address[7:0] bitfield definitions
3123
 * preprocessor definitions for the bitfield "msm register address[7:0]".
3124
 * port="pif_msm_reg_addr_i[7:0]"
3125
 */
3126

3127
/* register address for bitfield msm register address[7:0] */
3128
#define msm_reg_addr_adr 0x00004400
3129
/* bitmask for bitfield msm register address[7:0] */
3130
#define msm_reg_addr_msk 0x000000ff
3131
/* inverted bitmask for bitfield msm register address[7:0] */
3132
#define msm_reg_addr_mskn 0xffffff00
3133
/* lower bit position of bitfield msm register address[7:0] */
3134
#define msm_reg_addr_shift 0
3135
/* width of bitfield msm register address[7:0] */
3136
#define msm_reg_addr_width 8
3137
/* default value of bitfield msm register address[7:0] */
3138
#define msm_reg_addr_default 0x0
3139

3140
/* mac_phy register read strobe bitfield definitions
3141
 * preprocessor definitions for the bitfield "register read strobe".
3142
 * port="pif_msm_reg_rden_i"
3143
 */
3144

3145
/* register address for bitfield register read strobe */
3146
#define msm_reg_rd_strobe_adr 0x00004400
3147
/* bitmask for bitfield register read strobe */
3148
#define msm_reg_rd_strobe_msk 0x00000200
3149
/* inverted bitmask for bitfield register read strobe */
3150
#define msm_reg_rd_strobe_mskn 0xfffffdff
3151
/* lower bit position of bitfield register read strobe */
3152
#define msm_reg_rd_strobe_shift 9
3153
/* width of bitfield register read strobe */
3154
#define msm_reg_rd_strobe_width 1
3155
/* default value of bitfield register read strobe */
3156
#define msm_reg_rd_strobe_default 0x0
3157

3158
/* mac_phy msm register read data[31:0] bitfield definitions
3159
 * preprocessor definitions for the bitfield "msm register read data[31:0]".
3160
 * port="msm_pif_reg_rd_data_o[31:0]"
3161
 */
3162

3163
/* register address for bitfield msm register read data[31:0] */
3164
#define msm_reg_rd_data_adr 0x00004408
3165
/* bitmask for bitfield msm register read data[31:0] */
3166
#define msm_reg_rd_data_msk 0xffffffff
3167
/* inverted bitmask for bitfield msm register read data[31:0] */
3168
#define msm_reg_rd_data_mskn 0x00000000
3169
/* lower bit position of bitfield msm register read data[31:0] */
3170
#define msm_reg_rd_data_shift 0
3171
/* width of bitfield msm register read data[31:0] */
3172
#define msm_reg_rd_data_width 32
3173

3174
/* mac_phy msm register write data[31:0] bitfield definitions
3175
 * preprocessor definitions for the bitfield "msm register write data[31:0]".
3176
 * port="pif_msm_reg_wr_data_i[31:0]"
3177
 */
3178

3179
/* register address for bitfield msm register write data[31:0] */
3180
#define msm_reg_wr_data_adr 0x00004404
3181
/* bitmask for bitfield msm register write data[31:0] */
3182
#define msm_reg_wr_data_msk 0xffffffff
3183
/* inverted bitmask for bitfield msm register write data[31:0] */
3184
#define msm_reg_wr_data_mskn 0x00000000
3185
/* lower bit position of bitfield msm register write data[31:0] */
3186
#define msm_reg_wr_data_shift 0
3187
/* width of bitfield msm register write data[31:0] */
3188
#define msm_reg_wr_data_width 32
3189
/* default value of bitfield msm register write data[31:0] */
3190
#define msm_reg_wr_data_default 0x0
3191

3192
/* mac_phy register write strobe bitfield definitions
3193
 * preprocessor definitions for the bitfield "register write strobe".
3194
 * port="pif_msm_reg_wren_i"
3195
 */
3196

3197
/* register address for bitfield register write strobe */
3198
#define msm_reg_wr_strobe_adr 0x00004400
3199
/* bitmask for bitfield register write strobe */
3200
#define msm_reg_wr_strobe_msk 0x00000100
3201
/* inverted bitmask for bitfield register write strobe */
3202
#define msm_reg_wr_strobe_mskn 0xfffffeff
3203
/* lower bit position of bitfield register write strobe */
3204
#define msm_reg_wr_strobe_shift 8
3205
/* width of bitfield register write strobe */
3206
#define msm_reg_wr_strobe_width 1
3207
/* default value of bitfield register write strobe */
3208
#define msm_reg_wr_strobe_default 0x0
3209

3210
/* mif soft reset bitfield definitions
3211
 * preprocessor definitions for the bitfield "soft reset".
3212
 * port="pif_glb_res_i"
3213
 */
3214

3215
/* register address for bitfield soft reset */
3216
#define glb_soft_res_adr 0x00000000
3217
/* bitmask for bitfield soft reset */
3218
#define glb_soft_res_msk 0x00008000
3219
/* inverted bitmask for bitfield soft reset */
3220
#define glb_soft_res_mskn 0xffff7fff
3221
/* lower bit position of bitfield soft reset */
3222
#define glb_soft_res_shift 15
3223
/* width of bitfield soft reset */
3224
#define glb_soft_res_width 1
3225
/* default value of bitfield soft reset */
3226
#define glb_soft_res_default 0x0
3227

3228
/* mif register reset disable bitfield definitions
3229
 * preprocessor definitions for the bitfield "register reset disable".
3230
 * port="pif_glb_reg_res_dsbl_i"
3231
 */
3232

3233
/* register address for bitfield register reset disable */
3234
#define glb_reg_res_dis_adr 0x00000000
3235
/* bitmask for bitfield register reset disable */
3236
#define glb_reg_res_dis_msk 0x00004000
3237
/* inverted bitmask for bitfield register reset disable */
3238
#define glb_reg_res_dis_mskn 0xffffbfff
3239
/* lower bit position of bitfield register reset disable */
3240
#define glb_reg_res_dis_shift 14
3241
/* width of bitfield register reset disable */
3242
#define glb_reg_res_dis_width 1
3243
/* default value of bitfield register reset disable */
3244
#define glb_reg_res_dis_default 0x1
3245

3246
/* tx dma debug control definitions */
3247
#define tx_dma_debug_ctl_adr 0x00008920u
3248

3249
/* tx dma descriptor base address msw definitions */
3250
#define tx_dma_desc_base_addrmsw_adr(descriptor) \
3251
	(0x00007c04u + (descriptor) * 0x40)
3252

3253
/* tx interrupt moderation control register definitions
3254
 * Preprocessor definitions for TX Interrupt Moderation Control Register
3255
 * Base Address: 0x00008980
3256
 * Parameter: queue {Q} | stride size 0x4 | range [0, 31]
3257
 */
3258

3259
#define tx_intr_moderation_ctl_adr(queue) (0x00008980u + (queue) * 0x4)
3260

3261
/* pcie reg_res_dsbl bitfield definitions
3262
 * preprocessor definitions for the bitfield "reg_res_dsbl".
3263
 * port="pif_pci_reg_res_dsbl_i"
3264
 */
3265

3266
/* register address for bitfield reg_res_dsbl */
3267
#define pci_reg_res_dsbl_adr 0x00001000
3268
/* bitmask for bitfield reg_res_dsbl */
3269
#define pci_reg_res_dsbl_msk 0x20000000
3270
/* inverted bitmask for bitfield reg_res_dsbl */
3271
#define pci_reg_res_dsbl_mskn 0xdfffffff
3272
/* lower bit position of bitfield reg_res_dsbl */
3273
#define pci_reg_res_dsbl_shift 29
3274
/* width of bitfield reg_res_dsbl */
3275
#define pci_reg_res_dsbl_width 1
3276
/* default value of bitfield reg_res_dsbl */
3277
#define pci_reg_res_dsbl_default 0x1
3278

3279

3280
/* global microprocessor scratch pad definitions */
3281
#define glb_cpu_scratch_scp_adr(scratch_scp) (0x00000300u + (scratch_scp) * 0x4)
3282
/* global microprocessor scratch pad definitions */
3283
#define glb_cpu_no_reset_scratchpad_adr(idx) (0x00000380u + (idx) * 0x4)
3284

3285
/*!  @name Global Standard Control 1 Definitions
3286
*
3287
*   Preprocessor definitions for Global Standard Control 1
3288
*   Address: 0x00000000
3289
@{*/
3290
#define glb_standard_ctl1_adr 0x00000000u
3291
/*@}*/
3292

3293
/*!  @name Global Control 2 Definitions
3294
*
3295
*   Preprocessor definitions for Global Control 2
3296
*   Address: 0x00000404
3297
@{*/
3298
#define glb_ctl2_adr 0x00000404u
3299
/*@}*/
3300

3301
/*!  @name Global Daisy Chain Status 1 Definitions
3302
*
3303
*   Preprocessor definitions for Global Daisy Chain Status 1
3304
*   Address: 0x00000704
3305
@{*/
3306
#define glb_daisy_chain_status1_adr 0x00000704u
3307
/*@}*/
3308

3309
/* mif up mailbox execute operation */
3310
#define mif_mcp_up_mailbox_execute_operation_adr 0x00000200u
3311
#define mif_mcp_up_mailbox_execute_operation_msk 0x00008000u
3312
#define mif_mcp_up_mailbox_execute_operation_shift 15
3313

3314
/*  MIF uP Mailbox Busy */
3315
#define mif_mcp_up_mailbox_busy_adr 0x00000200u
3316
#define mif_mcp_up_mailbox_busy_msk 0x00000100u
3317
#define mif_mcp_up_mailbox_busy_shift 8
3318

3319
/* mif uP mailbox address [1f:2]  */
3320
#define mif_mcp_up_mailbox_addr_adr 0x00000208u
3321
/* mif uP mailbox data [1f:0] */
3322
#define mif_mcp_up_mailbox_data_adr 0x0000020cu
3323

3324
#define HW_ATL_RX_CTRL_ADDR_BEGIN_FL3L4   0x00005380
3325
#define HW_ATL_RX_SRCA_ADDR_BEGIN_FL3L4   0x000053B0
3326
#define HW_ATL_RX_DESTA_ADDR_BEGIN_FL3L4  0x000053D0
3327

3328
#define HW_ATL_RX_GET_ADDR_CTRL_FL3L4(location)  \
3329
	(HW_ATL_RX_CTRL_ADDR_BEGIN_FL3L4 + ((location) * 0x4))
3330
#define HW_ATL_RX_GET_ADDR_SRCA_FL3L4(location)  \
3331
	(HW_ATL_RX_SRCA_ADDR_BEGIN_FL3L4 + ((location) * 0x4))
3332
#define HW_ATL_RX_GET_ADDR_DESTA_FL3L4(location) \
3333
	(HW_ATL_RX_DESTA_ADDR_BEGIN_FL3L4 + ((location) * 0x4))
3334

3335
#endif /* HW_ATL_LLH_INTERNAL_H */
3336

3337
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