CoCalc -- ata-nvidia.c

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/dev/ata/chipsets/ata-nvidia.c
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1
/*-
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 * SPDX-License-Identifier: BSD-2-Clause
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 *
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 * Copyright (c) 1998 - 2008 Søren Schmidt <[email protected]>
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * 1. Redistributions of source code must retain the above copyright
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 *    notice, this list of conditions and the following disclaimer,
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 *    without modification, immediately at the beginning of the file.
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 * 2. Redistributions in binary form must reproduce the above copyright
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 *    notice, this list of conditions and the following disclaimer in the
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 *    documentation and/or other materials provided with the distribution.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#include <sys/param.h>
30
#include <sys/module.h>
31
#include <sys/systm.h>
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#include <sys/kernel.h>
33
#include <sys/ata.h>
34
#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sema.h>
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#include <sys/stdarg.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/ata/ata-all.h>
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#include <dev/ata/ata-pci.h>
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#include <ata_if.h>
51

52
/* local prototypes */
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static int ata_nvidia_chipinit(device_t dev);
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static int ata_nvidia_ch_attach(device_t dev);
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static int ata_nvidia_ch_attach_dumb(device_t dev);
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static int ata_nvidia_status(device_t dev);
57
static void ata_nvidia_reset(device_t dev);
58
static int ata_nvidia_setmode(device_t dev, int target, int mode);
59

60
/* misc defines */
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#define NV4             0x01
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#define NVQ             0x02
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#define NVAHCI          0x04
64

65
/*
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 * nVidia chipset support functions
67
 */
68
static int
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ata_nvidia_probe(device_t dev)
70
{
71
    struct ata_pci_controller *ctlr = device_get_softc(dev);
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    static const struct ata_chip_id ids[] =
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    {{ ATA_NFORCE1,         0, 0,       0, ATA_UDMA5, "nForce" },
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     { ATA_NFORCE2,         0, 0,       0, ATA_UDMA6, "nForce2" },
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     { ATA_NFORCE2_PRO,     0, 0,       0, ATA_UDMA6, "nForce2 Pro" },
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     { ATA_NFORCE2_PRO_S1,  0, 0,       0, ATA_SA150, "nForce2 Pro" },
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     { ATA_NFORCE3,         0, 0,       0, ATA_UDMA6, "nForce3" },
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     { ATA_NFORCE3_PRO,     0, 0,       0, ATA_UDMA6, "nForce3 Pro" },
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     { ATA_NFORCE3_PRO_S1,  0, 0,       0, ATA_SA150, "nForce3 Pro" },
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     { ATA_NFORCE3_PRO_S2,  0, 0,       0, ATA_SA150, "nForce3 Pro" },
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     { ATA_NFORCE_MCP04,    0, 0,       0, ATA_UDMA6, "nForce MCP" },
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     { ATA_NFORCE_MCP04_S1, 0, NV4,     0, ATA_SA150, "nForce MCP" },
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     { ATA_NFORCE_MCP04_S2, 0, NV4,     0, ATA_SA150, "nForce MCP" },
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     { ATA_NFORCE_CK804,    0, 0,       0, ATA_UDMA6, "nForce CK804" },
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     { ATA_NFORCE_CK804_S1, 0, NV4,     0, ATA_SA300, "nForce CK804" },
86
     { ATA_NFORCE_CK804_S2, 0, NV4,     0, ATA_SA300, "nForce CK804" },
87
     { ATA_NFORCE_MCP51,    0, 0,       0, ATA_UDMA6, "nForce MCP51" },
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     { ATA_NFORCE_MCP51_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP51" },
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     { ATA_NFORCE_MCP51_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP51" },
90
     { ATA_NFORCE_MCP55,    0, 0,       0, ATA_UDMA6, "nForce MCP55" },
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     { ATA_NFORCE_MCP55_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP55" },
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     { ATA_NFORCE_MCP55_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP55" },
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     { ATA_NFORCE_MCP61,    0, 0,       0, ATA_UDMA6, "nForce MCP61" },
94
     { ATA_NFORCE_MCP61_S1, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" },
95
     { ATA_NFORCE_MCP61_S2, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" },
96
     { ATA_NFORCE_MCP61_S3, 0, NV4|NVQ, 0, ATA_SA300, "nForce MCP61" },
97
     { ATA_NFORCE_MCP65,    0, 0,       0, ATA_UDMA6, "nForce MCP65" },
98
     { ATA_NFORCE_MCP65_A0, 0, NVAHCI,  0, ATA_SA300, "nForce MCP65" },
99
     { ATA_NFORCE_MCP65_A1, 0, NVAHCI,  0, ATA_SA300, "nForce MCP65" },
100
     { ATA_NFORCE_MCP65_A2, 0, NVAHCI,  0, ATA_SA300, "nForce MCP65" },
101
     { ATA_NFORCE_MCP65_A3, 0, NVAHCI,  0, ATA_SA300, "nForce MCP65" },
102
     { ATA_NFORCE_MCP65_A4, 0, NVAHCI,  0, ATA_SA300, "nForce MCP65" },
103
     { ATA_NFORCE_MCP65_A5, 0, NVAHCI,  0, ATA_SA300, "nForce MCP65" },
104
     { ATA_NFORCE_MCP65_A6, 0, NVAHCI,  0, ATA_SA300, "nForce MCP65" },
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     { ATA_NFORCE_MCP65_A7, 0, NVAHCI,  0, ATA_SA300, "nForce MCP65" },
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     { ATA_NFORCE_MCP67,    0, 0,       0, ATA_UDMA6, "nForce MCP67" },
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     { ATA_NFORCE_MCP67_A0, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
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     { ATA_NFORCE_MCP67_A1, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
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     { ATA_NFORCE_MCP67_A2, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
110
     { ATA_NFORCE_MCP67_A3, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
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     { ATA_NFORCE_MCP67_A4, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
112
     { ATA_NFORCE_MCP67_A5, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
113
     { ATA_NFORCE_MCP67_A6, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
114
     { ATA_NFORCE_MCP67_A7, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
115
     { ATA_NFORCE_MCP67_A8, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
116
     { ATA_NFORCE_MCP67_A9, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
117
     { ATA_NFORCE_MCP67_AA, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
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     { ATA_NFORCE_MCP67_AB, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
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     { ATA_NFORCE_MCP67_AC, 0, NVAHCI,  0, ATA_SA300, "nForce MCP67" },
120
     { ATA_NFORCE_MCP73,    0, 0,       0, ATA_UDMA6, "nForce MCP73" },
121
     { ATA_NFORCE_MCP73_A0, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
122
     { ATA_NFORCE_MCP73_A1, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
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     { ATA_NFORCE_MCP73_A2, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
124
     { ATA_NFORCE_MCP73_A3, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
125
     { ATA_NFORCE_MCP73_A4, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
126
     { ATA_NFORCE_MCP73_A5, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
127
     { ATA_NFORCE_MCP73_A6, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
128
     { ATA_NFORCE_MCP73_A7, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
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     { ATA_NFORCE_MCP73_A8, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
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     { ATA_NFORCE_MCP73_A9, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
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     { ATA_NFORCE_MCP73_AA, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
132
     { ATA_NFORCE_MCP73_AB, 0, NVAHCI,  0, ATA_SA300, "nForce MCP73" },
133
     { ATA_NFORCE_MCP77,    0, 0,       0, ATA_UDMA6, "nForce MCP77" },
134
     { ATA_NFORCE_MCP77_A0, 0, NVAHCI,  0, ATA_SA300, "nForce MCP77" },
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     { ATA_NFORCE_MCP77_A1, 0, NVAHCI,  0, ATA_SA300, "nForce MCP77" },
136
     { ATA_NFORCE_MCP77_A2, 0, NVAHCI,  0, ATA_SA300, "nForce MCP77" },
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     { ATA_NFORCE_MCP77_A3, 0, NVAHCI,  0, ATA_SA300, "nForce MCP77" },
138
     { ATA_NFORCE_MCP77_A4, 0, NVAHCI,  0, ATA_SA300, "nForce MCP77" },
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     { ATA_NFORCE_MCP77_A5, 0, NVAHCI,  0, ATA_SA300, "nForce MCP77" },
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     { ATA_NFORCE_MCP77_A6, 0, NVAHCI,  0, ATA_SA300, "nForce MCP77" },
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     { ATA_NFORCE_MCP77_A7, 0, NVAHCI,  0, ATA_SA300, "nForce MCP77" },
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     { ATA_NFORCE_MCP77_A8, 0, NVAHCI,  0, ATA_SA300, "nForce MCP77" },
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     { ATA_NFORCE_MCP77_A9, 0, NVAHCI,  0, ATA_SA300, "nForce MCP77" },
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     { ATA_NFORCE_MCP77_AA, 0, NVAHCI,  0, ATA_SA300, "nForce MCP77" },
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     { ATA_NFORCE_MCP77_AB, 0, NVAHCI,  0, ATA_SA300, "nForce MCP77" },
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     { ATA_NFORCE_MCP79_A0, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
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     { ATA_NFORCE_MCP79_A1, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
148
     { ATA_NFORCE_MCP79_A2, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
149
     { ATA_NFORCE_MCP79_A3, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
150
     { ATA_NFORCE_MCP79_A4, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
151
     { ATA_NFORCE_MCP79_A5, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
152
     { ATA_NFORCE_MCP79_A6, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
153
     { ATA_NFORCE_MCP79_A7, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
154
     { ATA_NFORCE_MCP79_A8, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
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     { ATA_NFORCE_MCP79_A9, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
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     { ATA_NFORCE_MCP79_AA, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
157
     { ATA_NFORCE_MCP79_AB, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
158
     { ATA_NFORCE_MCP89_A0, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
159
     { ATA_NFORCE_MCP89_A1, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
160
     { ATA_NFORCE_MCP89_A2, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
161
     { ATA_NFORCE_MCP89_A3, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
162
     { ATA_NFORCE_MCP89_A4, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
163
     { ATA_NFORCE_MCP89_A5, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
164
     { ATA_NFORCE_MCP89_A6, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
165
     { ATA_NFORCE_MCP89_A7, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
166
     { ATA_NFORCE_MCP89_A8, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
167
     { ATA_NFORCE_MCP89_A9, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
168
     { ATA_NFORCE_MCP89_AA, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
169
     { ATA_NFORCE_MCP89_AB, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
170
     { 0, 0, 0, 0, 0, 0}} ;
171

172
    if (pci_get_vendor(dev) != ATA_NVIDIA_ID)
173
	return ENXIO;
174

175
    if (!(ctlr->chip = ata_match_chip(dev, ids)))
176
	return ENXIO;
177

178
    if ((ctlr->chip->cfg1 & NVAHCI) &&
179
	    pci_get_subclass(dev) != PCIS_STORAGE_IDE)
180
	return (ENXIO);
181

182
    ata_set_desc(dev);
183
    ctlr->chipinit = ata_nvidia_chipinit;
184
    return (BUS_PROBE_LOW_PRIORITY);
185
}
186

187
static int
188
ata_nvidia_chipinit(device_t dev)
189
{
190
    struct ata_pci_controller *ctlr = device_get_softc(dev);
191

192
    if (ata_setup_interrupt(dev, ata_generic_intr))
193
	return ENXIO;
194

195
    if (ctlr->chip->cfg1 & NVAHCI) {
196
	ctlr->ch_attach = ata_nvidia_ch_attach_dumb;
197
	ctlr->setmode = ata_sata_setmode;
198
    } else if (ctlr->chip->max_dma >= ATA_SA150) {
199
	if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
200
	    ctlr->r_type2 = SYS_RES_IOPORT;
201
	else
202
	    ctlr->r_type2 = SYS_RES_MEMORY;
203
	ctlr->r_rid2 = PCIR_BAR(5);
204
	if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
205
						   &ctlr->r_rid2, RF_ACTIVE))) {
206
	    int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010;
207

208
	    ctlr->ch_attach = ata_nvidia_ch_attach;
209
	    ctlr->ch_detach = ata_pci_ch_detach;
210
	    ctlr->reset = ata_nvidia_reset;
211

212
	    /* enable control access */
213
	    pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
214
	    /* MCP55 seems to need some time to allow r_res2 read. */
215
	    DELAY(10);
216
	    if (ctlr->chip->cfg1 & NVQ) {
217
		/* clear interrupt status */
218
		ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
219

220
		/* enable device and PHY state change interrupts */
221
		ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
222

223
		/* disable NCQ support */
224
		ATA_OUTL(ctlr->r_res2, 0x0400,
225
			 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
226
	    } 
227
	    else {
228
		/* clear interrupt status */
229
		ATA_OUTB(ctlr->r_res2, offset, 0xff);
230

231
		/* enable device and PHY state change interrupts */
232
		ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
233
	    }
234
	}
235
	ctlr->setmode = ata_sata_setmode;
236
	ctlr->getrev = ata_sata_getrev;
237
    }
238
    else {
239
	/* disable prefetch, postwrite */
240
	pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
241
	ctlr->setmode = ata_nvidia_setmode;
242
    }
243
    return 0;
244
}
245

246
static int
247
ata_nvidia_ch_attach(device_t dev)
248
{
249
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
250
    struct ata_channel *ch = device_get_softc(dev);
251

252
    /* setup the usual register normal pci style */
253
    if (ata_pci_ch_attach(dev))
254
	return ENXIO;
255

256
    ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
257
    ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
258
    ch->r_io[ATA_SERROR].res = ctlr->r_res2;
259
    ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
260
    ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
261
    ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
262

263
    ch->hw.status = ata_nvidia_status;
264
    ch->flags |= ATA_NO_SLAVE;
265
    ch->flags |= ATA_SATA;
266
    return 0;
267
}
268

269
static int
270
ata_nvidia_ch_attach_dumb(device_t dev)
271
{
272
    struct ata_channel *ch = device_get_softc(dev);
273

274
    if (ata_pci_ch_attach(dev))
275
	return ENXIO;
276
    ch->flags |= ATA_SATA;
277
    return 0;
278
}
279

280
static int 
281
ata_nvidia_status(device_t dev)
282
{
283
    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
284
    struct ata_channel *ch = device_get_softc(dev);
285
    int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010;
286
    int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2);
287
    u_int32_t istatus;
288

289
    /* get interrupt status */
290
    if (ctlr->chip->cfg1 & NVQ)
291
	istatus = ATA_INL(ctlr->r_res2, offset);
292
    else
293
	istatus = ATA_INB(ctlr->r_res2, offset);
294

295
    /* do we have any PHY events ? */
296
    if (istatus & (0x0c << shift))
297
	ata_sata_phy_check_events(dev, -1);
298

299
    /* clear interrupt(s) */
300
    if (ctlr->chip->cfg1 & NVQ)
301
	ATA_OUTL(ctlr->r_res2, offset, (0x0f << shift) | 0x00f000f0);
302
    else
303
	ATA_OUTB(ctlr->r_res2, offset, (0x0f << shift));
304

305
    /* do we have any device action ? */
306
    return (istatus & (0x01 << shift));
307
}
308

309
static void
310
ata_nvidia_reset(device_t dev)
311
{
312
    struct ata_channel *ch = device_get_softc(dev);
313

314
    if (ata_sata_phy_reset(dev, -1, 1))
315
	ata_generic_reset(dev);
316
    else
317
	ch->devices = 0;
318
}
319

320
static int
321
ata_nvidia_setmode(device_t dev, int target, int mode)
322
{
323
	device_t parent = device_get_parent(dev);
324
	struct ata_pci_controller *ctlr = device_get_softc(parent);
325
	struct ata_channel *ch = device_get_softc(dev);
326
	int devno = (ch->unit << 1) + target;
327
	int piomode;
328
	static const uint8_t timings[] =
329
	    { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 };
330
	static const uint8_t modes[] =
331
	    { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 };
332
	int reg = 0x63 - devno;
333

334
	mode = min(mode, ctlr->chip->max_dma);
335

336
	if (mode >= ATA_UDMA0) {
337
	    pci_write_config(parent, reg, modes[mode & ATA_MODE_MASK], 1);
338
	    piomode = ATA_PIO4;
339
	} else {
340
	    pci_write_config(parent, reg, 0x8b, 1);
341
	    piomode = mode;
342
	}
343
	pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(piomode)], 1);
344
	return (mode);
345
}
346

347
ATA_DECLARE_DRIVER(ata_nvidia);
348

349
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