Path: blob/main/sys/dev/ath/ath_hal/ar5210/ar5210.h
39566 views
/*-1* SPDX-License-Identifier: ISC2*3* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting4* Copyright (c) 2002-2004 Atheros Communications, Inc.5*6* Permission to use, copy, modify, and/or distribute this software for any7* purpose with or without fee is hereby granted, provided that the above8* copyright notice and this permission notice appear in all copies.9*10* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES11* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF12* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR13* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES14* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN15* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF16* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.17*/18#ifndef _ATH_AR5210_H_19#define _ATH_AR5210_H_2021#define AR5210_MAGIC 0x199801242223#if 024/*25* RTS_ENABLE includes LONG_PKT because they essentially26* imply the same thing, and are set or not set together27* for this chip28*/29#define AR5210_TXD_CTRL_A_HDR_LEN(_val) (((_val) ) & 0x0003f)30#define AR5210_TXD_CTRL_A_TX_RATE(_val) (((_val) << 6) & 0x003c0)31#define AR5210_TXD_CTRL_A_RTS_ENABLE ( 0x00c00)32#define AR5210_TXD_CTRL_A_CLEAR_DEST_MASK(_val) (((_val) << 12) & 0x01000)33#define AR5210_TXD_CTRL_A_ANT_MODE(_val) (((_val) << 13) & 0x02000)34#define AR5210_TXD_CTRL_A_PKT_TYPE(_val) (((_val) << 14) & 0x1c000)35#define AR5210_TXD_CTRL_A_INT_REQ ( 0x20000)36#define AR5210_TXD_CTRL_A_KEY_VALID ( 0x40000)37#define AR5210_TXD_CTRL_B_KEY_ID(_val) (((_val) ) & 0x0003f)38#define AR5210_TXD_CTRL_B_RTS_DURATION(_val) (((_val) << 6) & 0x7ffc0)39#endif4041#define INIT_CONFIG_STATUS 0x0000000042#define INIT_ACKTOPS 0x0000000843#define INIT_BCON_CNTRL_REG 0x0000000044#define INIT_SLOT_TIME 0x0000016845#define INIT_SLOT_TIME_TURBO 0x000001e0 /* More aggressive turbo slot timing = 6 us */46#define INIT_ACK_CTS_TIMEOUT 0x0400040047#define INIT_ACK_CTS_TIMEOUT_TURBO 0x080008004849#define INIT_USEC 0x2750#define INIT_USEC_TURBO 0x4f51#define INIT_USEC_32 0x1f52#define INIT_TX_LATENCY 0x3653#define INIT_RX_LATENCY 0x1D54#define INIT_TRANSMIT_LATENCY \55((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \56(INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \57(INIT_USEC_32 << 7) | INIT_USEC )58#define INIT_TRANSMIT_LATENCY_TURBO \59((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \60(INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \61(INIT_USEC_32 << 7) | INIT_USEC_TURBO)6263#define INIT_SIFS 0x230 /* = 16 us - 2 us */64#define INIT_SIFS_TURBO 0x1E0 /* More aggressive turbo SIFS timing - 8 us - 2 us */6566/*67* Various fifo fill before Tx start, in 64-byte units68* i.e. put the frame in the air while still DMAing69*/70#define MIN_TX_FIFO_THRESHOLD 0x171#define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1)7273#define INIT_NEXT_CFP_START 0xffffffff7475#define INIT_BEACON_PERIOD 0xffff76#define INIT_BEACON_EN 0 /* this should be set by AP only when it's ready */77#define INIT_BEACON_CONTROL \78((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \79(INIT_TIM_OFFSET<<16) | INIT_BEACON_PERIOD)8081#define INIT_RSSI_THR 0x00000700 /* Missed beacon counter initialized to max value of 7 */82#define INIT_ProgIFS 0x398 /* PIFS - 2us */83#define INIT_ProgIFS_TURBO 0x3C084#define INIT_EIFS 0xd7085#define INIT_EIFS_TURBO 0x1ae086#define INIT_CARR_SENSE_EN 187#define INIT_PROTO_TIME_CNTRL ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS << 12) | \88(INIT_ProgIFS) )89#define INIT_PROTO_TIME_CNTRL_TURBO ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS_TURBO << 12) | \90(INIT_ProgIFS_TURBO) )9192#define AR5210_MAX_RATE_POWER 609394#undef HAL_NUM_TX_QUEUES /* from ah.h */95#define HAL_NUM_TX_QUEUES 39697struct ath_hal_5210 {98struct ath_hal_private ah_priv; /* base definitions */99100uint8_t ah_macaddr[IEEE80211_ADDR_LEN];101/*102* Runtime state.103*/104uint32_t ah_maskReg; /* shadow of IMR+IER regs */105uint32_t ah_txOkInterruptMask;106uint32_t ah_txErrInterruptMask;107uint32_t ah_txDescInterruptMask;108uint32_t ah_txEolInterruptMask;109uint32_t ah_txUrnInterruptMask;110uint8_t ah_bssid[IEEE80211_ADDR_LEN];111HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; /* beacon+cab+data */112/*113* Station mode support.114*/115uint32_t ah_staId1Defaults; /* STA_ID1 default settings */116uint32_t ah_rssiThr; /* RSSI_THR settings */117118u_int ah_sifstime; /* user-specified sifs time */119u_int ah_slottime; /* user-specified slot time */120u_int ah_acktimeout; /* user-specified ack timeout */121u_int ah_ctstimeout; /* user-specified cts timeout */122123uint16_t ah_associd; /* association id */124};125#define AH5210(ah) ((struct ath_hal_5210 *)(ah))126127struct ath_hal;128129extern void ar5210Detach(struct ath_hal *ah);130extern HAL_BOOL ar5210Reset(struct ath_hal *, HAL_OPMODE,131struct ieee80211_channel *, HAL_BOOL bChannelChange,132HAL_RESET_TYPE, HAL_STATUS *);133extern void ar5210SetPCUConfig(struct ath_hal *);134extern HAL_BOOL ar5210PhyDisable(struct ath_hal *);135extern HAL_BOOL ar5210Disable(struct ath_hal *);136extern HAL_BOOL ar5210ChipReset(struct ath_hal *, struct ieee80211_channel *);137extern HAL_BOOL ar5210PerCalibration(struct ath_hal *, struct ieee80211_channel *, HAL_BOOL *);138extern HAL_BOOL ar5210PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,139u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);140extern HAL_BOOL ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *);141extern int16_t ar5210GetNoiseFloor(struct ath_hal *);142extern int16_t ar5210GetNfAdjust(struct ath_hal *,143const HAL_CHANNEL_INTERNAL *);144extern HAL_BOOL ar5210SetTxPowerLimit(struct ath_hal *, uint32_t limit);145extern HAL_BOOL ar5210SetTransmitPower(struct ath_hal *,146const struct ieee80211_channel *);147extern HAL_BOOL ar5210CalNoiseFloor(struct ath_hal *, HAL_CHANNEL_INTERNAL *);148extern HAL_BOOL ar5210ResetDma(struct ath_hal *, HAL_OPMODE);149150extern HAL_BOOL ar5210SetTxQueueProps(struct ath_hal *ah, int q,151const HAL_TXQ_INFO *qInfo);152extern HAL_BOOL ar5210GetTxQueueProps(struct ath_hal *ah, int q,153HAL_TXQ_INFO *qInfo);154extern int ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,155const HAL_TXQ_INFO *qInfo);156extern HAL_BOOL ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q);157extern HAL_BOOL ar5210ResetTxQueue(struct ath_hal *ah, u_int q);158extern uint32_t ar5210GetTxDP(struct ath_hal *, u_int);159extern HAL_BOOL ar5210SetTxDP(struct ath_hal *, u_int, uint32_t txdp);160extern HAL_BOOL ar5210UpdateTxTrigLevel(struct ath_hal *, HAL_BOOL);161extern uint32_t ar5210NumTxPending(struct ath_hal *, u_int);162extern HAL_BOOL ar5210StartTxDma(struct ath_hal *, u_int);163extern HAL_BOOL ar5210StopTxDma(struct ath_hal *, u_int);164extern HAL_BOOL ar5210SetupTxDesc(struct ath_hal *, struct ath_desc *,165u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,166u_int txRate0, u_int txRetries0,167u_int keyIx, u_int antMode, u_int flags,168u_int rtsctsRate, u_int rtsctsDuration,169u_int compicvLen, u_int compivLen, u_int comp);170extern HAL_BOOL ar5210SetupXTxDesc(struct ath_hal *, struct ath_desc *,171u_int txRate1, u_int txRetries1,172u_int txRate2, u_int txRetries2,173u_int txRate3, u_int txRetries3);174extern HAL_BOOL ar5210FillTxDesc(struct ath_hal *, struct ath_desc *,175HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList,176u_int descId, u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg,177const struct ath_desc *ds0);178extern HAL_STATUS ar5210ProcTxDesc(struct ath_hal *,179struct ath_desc *, struct ath_tx_status *);180extern void ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *);181extern void ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);182extern HAL_BOOL ar5210GetTxCompletionRates(struct ath_hal *ah,183const struct ath_desc *, int *rates, int *tries);184extern void ar5210SetTxDescLink(struct ath_hal *ah, void *ds,185uint32_t link);186extern void ar5210GetTxDescLink(struct ath_hal *ah, void *ds,187uint32_t *link);188extern void ar5210GetTxDescLinkPtr(struct ath_hal *ah, void *ds,189uint32_t **linkptr);190191extern uint32_t ar5210GetRxDP(struct ath_hal *, HAL_RX_QUEUE);192extern void ar5210SetRxDP(struct ath_hal *, uint32_t rxdp, HAL_RX_QUEUE);193extern void ar5210EnableReceive(struct ath_hal *);194extern HAL_BOOL ar5210StopDmaReceive(struct ath_hal *);195extern void ar5210StartPcuReceive(struct ath_hal *, HAL_BOOL);196extern void ar5210StopPcuReceive(struct ath_hal *);197extern void ar5210SetMulticastFilter(struct ath_hal *,198uint32_t filter0, uint32_t filter1);199extern HAL_BOOL ar5210ClrMulticastFilterIndex(struct ath_hal *, uint32_t);200extern HAL_BOOL ar5210SetMulticastFilterIndex(struct ath_hal *, uint32_t);201extern uint32_t ar5210GetRxFilter(struct ath_hal *);202extern void ar5210SetRxFilter(struct ath_hal *, uint32_t);203extern HAL_BOOL ar5210SetupRxDesc(struct ath_hal *, struct ath_desc *,204uint32_t, u_int flags);205extern HAL_STATUS ar5210ProcRxDesc(struct ath_hal *, struct ath_desc *,206uint32_t, struct ath_desc *, uint64_t,207struct ath_rx_status *);208209extern void ar5210GetMacAddress(struct ath_hal *, uint8_t *);210extern HAL_BOOL ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *);211extern void ar5210GetBssIdMask(struct ath_hal *, uint8_t *);212extern HAL_BOOL ar5210SetBssIdMask(struct ath_hal *, const uint8_t *);213extern HAL_BOOL ar5210EepromRead(struct ath_hal *, u_int off, uint16_t *data);214extern HAL_BOOL ar5210EepromWrite(struct ath_hal *, u_int off, uint16_t data);215extern HAL_BOOL ar5210SetRegulatoryDomain(struct ath_hal *,216uint16_t, HAL_STATUS *);217extern u_int ar5210GetWirelessModes(struct ath_hal *ah);218extern void ar5210EnableRfKill(struct ath_hal *);219extern HAL_BOOL ar5210GpioCfgInput(struct ath_hal *, uint32_t gpio);220extern HAL_BOOL ar5210GpioCfgOutput(struct ath_hal *, uint32_t gpio,221HAL_GPIO_MUX_TYPE);222extern uint32_t ar5210GpioGet(struct ath_hal *, uint32_t gpio);223extern HAL_BOOL ar5210GpioSet(struct ath_hal *, uint32_t gpio, uint32_t);224extern void ar5210Gpio0SetIntr(struct ath_hal *, u_int, uint32_t ilevel);225extern void ar5210SetLedState(struct ath_hal *, HAL_LED_STATE);226extern u_int ar5210GetDefAntenna(struct ath_hal *);227extern void ar5210SetDefAntenna(struct ath_hal *, u_int);228extern HAL_ANT_SETTING ar5210GetAntennaSwitch(struct ath_hal *);229extern HAL_BOOL ar5210SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);230extern void ar5210WriteAssocid(struct ath_hal *,231const uint8_t *bssid, uint16_t assocId);232extern uint32_t ar5210GetTsf32(struct ath_hal *);233extern uint64_t ar5210GetTsf64(struct ath_hal *);234extern void ar5210ResetTsf(struct ath_hal *);235extern uint32_t ar5210GetRandomSeed(struct ath_hal *);236extern HAL_BOOL ar5210DetectCardPresent(struct ath_hal *);237extern void ar5210UpdateMibCounters(struct ath_hal *, HAL_MIB_STATS *);238extern void ar5210EnableHwEncryption(struct ath_hal *);239extern void ar5210DisableHwEncryption(struct ath_hal *);240extern HAL_RFGAIN ar5210GetRfgain(struct ath_hal *);241extern HAL_BOOL ar5210SetSifsTime(struct ath_hal *, u_int);242extern u_int ar5210GetSifsTime(struct ath_hal *);243extern HAL_BOOL ar5210SetSlotTime(struct ath_hal *, u_int);244extern u_int ar5210GetSlotTime(struct ath_hal *);245extern HAL_BOOL ar5210SetAckTimeout(struct ath_hal *, u_int);246extern u_int ar5210GetAckTimeout(struct ath_hal *);247extern HAL_BOOL ar5210SetAckCTSRate(struct ath_hal *, u_int);248extern u_int ar5210GetAckCTSRate(struct ath_hal *);249extern HAL_BOOL ar5210SetCTSTimeout(struct ath_hal *, u_int);250extern u_int ar5210GetCTSTimeout(struct ath_hal *);251extern HAL_BOOL ar5210SetDecompMask(struct ath_hal *, uint16_t, int);252void ar5210SetCoverageClass(struct ath_hal *, uint8_t, int);253extern HAL_STATUS ar5210SetQuiet(struct ath_hal *, uint32_t, uint32_t,254uint32_t, HAL_QUIET_FLAG);255extern HAL_STATUS ar5210GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,256uint32_t, uint32_t *);257extern HAL_BOOL ar5210SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,258uint32_t, uint32_t, HAL_STATUS *);259extern HAL_BOOL ar5210GetDiagState(struct ath_hal *ah, int request,260const void *args, uint32_t argsize,261void **result, uint32_t *resultsize);262extern uint32_t ar5210Get11nExtBusy(struct ath_hal *);263extern HAL_BOOL ar5210GetMibCycleCounts(struct ath_hal *,264HAL_SURVEY_SAMPLE *);265extern void ar5210SetChainMasks(struct ath_hal *, uint32_t, uint32_t);266extern void ar5210EnableDfs(struct ath_hal *, HAL_PHYERR_PARAM *);267extern void ar5210GetDfsThresh(struct ath_hal *, HAL_PHYERR_PARAM *);268extern void ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val);269extern void ar5210SetNav(struct ath_hal *ah, u_int val);270extern u_int ar5210GetNav(struct ath_hal *ah);271272extern u_int ar5210GetKeyCacheSize(struct ath_hal *);273extern HAL_BOOL ar5210IsKeyCacheEntryValid(struct ath_hal *, uint16_t);274extern HAL_BOOL ar5210ResetKeyCacheEntry(struct ath_hal *, uint16_t entry);275extern HAL_BOOL ar5210SetKeyCacheEntry(struct ath_hal *, uint16_t entry,276const HAL_KEYVAL *, const uint8_t *mac, int xorKey);277extern HAL_BOOL ar5210SetKeyCacheEntryMac(struct ath_hal *,278uint16_t, const uint8_t *);279280extern HAL_BOOL ar5210SetPowerMode(struct ath_hal *, HAL_POWER_MODE mode,281int setChip);282extern HAL_POWER_MODE ar5210GetPowerMode(struct ath_hal *);283284extern void ar5210SetBeaconTimers(struct ath_hal *,285const HAL_BEACON_TIMERS *);286extern void ar5210BeaconInit(struct ath_hal *, uint32_t, uint32_t);287extern void ar5210SetStaBeaconTimers(struct ath_hal *,288const HAL_BEACON_STATE *);289extern void ar5210ResetStaBeaconTimers(struct ath_hal *);290extern uint64_t ar5210GetNextTBTT(struct ath_hal *);291292extern HAL_BOOL ar5210IsInterruptPending(struct ath_hal *);293extern HAL_BOOL ar5210GetPendingInterrupts(struct ath_hal *, HAL_INT *);294extern HAL_INT ar5210GetInterrupts(struct ath_hal *);295extern HAL_INT ar5210SetInterrupts(struct ath_hal *, HAL_INT ints);296297extern const HAL_RATE_TABLE *ar5210GetRateTable(struct ath_hal *, u_int mode);298299extern HAL_BOOL ar5210AniControl(struct ath_hal *, HAL_ANI_CMD, int );300extern void ar5210AniPoll(struct ath_hal *, const struct ieee80211_channel *);301extern void ar5210RxMonitor(struct ath_hal *, const HAL_NODE_STATS *,302const struct ieee80211_channel *);303extern void ar5210MibEvent(struct ath_hal *, const HAL_NODE_STATS *);304#endif /* _ATH_AR5210_H_ */305306307