Path: blob/main/sys/dev/ath/ath_hal/ar5210/ar5210phy.h
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/*-1* SPDX-License-Identifier: ISC2*3* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting4* Copyright (c) 2002-2004 Atheros Communications, Inc.5*6* Permission to use, copy, modify, and/or distribute this software for any7* purpose with or without fee is hereby granted, provided that the above8* copyright notice and this permission notice appear in all copies.9*10* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES11* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF12* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR13* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES14* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN15* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF16* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.17*/18#ifndef _DEV_ATH_AR5210PHY_H19#define _DEV_ATH_AR5210PHY_H2021/*22* Definitions for the PHY on the Atheros AR5210 parts.23*/2425/* PHY Registers */26#define AR_PHY_BASE 0x9800 /* PHY register base */27#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))2829#define AR_PHY_FRCTL 0x9804 /* PHY frame control */30#define AR_PHY_TURBO_MODE 0x00000001 /* PHY turbo mode */31#define AR_PHY_TURBO_SHORT 0x00000002 /* PHY turbo short symbol */32#define AR_PHY_TIMING_ERR 0x01000000 /* Detect PHY timing error */33#define AR_PHY_PARITY_ERR 0x02000000 /* Detect signal parity err */34#define AR_PHY_ILLRATE_ERR 0x04000000 /* Detect PHY illegal rate */35#define AR_PHY_ILLLEN_ERR 0x08000000 /* Detect PHY illegal length */36#define AR_PHY_SERVICE_ERR 0x20000000 /* Detect PHY nonzero service */37#define AR_PHY_TXURN_ERR 0x40000000 /* DetectPHY TX underrun */38#define AR_PHY_FRCTL_BITS \39"\20\1TURBO_MODE\2TURBO_SHORT\30TIMING_ERR\31PARITY_ERR\32ILLRATE_ERR"\40"\33ILLEN_ERR\35SERVICE_ERR\36TXURN_ERR"4142#define AR_PHY_AGC 0x9808 /* PHY AGC command */43#define AR_PHY_AGC_DISABLE 0x08000000 /* Disable PHY AGC */44#define AR_PHY_AGC_BITS "\20\33DISABLE"4546#define AR_PHY_CHIPID 0x9818 /* PHY chip revision */4748#define AR_PHY_ACTIVE 0x981c /* PHY activation */49#define AR_PHY_ENABLE 0x00000001 /* activate PHY */50#define AR_PHY_DISABLE 0x00000002 /* deactivate PHY */51#define AR_PHY_ACTIVE_BITS "\20\1ENABLE\2DISABLE"5253#define AR_PHY_AGCCTL 0x9860 /* PHY calibration and noise floor */54#define AR_PHY_AGC_CAL 0x00000001 /* PHY internal calibration */55#define AR_PHY_AGC_NF 0x00000002 /* calc PHY noise-floor */56#define AR_PHY_AGCCTL_BITS "\20\1CAL\2NF"5758#endif /* _DEV_ATH_AR5210PHY_H */596061