Path: blob/main/sys/dev/ath/ath_hal/ar5416/ar5416desc.h
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/*-1* SPDX-License-Identifier: ISC2*3* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting4* Copyright (c) 2002-2008 Atheros Communications, Inc.5*6* Permission to use, copy, modify, and/or distribute this software for any7* purpose with or without fee is hereby granted, provided that the above8* copyright notice and this permission notice appear in all copies.9*10* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES11* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF12* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR13* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES14* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN15* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF16* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.17*/18#ifndef _ATH_AR5416_DESC_H_19#define _ATH_AR5416_DESC_H_2021/*22* Hardware-specific descriptor structures.23*/2425/* XXX Need to replace this with a dynamic26* method of determining Owl2 if possible27*/28#define _get_index(_ah) ( IS_5416V1(_ah) ? -4 : 0 )29#define AR5416_DS_TXSTATUS(_ah, _ads) \30((uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)]))31#define AR5416_DS_TXSTATUS_CONST(_ah, _ads) \32((const uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)]))3334#define AR5416_NUM_TX_STATUS 10 /* Number of TX status words */35/* Clear the whole descriptor */36#define AR5416_DESC_TX_CTL_SZ sizeof(struct ar5416_tx_desc)3738struct ar5416_tx_desc { /* tx desc has 12 control words + 10 status words */39uint32_t ctl2;40uint32_t ctl3;41uint32_t ctl4;42uint32_t ctl5;43uint32_t ctl6;44uint32_t ctl7;45uint32_t ctl8;46uint32_t ctl9;47uint32_t ctl10;48uint32_t ctl11;49uint32_t status[AR5416_NUM_TX_STATUS];50};5152struct ar5416_rx_desc { /* rx desc has 2 control words + 9 status words */53uint32_t status0;54uint32_t status1;55uint32_t status2;56uint32_t status3;57uint32_t status4;58uint32_t status5;59uint32_t status6;60uint32_t status7;61uint32_t status8;62};6364struct ar5416_desc {65uint32_t ds_link; /* link pointer */66uint32_t ds_data; /* data buffer pointer */67uint32_t ds_ctl0; /* DMA control 0 */68uint32_t ds_ctl1; /* DMA control 1 */69union {70struct ar5416_tx_desc tx;71struct ar5416_rx_desc rx;72} u;73} __packed;74#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))75#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))7677#define ds_ctl2 u.tx.ctl278#define ds_ctl3 u.tx.ctl379#define ds_ctl4 u.tx.ctl480#define ds_ctl5 u.tx.ctl581#define ds_ctl6 u.tx.ctl682#define ds_ctl7 u.tx.ctl783#define ds_ctl8 u.tx.ctl884#define ds_ctl9 u.tx.ctl985#define ds_ctl10 u.tx.ctl1086#define ds_ctl11 u.tx.ctl118788#define ds_rxstatus0 u.rx.status089#define ds_rxstatus1 u.rx.status190#define ds_rxstatus2 u.rx.status291#define ds_rxstatus3 u.rx.status392#define ds_rxstatus4 u.rx.status493#define ds_rxstatus5 u.rx.status594#define ds_rxstatus6 u.rx.status695#define ds_rxstatus7 u.rx.status796#define ds_rxstatus8 u.rx.status89798/***********99* TX Desc *100***********/101102/* ds_ctl0 */103#define AR_FrameLen 0x00000fff104#define AR_VirtMoreFrag 0x00001000105#define AR_TxCtlRsvd00 0x0000e000106#define AR_XmitPower 0x003f0000107#define AR_XmitPower_S 16108#define AR_RTSEnable 0x00400000109#define AR_VEOL 0x00800000110#define AR_ClrDestMask 0x01000000111#define AR_TxCtlRsvd01 0x1e000000112#define AR_TxIntrReq 0x20000000113#define AR_DestIdxValid 0x40000000114#define AR_CTSEnable 0x80000000115116/* ds_ctl1 */117#define AR_BufLen 0x00000fff118#define AR_TxMore 0x00001000119#define AR_DestIdx 0x000fe000120#define AR_DestIdx_S 13121#define AR_FrameType 0x00f00000122#define AR_FrameType_S 20123#define AR_NoAck 0x01000000124#define AR_InsertTS 0x02000000125#define AR_CorruptFCS 0x04000000126#define AR_ExtOnly 0x08000000127#define AR_ExtAndCtl 0x10000000128#define AR_MoreAggr 0x20000000129#define AR_IsAggr 0x40000000130#define AR_MoreRifs 0x80000000131132/* ds_ctl2 */133#define AR_BurstDur 0x00007fff134#define AR_BurstDur_S 0135#define AR_DurUpdateEn 0x00008000136#define AR_XmitDataTries0 0x000f0000137#define AR_XmitDataTries0_S 16138#define AR_XmitDataTries1 0x00f00000139#define AR_XmitDataTries1_S 20140#define AR_XmitDataTries2 0x0f000000141#define AR_XmitDataTries2_S 24142#define AR_XmitDataTries3 0xf0000000143#define AR_XmitDataTries3_S 28144145/* ds_ctl3 */146#define AR_XmitRate0 0x000000ff147#define AR_XmitRate0_S 0148#define AR_XmitRate1 0x0000ff00149#define AR_XmitRate1_S 8150#define AR_XmitRate2 0x00ff0000151#define AR_XmitRate2_S 16152#define AR_XmitRate3 0xff000000153#define AR_XmitRate3_S 24154155/* ds_ctl4 */156#define AR_PacketDur0 0x00007fff157#define AR_PacketDur0_S 0158#define AR_RTSCTSQual0 0x00008000159#define AR_PacketDur1 0x7fff0000160#define AR_PacketDur1_S 16161#define AR_RTSCTSQual1 0x80000000162163/* ds_ctl5 */164#define AR_PacketDur2 0x00007fff165#define AR_PacketDur2_S 0166#define AR_RTSCTSQual2 0x00008000167#define AR_PacketDur3 0x7fff0000168#define AR_PacketDur3_S 16169#define AR_RTSCTSQual3 0x80000000170171/* ds_ctl6 */172#define AR_AggrLen 0x0000ffff173#define AR_AggrLen_S 0174#define AR_TxCtlRsvd60 0x00030000175#define AR_PadDelim 0x03fc0000176#define AR_PadDelim_S 18177#define AR_EncrType 0x0c000000178#define AR_EncrType_S 26179#define AR_TxCtlRsvd61 0xf0000000180181/* ds_ctl7 */182#define AR_2040_0 0x00000001183#define AR_GI0 0x00000002184#define AR_ChainSel0 0x0000001c185#define AR_ChainSel0_S 2186#define AR_2040_1 0x00000020187#define AR_GI1 0x00000040188#define AR_ChainSel1 0x00000380189#define AR_ChainSel1_S 7190#define AR_2040_2 0x00000400191#define AR_GI2 0x00000800192#define AR_ChainSel2 0x00007000193#define AR_ChainSel2_S 12194#define AR_2040_3 0x00008000195#define AR_GI3 0x00010000196#define AR_ChainSel3 0x000e0000197#define AR_ChainSel3_S 17198#define AR_RTSCTSRate 0x0ff00000199#define AR_RTSCTSRate_S 20200#define AR_STBC0 0x10000000201#define AR_STBC1 0x20000000202#define AR_STBC2 0x40000000203#define AR_STBC3 0x80000000204205/* ds_ctl8 */206#define AR_AntCtl0 0x00ffffff207#define AR_AntCtl0_S 0208/* Xmit 0 TPC is AR_XmitPower in ctl0 */209210/* ds_ctl9 */211#define AR_AntCtl1 0x00ffffff212#define AR_AntCtl1_S 0213#define AR_XmitPower1 0xff000000214#define AR_XmitPower1_S 24215216/* ds_ctl10 */217#define AR_AntCtl2 0x00ffffff218#define AR_AntCtl2_S 0219#define AR_XmitPower2 0xff000000220#define AR_XmitPower2_S 24221222/* ds_ctl11 */223#define AR_AntCtl3 0x00ffffff224#define AR_AntCtl3_S 0225#define AR_XmitPower3 0xff000000226#define AR_XmitPower3_S 24227228/*************229* TX Status *230*************/231232/* ds_status0 */233#define AR_TxRSSIAnt00 0x000000ff234#define AR_TxRSSIAnt00_S 0235#define AR_TxRSSIAnt01 0x0000ff00236#define AR_TxRSSIAnt01_S 8237#define AR_TxRSSIAnt02 0x00ff0000238#define AR_TxRSSIAnt02_S 16239#define AR_TxStatusRsvd00 0x3f000000240#define AR_TxBaStatus 0x40000000241#define AR_TxStatusRsvd01 0x80000000242243/* ds_status1 */244#define AR_FrmXmitOK 0x00000001245#define AR_ExcessiveRetries 0x00000002246#define AR_FIFOUnderrun 0x00000004247#define AR_Filtered 0x00000008248#define AR_RTSFailCnt 0x000000f0249#define AR_RTSFailCnt_S 4250#define AR_DataFailCnt 0x00000f00251#define AR_DataFailCnt_S 8252#define AR_VirtRetryCnt 0x0000f000253#define AR_VirtRetryCnt_S 12254#define AR_TxDelimUnderrun 0x00010000255#define AR_TxDelimUnderrun_S 13256#define AR_TxDataUnderrun 0x00020000257#define AR_TxDataUnderrun_S 14258#define AR_DescCfgErr 0x00040000259#define AR_DescCfgErr_S 15260#define AR_TxTimerExpired 0x00080000261#define AR_TxStatusRsvd10 0xfff00000262263/* ds_status2 */264#define AR_SendTimestamp(_ptr) (_ptr)[2]265266/* ds_status3 */267#define AR_BaBitmapLow(_ptr) (_ptr)[3]268269/* ds_status4 */270#define AR_BaBitmapHigh(_ptr) (_ptr)[4]271272/* ds_status5 */273#define AR_TxRSSIAnt10 0x000000ff274#define AR_TxRSSIAnt10_S 0275#define AR_TxRSSIAnt11 0x0000ff00276#define AR_TxRSSIAnt11_S 8277#define AR_TxRSSIAnt12 0x00ff0000278#define AR_TxRSSIAnt12_S 16279#define AR_TxRSSICombined 0xff000000280#define AR_TxRSSICombined_S 24281282/* ds_status6 */283#define AR_TxEVM0(_ptr) (_ptr)[6]284285/* ds_status7 */286#define AR_TxEVM1(_ptr) (_ptr)[7]287288/* ds_status8 */289#define AR_TxEVM2(_ptr) (_ptr)[8]290291/* ds_status9 */292#define AR_TxDone 0x00000001293#define AR_SeqNum 0x00001ffe294#define AR_SeqNum_S 1295#define AR_TxStatusRsvd80 0x0001e000296#define AR_TxOpExceeded 0x00020000297#define AR_TxStatusRsvd81 0x001c0000298#define AR_FinalTxIdx 0x00600000299#define AR_FinalTxIdx_S 21300#define AR_TxStatusRsvd82 0x01800000301#define AR_PowerMgmt 0x02000000302#define AR_TxTid 0xf0000000303#define AR_TxTid_S 28304#define AR_TxStatusRsvd83 0xfc000000305306/***********307* RX Desc *308***********/309310/* ds_ctl0 */311#define AR_RxCTLRsvd00 0xffffffff312313/* ds_ctl1 */314#define AR_BufLen 0x00000fff315#define AR_RxCtlRsvd00 0x00001000316#define AR_RxIntrReq 0x00002000317#define AR_RxCtlRsvd01 0xffffc000318319/*************320* Rx Status *321*************/322323/* ds_status0 */324#define AR_RxRSSIAnt00 0x000000ff325#define AR_RxRSSIAnt00_S 0326#define AR_RxRSSIAnt01 0x0000ff00327#define AR_RxRSSIAnt01_S 8328#define AR_RxRSSIAnt02 0x00ff0000329#define AR_RxRSSIAnt02_S 16330/* Rev specific */331/* Owl 1.x only */332#define AR_RxStatusRsvd00 0xff000000333/* Owl 2.x only */334#define AR_RxRate 0xff000000335#define AR_RxRate_S 24336337/* ds_status1 */338#define AR_DataLen 0x00000fff339#define AR_RxMore 0x00001000340#define AR_NumDelim 0x003fc000341#define AR_NumDelim_S 14342#define AR_RxStatusRsvd10 0xff800000343344/* ds_status2 */345#define AR_RcvTimestamp ds_rxstatus2346347/* ds_status3 */348#define AR_GI 0x00000001349#define AR_2040 0x00000002350/* Rev specific */351/* Owl 1.x only */352#define AR_RxRateV1 0x000003fc353#define AR_RxRateV1_S 2354#define AR_Parallel40 0x00000400355#define AR_RxStatusRsvd30 0xfffff800356/* Owl 2.x only */357#define AR_DupFrame 0x00000004358#define AR_STBCFrame 0x00000008359#define AR_RxAntenna 0xffffff00360#define AR_RxAntenna_S 8361362/* ds_status4 */363#define AR_RxRSSIAnt10 0x000000ff364#define AR_RxRSSIAnt10_S 0365#define AR_RxRSSIAnt11 0x0000ff00366#define AR_RxRSSIAnt11_S 8367#define AR_RxRSSIAnt12 0x00ff0000368#define AR_RxRSSIAnt12_S 16369#define AR_RxRSSICombined 0xff000000370#define AR_RxRSSICombined_S 24371372/* ds_status5 */373#define AR_RxEVM0 ds_rxstatus5374375/* ds_status6 */376#define AR_RxEVM1 ds_rxstatus6377378/* ds_status7 */379#define AR_RxEVM2 ds_rxstatus7380381/* ds_status8 */382#define AR_RxDone 0x00000001383#define AR_RxFrameOK 0x00000002384#define AR_CRCErr 0x00000004385#define AR_DecryptCRCErr 0x00000008386#define AR_PHYErr 0x00000010387#define AR_MichaelErr 0x00000020388#define AR_PreDelimCRCErr 0x00000040389#define AR_RxStatusRsvd70 0x00000080390#define AR_RxKeyIdxValid 0x00000100391#define AR_KeyIdx 0x0000fe00392#define AR_KeyIdx_S 9393#define AR_PHYErrCode 0x0000ff00394#define AR_PHYErrCode_S 8395#define AR_RxMoreAggr 0x00010000396#define AR_RxAggr 0x00020000397#define AR_PostDelimCRCErr 0x00040000398#define AR_RxStatusRsvd71 0x2ff80000399#define AR_HiRxChain 0x10000000400#define AR_DecryptBusyErr 0x40000000401#define AR_KeyMiss 0x80000000402403#define TXCTL_OFFSET(ah) 2404#define TXCTL_NUMWORDS(ah) (AR_SREV_5416_V20_OR_LATER(ah) ? 12 : 8)405#define TXSTATUS_OFFSET(ah) (AR_SREV_5416_V20_OR_LATER(ah) ? 14 : 10)406#define TXSTATUS_NUMWORDS(ah) 10407408#define RXCTL_OFFSET(ah) 3409#define RXCTL_NUMWORDS(ah) 1410#define RXSTATUS_OFFSET(ah) 4411#define RXSTATUS_NUMWORDS(ah) 9412#define RXSTATUS_RATE(ah, ads) \413(AR_SREV_5416_V20_OR_LATER(ah) ? \414MS((ads)->ds_rxstatus0, AR_RxRate) : \415((ads)->ds_rxstatus3 >> 2) & 0xFF)416#define RXSTATUS_DUPLICATE(ah, ads) \417(AR_SREV_5416_V20_OR_LATER(ah) ? \418MS((ads)->ds_rxstatus3, AR_Parallel40) : \419((ads)->ds_rxstatus3 >> 10) & 0x1)420#endif /* _ATH_AR5416_DESC_H_ */421422423