Path: blob/main/sys/dev/ath/ath_hal/ar9002/ar9287_olc.c
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/*-1* SPDX-License-Identifier: BSD-2-Clause2*3* Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd.4*5* Redistribution and use in source and binary forms, with or without6* modification, are permitted provided that the following conditions7* are met:8* 1. Redistributions of source code must retain the above copyright9* notice, this list of conditions and the following disclaimer.10* 2. Redistributions in binary form must reproduce the above copyright11* notice, this list of conditions and the following disclaimer in the12* documentation and/or other materials provided with the distribution.13*14* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND15* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE16* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE17* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE18* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL19* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS20* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)21* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT22* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY23* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF24* SUCH DAMAGE.25*/26#include "opt_ah.h"2728#include "ah.h"29#include "ah_internal.h"3031#include "ah_eeprom_v14.h"32#include "ah_eeprom_9287.h"3334#include "ar9002/ar9280.h"35#include "ar5416/ar5416reg.h"36#include "ar5416/ar5416phy.h"37#include "ar9002/ar9002phy.h"3839#include "ar9002/ar9287phy.h"40#include "ar9002/ar9287an.h"41#include "ar9002/ar9287_olc.h"4243void44ar9287olcInit(struct ath_hal *ah)45{46OS_REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,47AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);48OS_A_REG_RMW_FIELD(ah, AR9287_AN_TXPC0,49AR9287_AN_TXPC0_TXPCMODE,50AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);51OS_DELAY(100);52}5354/*55* Run temperature compensation calibration.56*57* The TX gain table is adjusted depending upon the difference58* between the initial PDADC value and the currently read59* average TX power sample value. This value is only valid if60* frames have been transmitted, so currPDADC will be 0 if61* no frames have yet been transmitted.62*/63void64ar9287olcTemperatureCompensation(struct ath_hal *ah)65{66uint32_t rddata;67int32_t delta, currPDADC, slope;6869rddata = OS_REG_READ(ah, AR_PHY_TX_PWRCTRL4);70currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);7172HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: initPDADC=%d, currPDADC=%d\n",73__func__, AH5416(ah)->initPDADC, currPDADC);7475if (AH5416(ah)->initPDADC == 0 || currPDADC == 0) {76/*77* Zero value indicates that no frames have been transmitted78* yet, can't do temperature compensation until frames are79* transmitted.80*/81return;82} else {83int8_t val;84(void) (ath_hal_eepromGet(ah, AR_EEP_TEMPSENSE_SLOPE, &val));85slope = val;8687if (slope == 0) { /* to avoid divide by zero case */88delta = 0;89} else {90delta = ((currPDADC - AH5416(ah)->initPDADC)*4) / slope;91}92OS_REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,93AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);94OS_REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,95AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);9697HALDEBUG(ah, HAL_DEBUG_PERCAL, "%s: delta=%d\n", __func__, delta);98}99}100101void102ar9287olcGetTxGainIndex(struct ath_hal *ah,103const struct ieee80211_channel *chan,104struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,105uint8_t *pCalChans, uint16_t availPiers, int8_t *pPwr)106{107uint16_t idxL = 0, idxR = 0, numPiers;108HAL_BOOL match;109CHAN_CENTERS centers;110111ar5416GetChannelCenters(ah, chan, ¢ers);112113for (numPiers = 0; numPiers < availPiers; numPiers++) {114if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)115break;116}117118match = ath_ee_getLowerUpperIndex(119(uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),120pCalChans, numPiers, &idxL, &idxR);121122if (match) {123*pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];124} else {125*pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +126(int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;127}128}129130void131ar9287olcSetPDADCs(struct ath_hal *ah, int32_t txPower,132uint16_t chain)133{134uint32_t tmpVal;135uint32_t a;136137/* Enable OLPC for chain 0 */138139tmpVal = OS_REG_READ(ah, 0xa270);140tmpVal = tmpVal & 0xFCFFFFFF;141tmpVal = tmpVal | (0x3 << 24);142OS_REG_WRITE(ah, 0xa270, tmpVal);143144/* Enable OLPC for chain 1 */145146tmpVal = OS_REG_READ(ah, 0xb270);147tmpVal = tmpVal & 0xFCFFFFFF;148tmpVal = tmpVal | (0x3 << 24);149OS_REG_WRITE(ah, 0xb270, tmpVal);150151/* Write the OLPC ref power for chain 0 */152153if (chain == 0) {154tmpVal = OS_REG_READ(ah, 0xa398);155tmpVal = tmpVal & 0xff00ffff;156a = (txPower)&0xff;157tmpVal = tmpVal | (a << 16);158OS_REG_WRITE(ah, 0xa398, tmpVal);159}160161/* Write the OLPC ref power for chain 1 */162163if (chain == 1) {164tmpVal = OS_REG_READ(ah, 0xb398);165tmpVal = tmpVal & 0xff00ffff;166a = (txPower)&0xff;167tmpVal = tmpVal | (a << 16);168OS_REG_WRITE(ah, 0xb398, tmpVal);169}170}171172173