/*-1* SPDX-License-Identifier: BSD-3-Clause2*3* Copyright (c) 2004 INRIA4* Copyright (c) 2002-2005 Sam Leffler, Errno Consulting5* All rights reserved.6*7* Redistribution and use in source and binary forms, with or without8* modification, are permitted provided that the following conditions9* are met:10* 1. Redistributions of source code must retain the above copyright11* notice, this list of conditions and the following disclaimer,12without modification.13* 2. Redistributions in binary form must reproduce at minimum a disclaimer14* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any15* redistribution must be conditioned upon including a substantially16* similar Disclaimer requirement for further binary redistribution.17* 3. Neither the names of the above-listed copyright holders nor the names18* of any contributors may be used to endorse or promote products derived19* from this software without specific prior written permission.20*21* Alternatively, this software may be distributed under the terms of the22* GNU General Public License ("GPL") version 2 as published by the Free23* Software Foundation.24*25* NO WARRANTY26* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS27* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT28* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY29* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL30* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,31* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF32* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS33* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER34* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)35* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF36* THE POSSIBILITY OF SUCH DAMAGES.37*/3839#ifndef _DEV_ATH_RATE_AMRR_H40#define _DEV_ATH_RATE_AMRR_H4142/* per-device state */43struct amrr_softc {44struct ath_ratectrl arc; /* base state */45};4647/* per-node state */48struct amrr_node {49int amn_rix; /* current rate index */50int amn_ticks; /* time of last update */51int amn_interval; /* update interval (ticks) */52/* AMRR statistics for this node */53u_int amn_tx_try0_cnt;54u_int amn_tx_try1_cnt;55u_int amn_tx_try2_cnt;56u_int amn_tx_try3_cnt;57u_int amn_tx_failure_cnt;58/* AMRR algorithm state for this node */59u_int amn_success_threshold;60u_int amn_success;61u_int amn_recovery;62/* rate index et al. */63u_int8_t amn_tx_rix0; /* series 0 rate index */64u_int8_t amn_tx_rate0; /* series 0 h/w rate */65u_int8_t amn_tx_rate1; /* series 1 h/w rate */66u_int8_t amn_tx_rate2; /* series 2 h/w rate */67u_int8_t amn_tx_rate3; /* series 3 h/w rate */68u_int8_t amn_tx_rate0sp; /* series 0 short preamble h/w rate */69u_int8_t amn_tx_rate1sp; /* series 1 short preamble h/w rate */70u_int8_t amn_tx_rate2sp; /* series 2 short preamble h/w rate */71u_int8_t amn_tx_rate3sp; /* series 3 short preamble h/w rate */72u_int8_t amn_tx_try0; /* series 0 try count */73u_int amn_tx_try1; /* series 1 try count */74u_int amn_tx_try2; /* series 2 try count */75u_int amn_tx_try3; /* series 3 try count */76};77#define ATH_NODE_AMRR(an) ((struct amrr_node *)&an[1])78#endif /* _DEV_ATH_RATE_AMRR_H */798081