CoCalc -- if_bcereg.h

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/dev/bce/if_bcereg.h
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/*-
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 * SPDX-License-Identifier: BSD-3-Clause
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 *
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 * Copyright (c) 2006-2014 QLogic Corporation
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * 1. Redistributions of source code must retain the above copyright
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 *    notice, this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright
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 *    notice, this list of conditions and the following disclaimer in the
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 *    documentation and/or other materials provided with the distribution.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
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 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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 * THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#ifndef	_BCEREG_H_DEFINED
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#define _BCEREG_H_DEFINED
30

31
/****************************************************************************/
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/* Conversion to FreeBSD type definitions.                                  */
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/****************************************************************************/
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#define u64 uint64_t
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#define u32 uint32_t
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#define u16 uint16_t
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#define u8  uint8_t
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#if BYTE_ORDER == BIG_ENDIAN
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#define __BIG_ENDIAN 1
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#undef  __LITTLE_ENDIAN
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#else
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#undef  __BIG_ENDIAN
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#define __LITTLE_ENDIAN 1
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#endif
46

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#define BCE_DWORD_PRINTFB	\
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	"\020"			\
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	"\40b31"		\
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	"\37b30"		\
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	"\36b29"		\
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	"\35b28"		\
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	"\34b27"		\
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	"\33b26"		\
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	"\32b25"		\
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	"\31b24"		\
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	"\30b23"		\
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	"\27b22"		\
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	"\26b21"		\
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	"\25b20"		\
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	"\24b19"		\
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	"\23b18"		\
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	"\22b17"		\
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	"\21b16"		\
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	"\20b15"		\
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	"\17b14"		\
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	"\16b13"		\
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	"\15b12"		\
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	"\14b11"		\
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	"\13b10"		\
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	"\12b9"			\
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	"\11b8"			\
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	"\10b7"			\
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	"\07b6"			\
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	"\06b5"			\
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	"\05b4"			\
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	"\04b3"			\
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	"\03b2"			\
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	"\02b1"			\
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	"\01b0"
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/* MII Control Register 0x0 */
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#define BCE_BMCR_PRINTFB	\
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	"\020"			\
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	"\20Reset"		\
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	"\17Loopback"		\
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	"\16Spd0"		\
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	"\15AnegEna"		\
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	"\14PwrDn"		\
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	"\13Isolate"		\
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	"\12RstrtAneg"		\
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	"\11FD"			\
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	"\10CollTst"		\
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	"\07Spd1"		\
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	"\06Rsrvd"		\
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	"\05Rsrvd"		\
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	"\04Rsrvd"		\
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	"\03Rsrvd"		\
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	"\02Rsrvd"		\
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	"\01Rsrvd"
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/* MII Status Register 0x1 */
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#define BCE_BMSR_PRINTFB	\
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	"\020"			\
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	"\20Cap100T4"		\
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	"\17Cap100XFD"		\
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	"\16Cap100XHD"		\
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	"\15Cap10FD"		\
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	"\14Cap10HD"		\
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	"\13Cap100T2FD"		\
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	"\12Cap100T2HD"		\
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	"\11ExtStsPrsnt"	\
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	"\10Rsrvd"		\
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	"\07PrmblSupp"		\
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	"\06AnegCmpl"		\
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	"\05RemFaultDet"	\
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	"\04AnegCap"		\
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	"\03LnkUp"		\
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	"\02JabberDet"		\
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	"\01ExtCapSupp"
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/* MII Autoneg Advertisement Register 0x4 */
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#define BCE_ANAR_PRINTFB	\
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	"\020"			\
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	"\20AdvNxtPg"		\
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	"\17Rsrvd"		\
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	"\16AdvRemFault"	\
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	"\15Rsrvd"		\
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	"\14AdvAsymPause"	\
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	"\13AdvPause"		\
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	"\12Adv100T4"		\
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	"\11Adv100FD"		\
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	"\10Adv100HD"		\
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	"\07Adv10FD"		\
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	"\06Adv10HD"		\
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	"\05Rsrvd"		\
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	"\04Rsrvd"		\
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	"\03Rsrvd"		\
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	"\02Rsrvd"		\
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	"\01Adv802.3"
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/* MII Autoneg Link Partner Ability Register 0x5 */
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#define BCE_ANLPAR_PRINTFB	\
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	"\020"			\
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	"\20CapNxtPg"		\
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	"\17Ack"		\
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	"\16CapRemFault"	\
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	"\15Rsrvd"		\
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	"\14CapAsymPause"	\
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	"\13CapPause"		\
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	"\12Cap100T4"		\
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	"\11Cap100FD"		\
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	"\10Cap100HD"		\
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	"\07Cap10FD"		\
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	"\06Cap10HD"		\
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	"\05Rsrvd"		\
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	"\04Rsrvd"		\
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	"\03Rsrvd"		\
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	"\02Rsrvd"		\
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	"\01Cap802.3"
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/* 1000Base-T Control Register 0x09 */
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#define BCE_1000CTL_PRINTFB	\
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	"\020"			\
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	"\20Test3"		\
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	"\17Test2"		\
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	"\16Test1"		\
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	"\15MasterSlave"	\
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	"\14ForceMaster"	\
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	"\13SwitchDev" 		\
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	"\12Adv1000TFD"		\
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	"\11Adv1000THD"		\
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	"\10Rsrvd"		\
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	"\07Rsrvd"		\
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	"\06Rsrvd"		\
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	"\05Rsrvd"		\
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	"\04Rsrvd"		\
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	"\03Rsrvd"		\
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	"\02Rsrvd"		\
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	"\01Rsrvd"
181

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/* MII 1000Base-T Status Register 0x0a */
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#define BCE_1000STS_PRINTFB	\
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	"\020"			\
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	"\20MstrSlvFault"	\
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	"\17Master"		\
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	"\16LclRcvrOk"		\
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	"\15RemRcvrOk"		\
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	"\14Cap1000FD"		\
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	"\13Cpa1000HD"		\
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	"\12Rsrvd"		\
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	"\11Rsrvd"
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/* MII Extended Status Register 0x0f */
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#define BCE_EXTSTS_PRINTFB	\
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	"\020"			\
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	"\20b15"		\
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	"\17b14"		\
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	"\16b13"		\
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	"\15b12"		\
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	"\14Rsrvd"		\
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	"\13Rsrvd"		\
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	"\12Rsrvd"		\
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	"\11Rsrvd"		\
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	"\10Rsrvd"		\
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	"\07Rsrvd"		\
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	"\06Rsrvd" 		\
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	"\05Rsrvd"		\
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	"\04Rsrvd"		\
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	"\03Rsrvd"		\
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	"\02Rsrvd"		\
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	"\01Rsrvd"
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/* MII Autoneg Link Partner Ability Register 0x19 */
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#define BCE_AUXSTS_PRINTFB	\
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	"\020"			\
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	"\20AnegCmpl"		\
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	"\17AnegCmplAck"	\
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	"\16AnegAckDet"		\
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	"\15AnegAblDet"		\
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	"\14AnegNextPgWait"	\
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	"\13HCD"		\
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	"\12HCD" 		\
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	"\11HCD" 		\
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	"\10PrlDetFault"	\
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	"\07RemFault"		\
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	"\06PgRcvd"		\
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	"\05LnkPrtnrAnegAbl"	\
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	"\04LnkPrtnrNPAbl"	\
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	"\03LnkUp"		\
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	"\02EnaPauseRcv"	\
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	"\01EnaPausXmit"
233

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/*
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 * Remove before release:
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 *
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 * #define BCE_DEBUG
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 * #define BCE_NVRAM_WRITE_SUPPORT
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 */
240

241
/****************************************************************************/
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/* Debugging macros and definitions.                                        */
243
/****************************************************************************/
244

245
#define BCE_CP_LOAD 		0x00000001
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#define BCE_CP_SEND		0x00000002
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#define BCE_CP_RECV		0x00000004
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#define BCE_CP_INTR		0x00000008
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#define BCE_CP_UNLOAD		0x00000010
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#define BCE_CP_RESET		0x00000020
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#define BCE_CP_PHY			0x00000040
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#define BCE_CP_NVRAM		0x00000080
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#define BCE_CP_FIRMWARE	0x00000100
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#define BCE_CP_CTX			0x00000200
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#define BCE_CP_REG			0x00000400
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#define BCE_CP_MISC		0x00400000
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#define BCE_CP_SPECIAL		0x00800000
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#define BCE_CP_ALL			0x00FFFFFF
259

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#define BCE_CP_MASK		0x00FFFFFF
261

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#define BCE_LEVEL_FATAL	0x00000000
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#define BCE_LEVEL_WARN		0x01000000
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#define BCE_LEVEL_INFO		0x02000000
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#define BCE_LEVEL_VERBOSE	0x03000000
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#define BCE_LEVEL_EXTREME	0x04000000
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#define BCE_LEVEL_INSANE	0x05000000
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#define BCE_LEVEL_MASK		0xFF000000
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#define BCE_WARN_LOAD		(BCE_CP_LOAD | BCE_LEVEL_WARN)
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#define BCE_INFO_LOAD		(BCE_CP_LOAD | BCE_LEVEL_INFO)
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#define BCE_VERBOSE_LOAD	(BCE_CP_LOAD | BCE_LEVEL_VERBOSE)
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#define BCE_EXTREME_LOAD	(BCE_CP_LOAD | BCE_LEVEL_EXTREME)
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#define BCE_INSANE_LOAD	(BCE_CP_LOAD | BCE_LEVEL_INSANE)
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#define BCE_WARN_SEND		(BCE_CP_SEND | BCE_LEVEL_WARN)
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#define BCE_INFO_SEND		(BCE_CP_SEND | BCE_LEVEL_INFO)
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#define BCE_VERBOSE_SEND	(BCE_CP_SEND | BCE_LEVEL_VERBOSE)
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#define BCE_EXTREME_SEND	(BCE_CP_SEND | BCE_LEVEL_EXTREME)
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#define BCE_INSANE_SEND	(BCE_CP_SEND | BCE_LEVEL_INSANE)
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#define BCE_WARN_RECV		(BCE_CP_RECV | BCE_LEVEL_WARN)
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#define BCE_INFO_RECV		(BCE_CP_RECV | BCE_LEVEL_INFO)
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#define BCE_VERBOSE_RECV	(BCE_CP_RECV | BCE_LEVEL_VERBOSE)
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#define BCE_EXTREME_RECV	(BCE_CP_RECV | BCE_LEVEL_EXTREME)
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#define BCE_INSANE_RECV	(BCE_CP_RECV | BCE_LEVEL_INSANE)
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#define BCE_WARN_INTR		(BCE_CP_INTR | BCE_LEVEL_WARN)
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#define BCE_INFO_INTR		(BCE_CP_INTR | BCE_LEVEL_INFO)
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#define BCE_VERBOSE_INTR	(BCE_CP_INTR | BCE_LEVEL_VERBOSE)
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#define BCE_EXTREME_INTR	(BCE_CP_INTR | BCE_LEVEL_EXTREME)
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#define BCE_INSANE_INTR	(BCE_CP_INTR | BCE_LEVEL_INSANE)
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#define BCE_WARN_UNLOAD	(BCE_CP_UNLOAD | BCE_LEVEL_WARN)
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#define BCE_INFO_UNLOAD	(BCE_CP_UNLOAD | BCE_LEVEL_INFO)
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#define BCE_VERBOSE_UNLOAD	(BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE)
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#define BCE_EXTREME_UNLOAD	(BCE_CP_UNLOAD | BCE_LEVEL_EXTREME)
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#define BCE_INSANE_UNLOAD	(BCE_CP_UNLOAD | BCE_LEVEL_INSANE)
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#define BCE_WARN_RESET		(BCE_CP_RESET | BCE_LEVEL_WARN)
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#define BCE_INFO_RESET		(BCE_CP_RESET | BCE_LEVEL_INFO)
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#define BCE_VERBOSE_RESET	(BCE_CP_RESET | BCE_LEVEL_VERBOSE)
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#define BCE_EXTREME_RESET	(BCE_CP_RESET | BCE_LEVEL_EXTREME)
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#define BCE_INSANE_RESET	(BCE_CP_RESET | BCE_LEVEL_INSANE)
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#define BCE_WARN_PHY		(BCE_CP_PHY | BCE_LEVEL_WARN)
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#define BCE_INFO_PHY		(BCE_CP_PHY | BCE_LEVEL_INFO)
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#define BCE_VERBOSE_PHY	(BCE_CP_PHY | BCE_LEVEL_VERBOSE)
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#define BCE_EXTREME_PHY	(BCE_CP_PHY | BCE_LEVEL_EXTREME)
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#define BCE_INSANE_PHY		(BCE_CP_PHY | BCE_LEVEL_INSANE)
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#define BCE_WARN_NVRAM		(BCE_CP_NVRAM | BCE_LEVEL_WARN)
314
#define BCE_INFO_NVRAM		(BCE_CP_NVRAM | BCE_LEVEL_INFO)
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#define BCE_VERBOSE_NVRAM	(BCE_CP_NVRAM | BCE_LEVEL_VERBOSE)
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#define BCE_EXTREME_NVRAM	(BCE_CP_NVRAM | BCE_LEVEL_EXTREME)
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#define BCE_INSANE_NVRAM	(BCE_CP_NVRAM | BCE_LEVEL_INSANE)
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#define BCE_WARN_FIRMWARE	(BCE_CP_FIRMWARE | BCE_LEVEL_WARN)
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#define BCE_INFO_FIRMWARE	(BCE_CP_FIRMWARE | BCE_LEVEL_INFO)
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#define BCE_VERBOSE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_VERBOSE)
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#define BCE_EXTREME_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_EXTREME)
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#define BCE_INSANE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_INSANE)
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#define BCE_WARN_CTX		(BCE_CP_CTX | BCE_LEVEL_WARN)
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#define BCE_INFO_CTX		(BCE_CP_CTX | BCE_LEVEL_INFO)
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#define BCE_VERBOSE_CTX	(BCE_CP_CTX | BCE_LEVEL_VERBOSE)
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#define BCE_EXTREME_CTX	(BCE_CP_CTX | BCE_LEVEL_EXTREME)
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#define BCE_INSANE_CTX		(BCE_CP_CTX | BCE_LEVEL_INSANE)
330

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#define BCE_WARN_REG		(BCE_CP_REG | BCE_LEVEL_WARN)
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#define BCE_INFO_REG		(BCE_CP_REG | BCE_LEVEL_INFO)
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#define BCE_VERBOSE_REG	(BCE_CP_REG | BCE_LEVEL_VERBOSE)
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#define BCE_EXTREME_REG	(BCE_CP_REG | BCE_LEVEL_EXTREME)
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#define BCE_INSANE_REG		(BCE_CP_REG | BCE_LEVEL_INSANE)
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337
#define BCE_WARN_MISC		(BCE_CP_MISC | BCE_LEVEL_WARN)
338
#define BCE_INFO_MISC		(BCE_CP_MISC | BCE_LEVEL_INFO)
339
#define BCE_VERBOSE_MISC	(BCE_CP_MISC | BCE_LEVEL_VERBOSE)
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#define BCE_EXTREME_MISC	(BCE_CP_MISC | BCE_LEVEL_EXTREME)
341
#define BCE_INSANE_MISC	(BCE_CP_MISC | BCE_LEVEL_INSANE)
342

343
#define BCE_WARN_SPECIAL	(BCE_CP_SPECIAL | BCE_LEVEL_WARN)
344
#define BCE_INFO_SPECIAL	(BCE_CP_SPECIAL | BCE_LEVEL_INFO)
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#define BCE_VERBOSE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_VERBOSE)
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#define BCE_EXTREME_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_EXTREME)
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#define BCE_INSANE_SPECIAL	(BCE_CP_SPECIAL | BCE_LEVEL_INSANE)
348

349
#define BCE_FATAL			(BCE_CP_ALL | BCE_LEVEL_FATAL)
350
#define BCE_WARN			(BCE_CP_ALL | BCE_LEVEL_WARN)
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#define BCE_INFO			(BCE_CP_ALL | BCE_LEVEL_INFO)
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#define BCE_VERBOSE		(BCE_CP_ALL | BCE_LEVEL_VERBOSE)
353
#define BCE_EXTREME		(BCE_CP_ALL | BCE_LEVEL_EXTREME)
354
#define BCE_INSANE			(BCE_CP_ALL | BCE_LEVEL_INSANE)
355

356
#define BCE_CODE_PATH(cp)	((cp & BCE_CP_MASK) & bce_debug)
357
#define BCE_MSG_LEVEL(lv)	\
358
    ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK))
359
#define BCE_LOG_MSG(m)		(BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m))
360

361
#ifdef BCE_DEBUG
362

363
/* Print a message based on the logging level and code path. */
364
#define DBPRINT(sc, level, format, args...)			\
365
	if (BCE_LOG_MSG(level)) {				\
366
		device_printf(sc->bce_dev, format, ## args);	\
367
	}
368

369
/* Runs a particular command when debugging is enabled. */
370
#define DBRUN(args...)						\
371
	do {							\
372
		args;						\
373
	} while (0)
374

375
/* Runs a particular command based on the logging level and code path. */
376
#define DBRUNMSG(msg, args...)					\
377
	if (BCE_LOG_MSG(msg)) {					\
378
		args;						\
379
	}
380

381
/* Runs a particular command based on the logging level. */
382
#define DBRUNLV(level, args...) 				\
383
	if (BCE_MSG_LEVEL(level)) { 				\
384
		args;						\
385
	}
386

387
/* Runs a particular command based on the code path. */
388
#define DBRUNCP(cp, args...)					\
389
	if (BCE_CODE_PATH(cp)) { 				\
390
		args; 						\
391
	}
392

393
/* Runs a particular command based on a condition. */
394
#define DBRUNIF(cond, args...)					\
395
	if (cond) {						\
396
		args;						\
397
	}
398

399
/* Announces function entry. */
400
#define DBENTER(cond)						\
401
	DBPRINT(sc, (cond), "%s(enter)\n", __FUNCTION__)
402

403
/* Announces function exit. */
404
#define DBEXIT(cond)						\
405
	DBPRINT(sc, (cond), "%s(exit)\n", __FUNCTION__)
406

407
/* Temporarily override the debug level. */
408
#define DBPUSH(cond)						\
409
	u32 bce_debug_temp = bce_debug;				\
410
	bce_debug |= cond;
411

412
/* Restore the previously overridden debug level. */
413
#define DBPOP()							\
414
	bce_debug = bce_debug_temp;
415

416
/* Needed for random() function which is only used in debugging. */
417
#include <sys/random.h>
418

419
/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
420
#define DB_RANDOMFALSE(defects)        (random() > defects)
421
#define DB_OR_RANDOMFALSE(defects)  || (random() > defects)
422
#define DB_AND_RANDOMFALSE(defects) && (random() > defects)
423

424
/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
425
#define DB_RANDOMTRUE(defects)         (random() < defects)
426
#define DB_OR_RANDOMTRUE(defects)   || (random() < defects)
427
#define DB_AND_RANDOMTRUE(defects)  && (random() < defects)
428

429
#define DB_PRINT_PHY_REG(reg, val)					\
430
switch(reg) {								\
431
case 0x00: DBPRINT(sc, BCE_INSANE_PHY,					\
432
	"%s(): phy = %d, reg = 0x%04X (BMCR   ), val = 0x%b\n",		\
433
	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
434
	BCE_BMCR_PRINTFB); break;					\
435
case 0x01: DBPRINT(sc, BCE_INSANE_PHY,					\
436
	"%s(): phy = %d, reg = 0x%04X (BMSR   ), val = 0x%b\n",		\
437
	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
438
	BCE_BMSR_PRINTFB); break;					\
439
case 0x04: DBPRINT(sc, BCE_INSANE_PHY,					\
440
	"%s(): phy = %d, reg = 0x%04X (ANAR   ), val = 0x%b\n",		\
441
	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
442
	BCE_ANAR_PRINTFB); break;					\
443
case 0x05: DBPRINT(sc, BCE_INSANE_PHY,					\
444
	"%s(): phy = %d, reg = 0x%04X (ANLPAR ), val = 0x%b\n",		\
445
	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
446
	BCE_ANLPAR_PRINTFB); break;					\
447
case 0x09: DBPRINT(sc, BCE_INSANE_PHY,					\
448
	"%s(): phy = %d, reg = 0x%04X (1000CTL), val = 0x%b\n",		\
449
	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
450
	BCE_1000CTL_PRINTFB); break;					\
451
case 0x0a: DBPRINT(sc, BCE_INSANE_PHY,					\
452
	"%s(): phy = %d, reg = 0x%04X (1000STS), val = 0x%b\n",		\
453
	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
454
	BCE_1000STS_PRINTFB); break;					\
455
case 0x0f: DBPRINT(sc, BCE_INSANE_PHY,					\
456
	"%s(): phy = %d, reg = 0x%04X (EXTSTS ), val = 0x%b\n",		\
457
	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
458
	BCE_EXTSTS_PRINTFB); break;					\
459
case 0x19: DBPRINT(sc, BCE_INSANE_PHY,					\
460
	"%s(): phy = %d, reg = 0x%04X (AUXSTS ), val = 0x%b\n",		\
461
	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
462
	BCE_AUXSTS_PRINTFB); break;					\
463
default: DBPRINT(sc, BCE_INSANE_PHY,					\
464
	"%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",			\
465
	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff);	\
466
	}
467

468
#else
469

470
#define DBPRINT(level, format, args...)
471
#define DBRUN(args...)
472
#define DBRUNMSG(msg, args...)
473
#define DBRUNLV(level, args...)
474
#define DBRUNCP(cp, args...)
475
#define DBRUNIF(cond, args...)
476
#define DBENTER(cond)
477
#define DBEXIT(cond)
478
#define DBPUSH(cond)
479
#define DBPOP()
480
#define DB_RANDOMFALSE(defects)
481
#define DB_OR_RANDOMFALSE(percent)
482
#define DB_AND_RANDOMFALSE(percent)
483
#define DB_RANDOMTRUE(defects)
484
#define DB_OR_RANDOMTRUE(percent)
485
#define DB_AND_RANDOMTRUE(percent)
486
#define DB_PRINT_PHY_REG(reg, val)
487

488
#endif /* BCE_DEBUG */
489

490
/****************************************************************************/
491
/* Device identification definitions.                                       */
492
/****************************************************************************/
493
#define BRCM_VENDORID				0x14E4
494
#define BRCM_DEVICEID_BCM5706			0x164A
495
#define BRCM_DEVICEID_BCM5706S			0x16AA
496
#define BRCM_DEVICEID_BCM5708			0x164C
497
#define BRCM_DEVICEID_BCM5708S			0x16AC
498
#define BRCM_DEVICEID_BCM5709			0x1639
499
#define BRCM_DEVICEID_BCM5709S			0x163A
500
#define BRCM_DEVICEID_BCM5716			0x163B
501

502
#define HP_VENDORID				0x103C
503

504
#define PCI_ANY_ID				(u_int16_t) (~0U)
505

506
/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
507

508
#define BCE_CHIP_NUM(sc)		(((sc)->bce_chipid) & 0xffff0000)
509
#define BCE_CHIP_NUM_5706		0x57060000
510
#define BCE_CHIP_NUM_5708		0x57080000
511
#define BCE_CHIP_NUM_5709		0x57090000
512

513
#define BCE_CHIP_REV(sc)		(((sc)->bce_chipid) & 0x0000f000)
514
#define BCE_CHIP_REV_Ax			0x00000000
515
#define BCE_CHIP_REV_Bx			0x00001000
516
#define BCE_CHIP_REV_Cx			0x00002000
517

518
#define BCE_CHIP_METAL(sc)		(((sc)->bce_chipid) & 0x00000ff0)
519
#define BCE_CHIP_BOND(bp)		(((sc)->bce_chipid) & 0x0000000f)
520

521
#define BCE_CHIP_ID(sc)			(((sc)->bce_chipid) & 0xfffffff0)
522
#define BCE_CHIP_ID_5706_A0		0x57060000
523
#define BCE_CHIP_ID_5706_A1		0x57060010
524
#define BCE_CHIP_ID_5706_A2		0x57060020
525
#define BCE_CHIP_ID_5706_A3		0x57060030
526
#define BCE_CHIP_ID_5708_A0		0x57080000
527
#define BCE_CHIP_ID_5708_B0		0x57081000
528
#define BCE_CHIP_ID_5708_B1		0x57081010
529
#define BCE_CHIP_ID_5708_B2		0x57081020
530
#define BCE_CHIP_ID_5709_A0		0x57090000
531
#define BCE_CHIP_ID_5709_A1		0x57090010
532
#define BCE_CHIP_ID_5709_B0		0x57091000
533
#define BCE_CHIP_ID_5709_B1		0x57091010
534
#define BCE_CHIP_ID_5709_B2		0x57091020
535
#define BCE_CHIP_ID_5709_C0		0x57092000
536

537
#define BCE_CHIP_BOND_ID(sc)		(((sc)->bce_chipid) & 0xf)
538

539
/* A serdes chip will have the first bit of the bond id set. */
540
#define BCE_CHIP_BOND_ID_SERDES_BIT	0x01
541

542
/* shorthand one */
543
#define BCE_ASICREV(x)			((x) >> 28)
544
#define BCE_ASICREV_BCM5700		0x06
545

546
/* chip revisions */
547
#define BCE_CHIPREV(x)			((x) >> 24)
548
#define BCE_CHIPREV_5700_AX		0x70
549
#define BCE_CHIPREV_5700_BX		0x71
550
#define BCE_CHIPREV_5700_CX		0x72
551
#define BCE_CHIPREV_5701_AX		0x00
552

553
struct bce_type {
554
	u_int16_t bce_vid;
555
	u_int16_t bce_did;
556
	u_int16_t bce_svid;
557
	u_int16_t bce_sdid;
558
	const char *bce_name;
559
};
560

561
/****************************************************************************/
562
/* Byte order conversions.                                                  */
563
/****************************************************************************/
564
#define bce_htobe16(x) htobe16(x)
565
#define bce_htobe32(x) htobe32(x)
566
#define bce_htobe64(x) htobe64(x)
567
#define bce_htole16(x) htole16(x)
568
#define bce_htole32(x) htole32(x)
569
#define bce_htole64(x) htole64(x)
570

571
#define bce_be16toh(x) be16toh(x)
572
#define bce_be32toh(x) be32toh(x)
573
#define bce_be64toh(x) be64toh(x)
574
#define bce_le16toh(x) le16toh(x)
575
#define bce_le32toh(x) le32toh(x)
576
#define bce_le64toh(x) le64toh(x)
577

578
/****************************************************************************/
579
/* NVRAM Access                                                             */
580
/****************************************************************************/
581

582
/* Buffered flash (Atmel: AT45DB011B) specific information */
583
#define SEEPROM_PAGE_BITS		2
584
#define SEEPROM_PHY_PAGE_SIZE		(1 << SEEPROM_PAGE_BITS)
585
#define SEEPROM_BYTE_ADDR_MASK		(SEEPROM_PHY_PAGE_SIZE-1)
586
#define SEEPROM_PAGE_SIZE		4
587
#define SEEPROM_TOTAL_SIZE		65536
588

589
#define BUFFERED_FLASH_PAGE_BITS	9
590
#define BUFFERED_FLASH_PHY_PAGE_SIZE	(1 << BUFFERED_FLASH_PAGE_BITS)
591
#define BUFFERED_FLASH_BYTE_ADDR_MASK	(BUFFERED_FLASH_PHY_PAGE_SIZE-1)
592
#define BUFFERED_FLASH_PAGE_SIZE	264
593
#define BUFFERED_FLASH_TOTAL_SIZE	0x21000
594

595
#define SAIFUN_FLASH_PAGE_BITS		8
596
#define SAIFUN_FLASH_PHY_PAGE_SIZE	(1 << SAIFUN_FLASH_PAGE_BITS)
597
#define SAIFUN_FLASH_BYTE_ADDR_MASK	(SAIFUN_FLASH_PHY_PAGE_SIZE-1)
598
#define SAIFUN_FLASH_PAGE_SIZE		256
599
#define SAIFUN_FLASH_BASE_TOTAL_SIZE	65536
600

601
#define ST_MICRO_FLASH_PAGE_BITS	8
602
#define ST_MICRO_FLASH_PHY_PAGE_SIZE	(1 << ST_MICRO_FLASH_PAGE_BITS)
603
#define ST_MICRO_FLASH_BYTE_ADDR_MASK	(ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
604
#define ST_MICRO_FLASH_PAGE_SIZE	256
605
#define ST_MICRO_FLASH_BASE_TOTAL_SIZE	65536
606

607
#define BCM5709_FLASH_PAGE_BITS		8
608
#define BCM5709_FLASH_PHY_PAGE_SIZE	(1 << BCM5709_FLASH_PAGE_BITS)
609
#define BCM5709_FLASH_BYTE_ADDR_MASK	(BCM5709_FLASH_PHY_PAGE_SIZE-1)
610
#define BCM5709_FLASH_PAGE_SIZE		256
611

612
#define NVRAM_TIMEOUT_COUNT		30000
613
#define BCE_FLASHDESC_MAX		64
614

615
#define FLASH_STRAP_MASK	(BCE_NVM_CFG1_FLASH_MODE |	\
616
    BCE_NVM_CFG1_BUFFER_MODE | BCE_NVM_CFG1_PROTECT_MODE |	\
617
    BCE_NVM_CFG1_FLASH_SIZE)
618

619
#define FLASH_BACKUP_STRAP_MASK		(0xf << 26)
620

621
struct flash_spec {
622
	u32 strapping;
623
	u32 config1;
624
	u32 config2;
625
	u32 config3;
626
	u32 write1;
627
#define BCE_NV_BUFFERED		0x00000001
628
#define BCE_NV_TRANSLATE	0x00000002
629
#define BCE_NV_WREN		0x00000004
630
	u32 flags;
631
	u32 page_bits;
632
	u32 page_size;
633
	u32 addr_mask;
634
	u32 total_size;
635
	const u8 *name;
636
};
637

638
/****************************************************************************/
639
/* Shared Memory layout                                                     */
640
/* The BCE bootcode will initialize this data area with port configurtion   */
641
/* information which can be accessed by the driver.                         */
642
/****************************************************************************/
643

644
/*
645
 * This value (in milliseconds) determines the frequency of the driver
646
 * issuing the PULSE message code.  The firmware monitors this periodic
647
 * pulse to determine when to switch to an OS-absent mode.
648
 */
649
#define DRV_PULSE_PERIOD_MS                 250
650

651
/*
652
 * This value (in milliseconds) determines how long the driver should
653
 * wait for an acknowledgement from the firmware before timing out.  Once
654
 * the firmware has timed out, the driver will assume there is no firmware
655
 * running and there won't be any firmware-driver synchronization during a
656
 * driver reset.
657
 */
658
#define FW_ACK_TIME_OUT_MS			1000
659

660
#define BCE_DRV_RESET_SIGNATURE			0x00000000
661
#define BCE_DRV_RESET_SIGNATURE_MAGIC		0x4841564b /* HAVK */
662

663
#define BCE_DRV_MB				0x00000004
664
#define BCE_DRV_MSG_CODE	 		0xff000000
665
#define BCE_DRV_MSG_CODE_RESET		 	0x01000000
666
#define BCE_DRV_MSG_CODE_UNLOAD			0x02000000
667
#define BCE_DRV_MSG_CODE_SHUTDOWN	 	0x03000000
668
#define BCE_DRV_MSG_CODE_SUSPEND_WOL		0x04000000
669
#define BCE_DRV_MSG_CODE_FW_TIMEOUT	 	0x05000000
670
#define BCE_DRV_MSG_CODE_PULSE		 	0x06000000
671
#define BCE_DRV_MSG_CODE_DIAG		 	0x07000000
672
#define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL	 	0x09000000
673
#define BCE_DRV_MSG_CODE_UNLOAD_LNK_DN		0x0b000000
674
#define BCE_DRV_MSG_CODE_CMD_SET_LINK		0x10000000
675

676
#define BCE_DRV_MSG_DATA			0x00ff0000
677
#define BCE_DRV_MSG_DATA_WAIT0		 	0x00010000
678
#define BCE_DRV_MSG_DATA_WAIT1			0x00020000
679
#define BCE_DRV_MSG_DATA_WAIT2			0x00030000
680
#define BCE_DRV_MSG_DATA_WAIT3			0x00040000
681

682
#define BCE_DRV_MSG_SEQ				0x0000ffff
683

684
#define BCE_FW_MB				0x00000008
685
#define BCE_FW_MSG_ACK				 0x0000ffff
686
#define BCE_FW_MSG_STATUS_MASK			 0x00ff0000
687
#define BCE_FW_MSG_STATUS_OK			 0x00000000
688
#define BCE_FW_MSG_STATUS_INVALID_ARGS		 0x00010000
689
#define BCE_FW_MSG_STATUS_DRV_PRSNT		 0x00020000
690
#define BCE_FW_MSG_STATUS_FAILURE		 0x00ff0000
691

692
#define BCE_LINK_STATUS				0x0000000c
693
#define BCE_LINK_STATUS_INIT_VALUE		 0xffffffff
694
#define BCE_LINK_STATUS_LINK_UP		 	 0x1
695
#define BCE_LINK_STATUS_LINK_DOWN		 0x0
696
#define BCE_LINK_STATUS_SPEED_MASK		 0x1e
697
#define BCE_LINK_STATUS_AN_INCOMPLETE		 (0<<1)
698
#define BCE_LINK_STATUS_10HALF			 (1<<1)
699
#define BCE_LINK_STATUS_10FULL			 (2<<1)
700
#define BCE_LINK_STATUS_100HALF			 (3<<1)
701
#define BCE_LINK_STATUS_100BASE_T4		 (4<<1)
702
#define BCE_LINK_STATUS_100FULL			 (5<<1)
703
#define BCE_LINK_STATUS_1000HALF		 (6<<1)
704
#define BCE_LINK_STATUS_1000FULL		 (7<<1)
705
#define BCE_LINK_STATUS_2500HALF		 (8<<1)
706
#define BCE_LINK_STATUS_2500FULL		 (9<<1)
707
#define BCE_LINK_STATUS_AN_ENABLED		 (1<<5)
708
#define BCE_LINK_STATUS_AN_COMPLETE		 (1<<6)
709
#define BCE_LINK_STATUS_PARALLEL_DET		 (1<<7)
710
#define BCE_LINK_STATUS_RESERVED		 (1<<8)
711
#define BCE_LINK_STATUS_PARTNER_AD_1000FULL	 (1<<9)
712
#define BCE_LINK_STATUS_PARTNER_AD_1000HALF	 (1<<10)
713
#define BCE_LINK_STATUS_PARTNER_AD_100BT4	 (1<<11)
714
#define BCE_LINK_STATUS_PARTNER_AD_100FULL	 (1<<12)
715
#define BCE_LINK_STATUS_PARTNER_AD_100HALF	 (1<<13)
716
#define BCE_LINK_STATUS_PARTNER_AD_10FULL	 (1<<14)
717
#define BCE_LINK_STATUS_PARTNER_AD_10HALF	 (1<<15)
718
#define BCE_LINK_STATUS_TX_FC_ENABLED		 (1<<16)
719
#define BCE_LINK_STATUS_RX_FC_ENABLED		 (1<<17)
720
#define BCE_LINK_STATUS_PARTNER_SYM_PAUSE_CAP	 (1<<18)
721
#define BCE_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP	 (1<<19)
722
#define BCE_LINK_STATUS_SERDES_LINK		 (1<<20)
723
#define BCE_LINK_STATUS_PARTNER_AD_2500FULL	 (1<<21)
724
#define BCE_LINK_STATUS_PARTNER_AD_2500HALF	 (1<<22)
725

726
#define BCE_DRV_PULSE_MB			0x00000010
727
#define BCE_DRV_PULSE_SEQ_MASK			 0x00007fff
728

729
#define BCE_MB_ARGS_0				0x00000014
730
#define	BCE_NETLINK_SPEED_10HALF		 (1<<0)
731
#define	BCE_NETLINK_SPEED_10FULL		 (1<<1)
732
#define	BCE_NETLINK_SPEED_100HALF		 (1<<2)
733
#define	BCE_NETLINK_SPEED_100FULL		 (1<<3)
734
#define	BCE_NETLINK_SPEED_1000HALF		 (1<<4)
735
#define	BCE_NETLINK_SPEED_1000FULL		 (1<<5)
736
#define	BCE_NETLINK_SPEED_2500HALF		 (1<<6)
737
#define	BCE_NETLINK_SPEED_2500FULL		 (1<<7)
738
#define	BCE_NETLINK_SPEED_10GHALF		 (1<<8)
739
#define	BCE_NETLINK_SPEED_10GFULL		 (1<<9)
740
#define	BCE_NETLINK_ANEG_ENB		 	 (1<<10)
741
#define	BCE_NETLINK_PHY_APP_REMOTE	 	 (1<<11)
742
#define	BCE_NETLINK_FC_PAUSE_SYM	 	 (1<<12)
743
#define	BCE_NETLINK_FC_PAUSE_ASYM	 	 (1<<13)
744
#define	BCE_NETLINK_ETH_AT_WIRESPEED	 	 (1<<14)
745
#define	BCE_NETLINK_PHY_RESET	 	 	 (1<<15)
746

747
#define BCE_MB_ARGS_1				0x00000018
748

749
/* Indicate to the firmware not to go into the
750
 * OS absent when it is not getting driver pulse.
751
 * This is used for debugging. */
752
#define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE	 0x00080000
753

754
#define BCE_DEV_INFO_SIGNATURE			0x00000020
755
#define BCE_DEV_INFO_SIGNATURE_MAGIC		 0x44564900
756
#define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK	 0xffffff00
757
#define BCE_DEV_INFO_FEATURE_CFG_VALID		 0x01
758
#define BCE_DEV_INFO_SECONDARY_PORT		 0x80
759
#define BCE_DEV_INFO_DRV_ALWAYS_ALIVE		 0x40
760

761
#define BCE_SHARED_HW_CFG_PART_NUM		0x00000024
762

763
#define BCE_SHARED_HW_CFG_POWER_DISSIPATED	0x00000034
764
#define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK	 0xff000000
765
#define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK	 0xff0000
766
#define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK	 0xff00
767
#define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK	 0xff
768

769
#define BCE_SHARED_HW_CFG_POWER_CONSUMED	0x00000038
770
#define BCE_SHARED_HW_CFG_CONFIG		0x0000003c
771
#define BCE_SHARED_HW_CFG_DESIGN_NIC		 0
772
#define BCE_SHARED_HW_CFG_DESIGN_LOM		 0x1
773
#define BCE_SHARED_HW_CFG_PHY_COPPER		 0
774
#define BCE_SHARED_HW_CFG_PHY_FIBER		 0x2
775
#define BCE_SHARED_HW_CFG_PHY_2_5G		 0x20
776
#define BCE_SHARED_HW_CFG_PHY_BACKPLANE		 0x40
777
#define BCE_SHARED_HW_CFG_LED_MODE_SHIFT_BITS	 8
778
#define BCE_SHARED_HW_CFG_LED_MODE_MASK		 0x300
779
#define BCE_SHARED_HW_CFG_LED_MODE_MAC		 0
780
#define BCE_SHARED_HW_CFG_LED_MODE_GPHY1	 0x100
781
#define BCE_SHARED_HW_CFG_LED_MODE_GPHY2	 0x200
782

783
#define BCE_SHARED_HW_CFG_CONFIG2		0x00000040
784
#define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK	 0x00fff000
785

786
#define BCE_DEV_INFO_BC_REV			0x0000004c
787

788
#define BCE_PORT_HW_CFG_MAC_UPPER		0x00000050
789
#define BCE_PORT_HW_CFG_UPPERMAC_MASK		 0xffff
790

791
#define BCE_PORT_HW_CFG_MAC_LOWER		0x00000054
792
#define BCE_PORT_HW_CFG_CONFIG			0x00000058
793
#define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK		 0x0000ffff
794
#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK	 0x001f0000
795
#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN	 0x00000000
796
#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G	 0x00030000
797
#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G	 0x00040000
798

799
#define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER		0x00000068
800
#define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER		0x0000006c
801
#define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER		0x00000070
802
#define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER		0x00000074
803
#define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER		0x00000078
804
#define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER		0x0000007c
805

806
#define BCE_DEV_INFO_PER_PORT_HW_CONFIG2	0x000000b4
807

808
#define BCE_DEV_INFO_FORMAT_REV			0x000000c4
809
#define BCE_DEV_INFO_FORMAT_REV_MASK		 0xff000000
810
#define BCE_DEV_INFO_FORMAT_REV_ID		 ('A' << 24)
811

812
#define BCE_SHARED_FEATURE			0x000000c8
813
#define BCE_SHARED_FEATURE_MASK			 0xffffffff
814

815
#define BCE_PORT_FEATURE			0x000000d8
816
#define BCE_PORT2_FEATURE			0x00000014c
817
#define BCE_PORT_FEATURE_WOL_ENABLED		 0x01000000
818
#define BCE_PORT_FEATURE_MBA_ENABLED		 0x02000000
819
#define BCE_PORT_FEATURE_ASF_ENABLED		 0x04000000
820
#define BCE_PORT_FEATURE_IMD_ENABLED		 0x08000000
821
#define BCE_PORT_FEATURE_BAR1_SIZE_MASK		 0xf
822
#define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED	 0x0
823
#define BCE_PORT_FEATURE_BAR1_SIZE_64K		 0x1
824
#define BCE_PORT_FEATURE_BAR1_SIZE_128K		 0x2
825
#define BCE_PORT_FEATURE_BAR1_SIZE_256K		 0x3
826
#define BCE_PORT_FEATURE_BAR1_SIZE_512K		 0x4
827
#define BCE_PORT_FEATURE_BAR1_SIZE_1M		 0x5
828
#define BCE_PORT_FEATURE_BAR1_SIZE_2M		 0x6
829
#define BCE_PORT_FEATURE_BAR1_SIZE_4M		 0x7
830
#define BCE_PORT_FEATURE_BAR1_SIZE_8M		 0x8
831
#define BCE_PORT_FEATURE_BAR1_SIZE_16M		 0x9
832
#define BCE_PORT_FEATURE_BAR1_SIZE_32M		 0xa
833
#define BCE_PORT_FEATURE_BAR1_SIZE_64M		 0xb
834
#define BCE_PORT_FEATURE_BAR1_SIZE_128M		 0xc
835
#define BCE_PORT_FEATURE_BAR1_SIZE_256M		 0xd
836
#define BCE_PORT_FEATURE_BAR1_SIZE_512M		 0xe
837
#define BCE_PORT_FEATURE_BAR1_SIZE_1G		 0xf
838

839
#define BCE_PORT_FEATURE_WOL			0xdc
840
#define BCE_PORT2_FEATURE_WOL			0x150
841
#define BCE_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS	 4
842
#define BCE_PORT_FEATURE_WOL_DEFAULT_MASK	 0x30
843
#define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE	 0
844
#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC	 0x10
845
#define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI	 0x20
846
#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI	 0x30
847
#define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK	 0xf
848
#define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG	 0
849
#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10HALF	 1
850
#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10FULL	 2
851
#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100HALF	 3
852
#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100FULL	 4
853
#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000HALF	 5
854
#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000FULL	 6
855
#define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000	 0x40
856
#define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP	 0x400
857
#define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP	 0x800
858

859
#define BCE_PORT_FEATURE_MBA			0xe0
860
#define BCE_PORT2_FEATURE_MBA			0x154
861
#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS	 0
862
#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK	 0x3
863
#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE	 0
864
#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL	 1
865
#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP	 2
866
#define BCE_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS	 2
867
#define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK	 0x3c
868
#define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG	 0
869
#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF	 0x4
870
#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL	 0x8
871
#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF	 0xc
872
#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL	 0x10
873
#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14
874
#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18
875
#define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40
876
#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S	 0
877
#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B	 0x80
878
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS	 8
879
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK	 0xff00
880
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED	 0
881
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K	 0x100
882
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K	 0x200
883
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K	 0x300
884
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K	 0x400
885
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K	 0x500
886
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K	 0x600
887
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K	 0x700
888
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K	 0x800
889
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K	 0x900
890
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K	 0xa00
891
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M	 0xb00
892
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M	 0xc00
893
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M	 0xd00
894
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M	 0xe00
895
#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M	 0xf00
896
#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS	 16
897
#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK	 0xf0000
898
#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS	 20
899
#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK	 0x300000
900
#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO	 0
901
#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS	 0x100000
902
#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H	 0x200000
903
#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H	 0x300000
904

905
#define BCE_PORT_FEATURE_IMD			0xe4
906
#define BCE_PORT2_FEATURE_IMD			0x158
907
#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT	 0
908
#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE	 1
909

910
#define BCE_PORT_FEATURE_VLAN			0xe8
911
#define BCE_PORT2_FEATURE_VLAN			0x15c
912
#define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK	 0xffff
913
#define BCE_PORT_FEATURE_MBA_VLAN_ENABLE	 0x10000
914

915
#define BCE_MFW_VER_PTR				0x00000014c
916

917
#define BCE_BC_STATE_RESET_TYPE			0x000001c0
918
#define BCE_BC_STATE_RESET_TYPE_SIG		 0x00005254
919
#define BCE_BC_STATE_RESET_TYPE_SIG_MASK	 0x0000ffff
920

921
#define BCE_BC_STATE_RESET_TYPE_NONE 			\
922
    (BCE_BC_STATE_RESET_TYPE_SIG | 0x00010000)
923
#define BCE_BC_STATE_RESET_TYPE_PCI			\
924
    (BCE_BC_STATE_RESET_TYPE_SIG | 0x00020000)
925
#define BCE_BC_STATE_RESET_TYPE_VAUX			\
926
    (BCE_BC_STATE_RESET_TYPE_SIG | 0x00030000)
927
#define BCE_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE
928
#define BCE_BC_STATE_RESET_TYPE_DRV_RESET		\
929
    (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_RESET)
930
#define BCE_BC_STATE_RESET_TYPE_DRV_UNLOAD		\
931
    (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_UNLOAD)
932
#define BCE_BC_STATE_RESET_TYPE_DRV_SHUTDOWN		\
933
    (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_SHUTDOWN)
934
#define BCE_BC_STATE_RESET_TYPE_DRV_WOL			\
935
    (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_WOL)
936
#define BCE_BC_STATE_RESET_TYPE_DRV_DIAG		\
937
    (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_DIAG)
938
#define BCE_BC_STATE_RESET_TYPE_VALUE(msg)		\
939
    (BCE_BC_STATE_RESET_TYPE_SIG | (msg))
940

941
#define BCE_BC_RESET_TYPE			0x000001c0
942

943
#define BCE_BC_STATE				0x000001c4
944
#define BCE_BC_STATE_ERR_MASK			0x0000ff00
945
#define BCE_BC_STATE_SIGN			0x42530000
946
#define BCE_BC_STATE_SIGN_MASK			0xffff0000
947
#define BCE_BC_STATE_BC1_START			(BCE_BC_STATE_SIGN | 0x1)
948
#define BCE_BC_STATE_GET_NVM_CFG1		(BCE_BC_STATE_SIGN | 0x2)
949
#define BCE_BC_STATE_PROG_BAR			(BCE_BC_STATE_SIGN | 0x3)
950
#define BCE_BC_STATE_INIT_VID			(BCE_BC_STATE_SIGN | 0x4)
951
#define BCE_BC_STATE_GET_NVM_CFG2		(BCE_BC_STATE_SIGN | 0x5)
952
#define BCE_BC_STATE_APPLY_WKARND		(BCE_BC_STATE_SIGN | 0x6)
953
#define BCE_BC_STATE_LOAD_BC2			(BCE_BC_STATE_SIGN | 0x7)
954
#define BCE_BC_STATE_GOING_BC2			(BCE_BC_STATE_SIGN | 0x8)
955
#define BCE_BC_STATE_GOING_DIAG			(BCE_BC_STATE_SIGN | 0x9)
956
#define BCE_BC_STATE_RT_FINAL_INIT		(BCE_BC_STATE_SIGN | 0x81)
957
#define BCE_BC_STATE_RT_WKARND			(BCE_BC_STATE_SIGN | 0x82)
958
#define BCE_BC_STATE_RT_DRV_PULSE		(BCE_BC_STATE_SIGN | 0x83)
959
#define BCE_BC_STATE_RT_FIOEVTS			(BCE_BC_STATE_SIGN | 0x84)
960
#define BCE_BC_STATE_RT_DRV_CMD			(BCE_BC_STATE_SIGN | 0x85)
961
#define BCE_BC_STATE_RT_LOW_POWER		(BCE_BC_STATE_SIGN | 0x86)
962
#define BCE_BC_STATE_RT_SET_WOL			(BCE_BC_STATE_SIGN | 0x87)
963
#define BCE_BC_STATE_RT_OTHER_FW		(BCE_BC_STATE_SIGN | 0x88)
964
#define BCE_BC_STATE_RT_GOING_D3		(BCE_BC_STATE_SIGN | 0x89)
965
#define BCE_BC_STATE_ERR_BAD_VERSION		(BCE_BC_STATE_SIGN | 0x0100)
966
#define BCE_BC_STATE_ERR_BAD_BC2_CRC		(BCE_BC_STATE_SIGN | 0x0200)
967
#define BCE_BC_STATE_ERR_BC1_LOOP		(BCE_BC_STATE_SIGN | 0x0300)
968
#define BCE_BC_STATE_ERR_UNKNOWN_CMD		(BCE_BC_STATE_SIGN | 0x0400)
969
#define BCE_BC_STATE_ERR_DRV_DEAD		(BCE_BC_STATE_SIGN | 0x0500)
970
#define BCE_BC_STATE_ERR_NO_RXP			(BCE_BC_STATE_SIGN | 0x0600)
971
#define BCE_BC_STATE_ERR_TOO_MANY_RBUF		(BCE_BC_STATE_SIGN | 0x0700)
972

973
#define BCE_BC_STATE_CONDITION			0x000001c8
974
#define BCE_CONDITION_INIT_POR			0x00000001
975
#define BCE_CONDITION_INIT_VAUX_AVAIL		0x00000002
976
#define BCE_CONDITION_INIT_PCI_AVAIL		0x00000004
977
#define BCE_CONDITION_INIT_PCI_RESET		0x00000008
978
#define BCE_CONDITION_INIT_HD_RESET		0x00000010 /* 5709/16 only */
979
#define BCE_CONDITION_DRV_PRESENT		0x00000100
980
#define BCE_CONDITION_LOW_POWER_LINK		0x00000200
981
#define BCE_CONDITION_CORE_RST_OCCURRED		0x00000400 /* 5709/16 only */
982
#define BCE_CONDITION_UNUSED			0x00000800
983
#define BCE_CONDITION_BUSY_EXPROM		0x00001000 /* 5706/08 only */
984

985
#define BCE_CONDITION_MFW_RUN_UNKNOWN		0x00000000
986
#define BCE_CONDITION_MFW_RUN_IPMI		0x00002000
987
#define BCE_CONDITION_MFW_RUN_UMP		0x00004000
988
#define BCE_CONDITION_MFW_RUN_NCSI		0x00006000
989
#define BCE_CONDITION_MFW_RUN_NONE		0x0000e000
990
#define BCE_CONDITION_MFW_RUN_MASK		0x0000e000
991

992
/* 5709/16 only */
993
#define BCE_CONDITION_PM_STATE_MASK		0x00030000
994
#define BCE_CONDITION_PM_STATE_FULL		0x00030000
995
#define BCE_CONDITION_PM_STATE_PREP		0x00020000
996
#define BCE_CONDITION_PM_STATE_UNPREP		0x00010000
997
#define BCE_CONDITION_PM_RESERVED		0x00000000
998

999
/* 5709/16 only */
1000
#define BCE_CONDITION_RXMODE_KEEP_VLAN		0x00040000
1001
#define BCE_CONDITION_DRV_WOL_ENABLED		0x00080000
1002
#define BCE_CONDITION_PORT_DISABLED		0x00100000
1003
#define BCE_CONDITION_DRV_MAYBE_OUT		0x00200000
1004
#define BCE_CONDITION_DPFW_DEAD			0x00400000
1005

1006
#define BCE_BC_STATE_DEBUG_CMD			0x000001dc
1007
#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE	0x42440000
1008
#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK	0xffff0000
1009
#define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK	0xffff
1010
#define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE	0xffff
1011

1012
#define	BCE_FW_EVT_CODE_MB			0x00000354
1013
#define	BCE_FW_EVT_CODE_SW_TIMER_EXPIRE_EVENT	0x00000000
1014
#define	BCE_FW_EVT_CODE_LINK_EVENT		0x00000001
1015

1016
#define	BCE_DRV_ACK_CAP_MB			0x00000364
1017
#define	BCE_DRV_ACK_CAP_SIGNATURE_MAGIC		0x35450000
1018

1019
#define	BCE_FW_CAP_MB				0x00000368
1020
#define	BCE_FW_CAP_SIGNATURE_MAGIC		0xaa550000
1021
#define	BCE_FW_ACK_SIGNATURE_MAGIC		0x52500000
1022
#define	BCE_FW_CAP_SIGNATURE_MAGIC_MASK		0xffff0000
1023
#define	BCE_FW_CAP_REMOTE_PHY_CAP		0x00000001
1024
#define	BCE_FW_CAP_REMOTE_PHY_PRESENT		0x00000002
1025
#define	BCE_FW_CAP_MFW_KEEP_VLAN		0x00000008
1026
#define	BCE_FW_CAP_BC_KEEP_VLAN			0x00000010
1027

1028
#define	BCE_RPHY_SERDES_LINK			0x00000374
1029

1030
#define	BCE_RPHY_COPPER_LINK			0x00000378
1031

1032
#define HOST_VIEW_SHMEM_BASE			0x167c00
1033

1034
/*
1035
 * PCI registers defined in the PCI 2.2 spec.
1036
 */
1037
#define BCE_PCI_PCIX_CMD		0x42
1038

1039
/****************************************************************************/
1040
/* Convenience definitions.                                                 */
1041
/****************************************************************************/
1042
#define BCE_PRINTF(fmt, args...)			\
1043
    device_printf(sc->bce_dev, fmt, ##args)
1044

1045
#define	BCE_LOCK_INIT(_sc, _name)			\
1046
    mtx_init(&(_sc)->bce_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
1047
#define	BCE_LOCK(_sc)			mtx_lock(&(_sc)->bce_mtx)
1048
#define	BCE_LOCK_ASSERT(_sc)		mtx_assert(&(_sc)->bce_mtx, MA_OWNED)
1049
#define	BCE_UNLOCK(_sc)			mtx_unlock(&(_sc)->bce_mtx)
1050
#define	BCE_LOCK_DESTROY(_sc)		mtx_destroy(&(_sc)->bce_mtx)
1051

1052
#ifdef BCE_DEBUG
1053
#define	REG_WR(sc, offset, val)		bce_reg_wr(sc, offset, val)
1054
#define	REG_WR16(sc, offset, val)	bce_reg_wr16(sc, offset, val)
1055
#define	REG_RD(sc, offset)		bce_reg_rd(sc, offset)
1056
#else
1057
#define	REG_WR(sc, offset, val)				\
1058
    bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val)
1059
#define	REG_WR16(sc, offset, val)			\
1060
    bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val)
1061
#define	REG_RD(sc, offset)	 			\
1062
    bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset)
1063
#endif
1064

1065
#define	REG_RD_IND(sc, offset)		bce_reg_rd_ind(sc, offset)
1066
#define	REG_WR_IND(sc, offset, val)	bce_reg_wr_ind(sc, offset, val)
1067
#define	CTX_WR(sc, cid_addr, offset, val)bce_ctx_wr(sc, cid_addr, offset, val)
1068
#define	CTX_RD(sc, cid_addr, offset)	bce_ctx_rd(sc, cid_addr, offset)
1069

1070
#define	BCE_SETBIT(sc, reg, x)				\
1071
    REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
1072
#define	BCE_CLRBIT(sc, reg, x)				\
1073
    REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
1074
#define	PCI_SETBIT(dev, reg, x, s)			\
1075
    pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
1076
#define	PCI_CLRBIT(dev, reg, x, s)			\
1077
    pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
1078

1079
#define	BCE_STATS(x)			(u_long) stats->stat_ ## x ## _lo
1080

1081
#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
1082
#define	BCE_ADDR_LO(y)			((u64) (y) & 0xFFFFFFFF)
1083
#define	BCE_ADDR_HI(y)			((u64) (y) >> 32)
1084
#else
1085
#define	BCE_ADDR_LO(y)			((u32)y)
1086
#define	BCE_ADDR_HI(y)			(0)
1087
#endif
1088

1089
/****************************************************************************/
1090
/* Do not modify any of the following data structures, they are generated   */
1091
/* from RTL code.                                                           */
1092
/*                                                                          */
1093
/* Begin machine generated definitions.                                     */
1094
/****************************************************************************/
1095

1096
/*
1097
 *  tx_bd definition
1098
 */
1099
struct tx_bd {
1100
	u32 tx_bd_haddr_hi;
1101
	u32 tx_bd_haddr_lo;
1102
	u32 tx_bd_mss_nbytes;
1103
	u16 tx_bd_flags;
1104
#define TX_BD_FLAGS_CONN_FAULT		(1<<0)
1105
#define TX_BD_FLAGS_TCP_UDP_CKSUM	(1<<1)
1106
#define TX_BD_FLAGS_IP_CKSUM		(1<<2)
1107
#define TX_BD_FLAGS_VLAN_TAG		(1<<3)
1108
#define TX_BD_FLAGS_COAL_NOW		(1<<4)
1109
#define TX_BD_FLAGS_DONT_GEN_CRC	(1<<5)
1110
#define TX_BD_FLAGS_END			(1<<6)
1111
#define TX_BD_FLAGS_START			(1<<7)
1112
#define TX_BD_FLAGS_SW_OPTION_WORD	(0x1f<<8)
1113
#define TX_BD_FLAGS_SW_FLAGS		(1<<13)
1114
#define TX_BD_FLAGS_SW_SNAP		(1<<14)
1115
#define TX_BD_FLAGS_SW_LSO			(1<<15)
1116
	u16 tx_bd_vlan_tag;
1117
};
1118

1119
/*
1120
 *  rx_bd definition
1121
 */
1122
struct rx_bd {
1123
	u32 rx_bd_haddr_hi;
1124
	u32 rx_bd_haddr_lo;
1125
	u32 rx_bd_len;
1126
	u32 rx_bd_flags;
1127
#define RX_BD_FLAGS_NOPUSH		(1<<0)
1128
#define RX_BD_FLAGS_DUMMY		(1<<1)
1129
#define RX_BD_FLAGS_END		(1<<2)
1130
#define RX_BD_FLAGS_START		(1<<3)
1131
};
1132

1133
/*
1134
 *  status_block definition
1135
 */
1136
struct status_block {
1137
	u32 status_attn_bits;
1138
		#define STATUS_ATTN_BITS_LINK_STATE		(1L<<0)
1139
		#define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT	(1L<<1)
1140
		#define STATUS_ATTN_BITS_TX_BD_READ_ABORT	(1L<<2)
1141
		#define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT	(1L<<3)
1142
		#define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT	(1L<<4)
1143
		#define STATUS_ATTN_BITS_TX_DMA_ABORT		(1L<<5)
1144
		#define STATUS_ATTN_BITS_TX_PATCHUP_ABORT	(1L<<6)
1145
		#define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT	(1L<<7)
1146
		#define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT	(1L<<8)
1147
		#define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
1148
		#define STATUS_ATTN_BITS_RX_MBUF_ABORT		(1L<<10)
1149
		#define STATUS_ATTN_BITS_RX_LOOKUP_ABORT	(1L<<11)
1150
		#define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT	(1L<<12)
1151
		#define STATUS_ATTN_BITS_RX_V2P_ABORT		(1L<<13)
1152
		#define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT	(1L<<14)
1153
		#define STATUS_ATTN_BITS_RX_DMA_ABORT		(1L<<15)
1154
		#define STATUS_ATTN_BITS_COMPLETION_ABORT	(1L<<16)
1155
		#define STATUS_ATTN_BITS_HOST_COALESCE_ABORT	(1L<<17)
1156
		#define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT	(1L<<18)
1157
		#define STATUS_ATTN_BITS_CONTEXT_ABORT		(1L<<19)
1158
		#define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT	(1L<<20)
1159
		#define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT	(1L<<21)
1160
		#define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT	(1L<<22)
1161
		#define STATUS_ATTN_BITS_MAC_ABORT		(1L<<23)
1162
		#define STATUS_ATTN_BITS_TIMER_ABORT		(1L<<24)
1163
		#define STATUS_ATTN_BITS_DMAE_ABORT		(1L<<25)
1164
		#define STATUS_ATTN_BITS_FLSH_ABORT		(1L<<26)
1165
		#define STATUS_ATTN_BITS_GRC_ABORT		(1L<<27)
1166
		#define STATUS_ATTN_BITS_PARITY_ERROR		(1L<<31)
1167

1168
	u32 status_attn_bits_ack;
1169
#if defined(__BIG_ENDIAN)
1170
	u16 status_tx_quick_consumer_index0;
1171
	u16 status_tx_quick_consumer_index1;
1172
	u16 status_tx_quick_consumer_index2;
1173
	u16 status_tx_quick_consumer_index3;
1174
	u16 status_rx_quick_consumer_index0;
1175
	u16 status_rx_quick_consumer_index1;
1176
	u16 status_rx_quick_consumer_index2;
1177
	u16 status_rx_quick_consumer_index3;
1178
	u16 status_rx_quick_consumer_index4;
1179
	u16 status_rx_quick_consumer_index5;
1180
	u16 status_rx_quick_consumer_index6;
1181
	u16 status_rx_quick_consumer_index7;
1182
	u16 status_rx_quick_consumer_index8;
1183
	u16 status_rx_quick_consumer_index9;
1184
	u16 status_rx_quick_consumer_index10;
1185
	u16 status_rx_quick_consumer_index11;
1186
	u16 status_rx_quick_consumer_index12;
1187
	u16 status_rx_quick_consumer_index13;
1188
	u16 status_rx_quick_consumer_index14;
1189
	u16 status_rx_quick_consumer_index15;
1190
	u16 status_completion_producer_index;
1191
	u16 status_cmd_consumer_index;
1192
	u16 status_idx;
1193
	u16 status_unused;
1194
#elif defined(__LITTLE_ENDIAN)
1195
	u16 status_tx_quick_consumer_index1;
1196
	u16 status_tx_quick_consumer_index0;
1197
	u16 status_tx_quick_consumer_index3;
1198
	u16 status_tx_quick_consumer_index2;
1199
	u16 status_rx_quick_consumer_index1;
1200
	u16 status_rx_quick_consumer_index0;
1201
	u16 status_rx_quick_consumer_index3;
1202
	u16 status_rx_quick_consumer_index2;
1203
	u16 status_rx_quick_consumer_index5;
1204
	u16 status_rx_quick_consumer_index4;
1205
	u16 status_rx_quick_consumer_index7;
1206
	u16 status_rx_quick_consumer_index6;
1207
	u16 status_rx_quick_consumer_index9;
1208
	u16 status_rx_quick_consumer_index8;
1209
	u16 status_rx_quick_consumer_index11;
1210
	u16 status_rx_quick_consumer_index10;
1211
	u16 status_rx_quick_consumer_index13;
1212
	u16 status_rx_quick_consumer_index12;
1213
	u16 status_rx_quick_consumer_index15;
1214
	u16 status_rx_quick_consumer_index14;
1215
	u16 status_cmd_consumer_index;
1216
	u16 status_completion_producer_index;
1217
	u16 status_unused;
1218
	u16 status_idx;
1219
#endif
1220
};
1221

1222
/*
1223
 *  statistics_block definition
1224
 */
1225
struct statistics_block {
1226
	u32 stat_IfHCInOctets_hi;
1227
	u32 stat_IfHCInOctets_lo;
1228
	u32 stat_IfHCInBadOctets_hi;
1229
	u32 stat_IfHCInBadOctets_lo;
1230
	u32 stat_IfHCOutOctets_hi;
1231
	u32 stat_IfHCOutOctets_lo;
1232
	u32 stat_IfHCOutBadOctets_hi;
1233
	u32 stat_IfHCOutBadOctets_lo;
1234
	u32 stat_IfHCInUcastPkts_hi;
1235
	u32 stat_IfHCInUcastPkts_lo;
1236
	u32 stat_IfHCInMulticastPkts_hi;
1237
	u32 stat_IfHCInMulticastPkts_lo;
1238
	u32 stat_IfHCInBroadcastPkts_hi;
1239
	u32 stat_IfHCInBroadcastPkts_lo;
1240
	u32 stat_IfHCOutUcastPkts_hi;
1241
	u32 stat_IfHCOutUcastPkts_lo;
1242
	u32 stat_IfHCOutMulticastPkts_hi;
1243
	u32 stat_IfHCOutMulticastPkts_lo;
1244
	u32 stat_IfHCOutBroadcastPkts_hi;
1245
	u32 stat_IfHCOutBroadcastPkts_lo;
1246
	u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
1247
	u32 stat_Dot3StatsCarrierSenseErrors;
1248
	u32 stat_Dot3StatsFCSErrors;
1249
	u32 stat_Dot3StatsAlignmentErrors;
1250
	u32 stat_Dot3StatsSingleCollisionFrames;
1251
	u32 stat_Dot3StatsMultipleCollisionFrames;
1252
	u32 stat_Dot3StatsDeferredTransmissions;
1253
	u32 stat_Dot3StatsExcessiveCollisions;
1254
	u32 stat_Dot3StatsLateCollisions;
1255
	u32 stat_EtherStatsCollisions;
1256
	u32 stat_EtherStatsFragments;
1257
	u32 stat_EtherStatsJabbers;
1258
	u32 stat_EtherStatsUndersizePkts;
1259
	u32 stat_EtherStatsOversizePkts;
1260
	u32 stat_EtherStatsPktsRx64Octets;
1261
	u32 stat_EtherStatsPktsRx65Octetsto127Octets;
1262
	u32 stat_EtherStatsPktsRx128Octetsto255Octets;
1263
	u32 stat_EtherStatsPktsRx256Octetsto511Octets;
1264
	u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
1265
	u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
1266
	u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
1267
	u32 stat_EtherStatsPktsTx64Octets;
1268
	u32 stat_EtherStatsPktsTx65Octetsto127Octets;
1269
	u32 stat_EtherStatsPktsTx128Octetsto255Octets;
1270
	u32 stat_EtherStatsPktsTx256Octetsto511Octets;
1271
	u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
1272
	u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
1273
	u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
1274
	u32 stat_XonPauseFramesReceived;
1275
	u32 stat_XoffPauseFramesReceived;
1276
	u32 stat_OutXonSent;
1277
	u32 stat_OutXoffSent;
1278
	u32 stat_FlowControlDone;
1279
	u32 stat_MacControlFramesReceived;
1280
	u32 stat_XoffStateEntered;
1281
	u32 stat_IfInFramesL2FilterDiscards;
1282
	u32 stat_IfInRuleCheckerDiscards;
1283
	u32 stat_IfInFTQDiscards;
1284
	u32 stat_IfInMBUFDiscards;
1285
	u32 stat_IfInRuleCheckerP4Hit;
1286
	u32 stat_CatchupInRuleCheckerDiscards;
1287
	u32 stat_CatchupInFTQDiscards;
1288
	u32 stat_CatchupInMBUFDiscards;
1289
	u32 stat_CatchupInRuleCheckerP4Hit;
1290
	u32 stat_GenStat00;
1291
	u32 stat_GenStat01;
1292
	u32 stat_GenStat02;
1293
	u32 stat_GenStat03;
1294
	u32 stat_GenStat04;
1295
	u32 stat_GenStat05;
1296
	u32 stat_GenStat06;
1297
	u32 stat_GenStat07;
1298
	u32 stat_GenStat08;
1299
	u32 stat_GenStat09;
1300
	u32 stat_GenStat10;
1301
	u32 stat_GenStat11;
1302
	u32 stat_GenStat12;
1303
	u32 stat_GenStat13;
1304
	u32 stat_GenStat14;
1305
	u32 stat_GenStat15;
1306
};
1307

1308
/*
1309
 *  l2_fhdr definition
1310
 */
1311
struct l2_fhdr {
1312
	u32 l2_fhdr_status;
1313
		#define L2_FHDR_STATUS_RULE_CLASS	(0x7<<0)
1314
		#define L2_FHDR_STATUS_RULE_P2		(1<<3)
1315
		#define L2_FHDR_STATUS_RULE_P3		(1<<4)
1316
		#define L2_FHDR_STATUS_RULE_P4		(1<<5)
1317
		#define L2_FHDR_STATUS_L2_VLAN_TAG	(1<<6)
1318
		#define L2_FHDR_STATUS_L2_LLC_SNAP	(1<<7)
1319
		#define L2_FHDR_STATUS_RSS_HASH		(1<<8)
1320
		#define L2_FHDR_STATUS_IP_DATAGRAM	(1<<13)
1321
		#define L2_FHDR_STATUS_TCP_SEGMENT	(1<<14)
1322
		#define L2_FHDR_STATUS_UDP_DATAGRAM	(1<<15)
1323

1324
		#define L2_FHDR_STATUS_SPLIT		(1<<16)
1325
		#define L2_FHDR_ERRORS_BAD_CRC		(1<<17)
1326
		#define L2_FHDR_ERRORS_PHY_DECODE	(1<<18)
1327
		#define L2_FHDR_ERRORS_ALIGNMENT	(1<<19)
1328
		#define L2_FHDR_ERRORS_TOO_SHORT	(1<<20)
1329
		#define L2_FHDR_ERRORS_GIANT_FRAME	(1<<21)
1330
		#define L2_FHDR_ERRORS_IPV4_BAD_LEN	(1<<22)
1331
		#define L2_FHDR_ERRORS_TCP_XSUM		(1<<28)
1332
		#define L2_FHDR_ERRORS_UDP_XSUM		(1<<31)
1333

1334
	u32 l2_fhdr_hash;
1335
#if defined(__BIG_ENDIAN)
1336
	u16 l2_fhdr_pkt_len;
1337
	u16 l2_fhdr_vlan_tag;
1338
	u16 l2_fhdr_ip_xsum;
1339
	u16 l2_fhdr_tcp_udp_xsum;
1340
#elif defined(__LITTLE_ENDIAN)
1341
	u16 l2_fhdr_vlan_tag;
1342
	u16 l2_fhdr_pkt_len;
1343
	u16 l2_fhdr_tcp_udp_xsum;
1344
	u16 l2_fhdr_ip_xsum;
1345
#endif
1346
};
1347

1348
#define BCE_L2FHDR_PRINTFB	\
1349
	"\20"				\
1350
	"\40UDP_XSUM_ERR"	\
1351
	"\37b30"			\
1352
	"\36b29"			\
1353
	"\35TCP_XSUM_ERR"	\
1354
	"\34b27"			\
1355
	"\33b26"			\
1356
	"\32b25"			\
1357
	"\31b24"			\
1358
	"\30b23"			\
1359
	"\27IPv4_BAL_LEN"	\
1360
	"\26GIANT_ERR"		\
1361
	"\25SHORT_ERR"		\
1362
	"\24ALIGN_ERR"		\
1363
	"\23PHY_ERR"		\
1364
	"\22CRC_ERR"		\
1365
	"\21SPLIT"			\
1366
	"\20UDP"			\
1367
	"\17TCP"			\
1368
	"\16IP"				\
1369
	"\15SORT_b3"		\
1370
	"\14SORT_b2"		\
1371
	"\13SORT_b1"		\
1372
	"\12SORT_b0"		\
1373
	"\11RSS"			\
1374
	"\10SNAP"			\
1375
	"\07VLAN"			\
1376
	"\06P4"				\
1377
	"\05P3"				\
1378
	"\04P2"				\
1379
	"\03RULE_b2"		\
1380
	"\02RULE_b1"		\
1381
	"\01RULE_b0"
1382

1383
/*
1384
 *  l2_tx_context definition (5706 and 5708)
1385
 */
1386
#define BCE_L2CTX_TX_TYPE			0x00000000
1387
#define BCE_L2CTX_TX_TYPE_SIZE_L2		((0xc0/0x20)<<16)
1388
#define BCE_L2CTX_TX_TYPE_TYPE			(0xf<<28)
1389
#define BCE_L2CTX_TX_TYPE_TYPE_EMPTY		(0<<28)
1390
#define BCE_L2CTX_TX_TYPE_TYPE_L2		(1<<28)
1391

1392
#define BCE_L2CTX_TX_HOST_BIDX			0x00000088
1393
#define BCE_L2CTX_TX_EST_NBD			0x00000088
1394
#define BCE_L2CTX_TX_CMD_TYPE			0x00000088
1395
#define BCE_L2CTX_TX_CMD_TYPE_TYPE		(0xf<<24)
1396
#define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2		(0<<24)
1397
#define BCE_L2CTX_TX_CMD_TYPE_TYPE_TCP		(1<<24)
1398

1399
#define BCE_L2CTX_TX_HOST_BSEQ			0x00000090
1400
#define BCE_L2CTX_TX_TSCH_BSEQ			0x00000094
1401
#define BCE_L2CTX_TX_TBDR_BSEQ			0x00000098
1402
#define BCE_L2CTX_TX_TBDR_BOFF			0x0000009c
1403
#define BCE_L2CTX_TX_TBDR_BIDX			0x0000009c
1404
#define BCE_L2CTX_TX_TBDR_BHADDR_HI		0x000000a0
1405
#define BCE_L2CTX_TX_TBDR_BHADDR_LO		0x000000a4
1406
#define BCE_L2CTX_TX_TXP_BOFF			0x000000a8
1407
#define BCE_L2CTX_TX_TXP_BIDX			0x000000a8
1408
#define BCE_L2CTX_TX_TXP_BSEQ			0x000000ac
1409

1410
/*
1411
 *  l2_tx_context definition (5709 and 5716)
1412
 */
1413
#define BCE_L2CTX_TX_TYPE_XI			0x00000080
1414
#define BCE_L2CTX_TX_TYPE_SIZE_L2_XI		((0xc0/0x20)<<16)
1415
#define BCE_L2CTX_TX_TYPE_TYPE_XI		(0xf<<28)
1416
#define BCE_L2CTX_TX_TYPE_TYPE_EMPTY_XI		(0<<28)
1417
#define BCE_L2CTX_TX_TYPE_TYPE_L2_XI		(1<<28)
1418

1419
#define BCE_L2CTX_TX_CMD_TYPE_XI		0x00000240
1420
#define BCE_L2CTX_TX_CMD_TYPE_TYPE_XI		(0xf<<24)
1421
#define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI	(0<<24)
1422
#define BCE_L2CTX_TX_CMD_TYPE_TYPE_TCP_XI	(1<<24)
1423

1424
#define BCE_L2CTX_TX_HOST_BIDX_XI		0x00000240
1425
#define BCE_L2CTX_TX_HOST_BSEQ_XI		0x00000248
1426
#define BCE_L2CTX_TX_TBDR_BHADDR_HI_XI		0x00000258
1427
#define BCE_L2CTX_TX_TBDR_BHADDR_LO_XI		0x0000025c
1428

1429
/*
1430
 *  l2_rx_context definition (5706, 5708, 5709, and 5716)
1431
 */
1432
#define BCE_L2CTX_RX_WATER_MARK			0x00000000
1433
#define BCE_L2CTX_RX_LO_WATER_MARK_SHIFT	0
1434
#define BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT	32
1435
#define BCE_L2CTX_RX_LO_WATER_MARK_SCALE	4
1436
#define BCE_L2CTX_RX_LO_WATER_MARK_DIS		0
1437
#define BCE_L2CTX_RX_HI_WATER_MARK_SHIFT	4
1438
#define BCE_L2CTX_RX_HI_WATER_MARK_SCALE	16
1439
#define BCE_L2CTX_RX_WATER_MARKS_MSK		0x000000ff
1440

1441
#define BCE_L2CTX_RX_BD_PRE_READ		0x00000000
1442
#define BCE_L2CTX_RX_BD_PRE_READ_SHIFT		8
1443

1444
#define BCE_L2CTX_RX_CTX_SIZE			0x00000000
1445
#define BCE_L2CTX_RX_CTX_SIZE_SHIFT		16
1446
#define BCE_L2CTX_RX_CTX_TYPE_SIZE_L2	\
1447
    ((0x20/20)<<BCE_L2CTX_RX_CTX_SIZE_SHIFT)
1448

1449
#define BCE_L2CTX_RX_CTX_TYPE			0x00000000
1450
#define BCE_L2CTX_RX_CTX_TYPE_SHIFT		24
1451

1452
#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE	(0xf<<28)
1453
#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED	(0<<28)
1454
#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE	(1<<28)
1455

1456
#define BCE_L2CTX_RX_HOST_BDIDX			0x00000004
1457
#define BCE_L2CTX_RX_HOST_BSEQ			0x00000008
1458
#define BCE_L2CTX_RX_NX_BSEQ			0x0000000c
1459
#define BCE_L2CTX_RX_NX_BDHADDR_HI		0x00000010
1460
#define BCE_L2CTX_RX_NX_BDHADDR_LO		0x00000014
1461
#define BCE_L2CTX_RX_NX_BDIDX			0x00000018
1462

1463
#define BCE_L2CTX_RX_HOST_PG_BDIDX		0x00000044
1464
#define BCE_L2CTX_RX_PG_BUF_SIZE		0x00000048
1465
#define BCE_L2CTX_RX_RBDC_KEY			0x0000004c
1466
#define BCE_L2CTX_RX_RBDC_JUMBO_KEY		0x3ffe
1467
#define BCE_L2CTX_RX_NX_PG_BDHADDR_HI		0x00000050
1468
#define BCE_L2CTX_RX_NX_PG_BDHADDR_LO		0x00000054
1469
#define BCE_L2CTX_RX_NX_PG_BDIDX		0x00000058
1470

1471
/*
1472
 *  l2_mq definitions (5706, 5708, 5709, and 5716)
1473
 */
1474

1475
#define BCE_L2MQ_RX_HOST_BDIDX			0x00000004
1476
#define BCE_L2MQ_RX_HOST_BSEQ			0x00000008
1477
#define BCE_L2MQ_RX_HOST_PG_BDIDX		0x00000044
1478

1479
#define BCE_L2MQ_TX_HOST_BIDX			0x00000088
1480
#define BCE_L2MQ_TX_HOST_BSEQ			0x00000090
1481

1482
/*
1483
 *  pci_config_l definition
1484
 *  offset: 0000
1485
 */
1486
#define BCE_PCICFG_MISC_CONFIG				0x00000068
1487
#define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP	 		(1L<<2)
1488
#define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP	 (1L<<3)
1489
#define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA		 (1L<<5)
1490
#define BCE_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP	 (1L<<6)
1491
#define BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA		 (1L<<7)
1492
#define BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ		 (1L<<8)
1493
#define BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY		 (1L<<9)
1494
#define BCE_PCICFG_MISC_CONFIG_ASIC_METAL_REV		 (0xffL<<16)
1495
#define BCE_PCICFG_MISC_CONFIG_ASIC_BASE_REV		 (0xfL<<24)
1496
#define BCE_PCICFG_MISC_CONFIG_ASIC_ID			 (0xfL<<28)
1497
#define BCE_PCICFG_MISC_CONFIG_ASIC_REV			 (0xffffL<<16)
1498

1499
#define BCE_PCICFG_MISC_STATUS				0x0000006c
1500
#define BCE_PCICFG_MISC_STATUS_INTA_VALUE		 (1L<<0)
1501
#define BCE_PCICFG_MISC_STATUS_32BIT_DET		 (1L<<1)
1502
#define BCE_PCICFG_MISC_STATUS_M66EN			 (1L<<2)
1503
#define BCE_PCICFG_MISC_STATUS_PCIX_DET		 (1L<<3)
1504
#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED		 (0x3L<<4)
1505
#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66		 (0L<<4)
1506
#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_100		 (1L<<4)
1507
#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_133		 (2L<<4)
1508
#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE	 (3L<<4)
1509

1510
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS		0x00000070
1511
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET	 (0xfL<<0)
1512
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ	 (0L<<0)
1513
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ	 (1L<<0)
1514
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ	 (2L<<0)
1515
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ	 (3L<<0)
1516
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ	 (4L<<0)
1517
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ	 (5L<<0)
1518
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ	 (6L<<0)
1519
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ	 (7L<<0)
1520
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW	 (0xfL<<0)
1521
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE	 (1L<<6)
1522
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT	 (1L<<7)
1523
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC	 (0x7L<<8)
1524
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF	 (0L<<8)
1525
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12	 (1L<<8)
1526
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6	 (2L<<8)
1527
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62	 (4L<<8)
1528
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD	 (1L<<11)
1529
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED	 (0xfL<<12)
1530
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100	 (0L<<12)
1531
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80	 (1L<<12)
1532
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50	 (2L<<12)
1533
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40	 (4L<<12)
1534
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25	 (8L<<12)
1535
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP	 (1L<<16)
1536
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP	 (1L<<17)
1537
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18	 (1L<<18)
1538
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET	 (1L<<19)
1539
#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED	 (0xfffL<<20)
1540

1541
#define BCE_PCICFG_REG_WINDOW_ADDRESS			0x00000078
1542
#define BCE_PCICFG_REG_WINDOW				0x00000080
1543
#define BCE_PCICFG_INT_ACK_CMD				0x00000084
1544
#define BCE_PCICFG_INT_ACK_CMD_INDEX			 (0xffffL<<0)
1545
#define BCE_PCICFG_INT_ACK_CMD_INDEX_VALID		 (1L<<16)
1546
#define BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM	 (1L<<17)
1547
#define BCE_PCICFG_INT_ACK_CMD_MASK_INT		 (1L<<18)
1548

1549
#define BCE_PCICFG_STATUS_BIT_SET_CMD			0x00000088
1550
#define BCE_PCICFG_STATUS_BIT_CLEAR_CMD		0x0000008c
1551
#define BCE_PCICFG_MAILBOX_QUEUE_ADDR			0x00000090
1552
#define BCE_PCICFG_MAILBOX_QUEUE_DATA			0x00000094
1553

1554
/*
1555
 *  pci_reg definition
1556
 *  offset: 0x400
1557
 */
1558
#define BCE_PCI_GRC_WINDOW_ADDR			0x00000400
1559
#define BCE_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE	 (0x3ffffL<<8)
1560

1561
#define BCE_PCI_CONFIG_1				0x00000404
1562
#define BCE_PCI_CONFIG_1_READ_BOUNDARY			 (0x7L<<8)
1563
#define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF		 (0L<<8)
1564
#define BCE_PCI_CONFIG_1_READ_BOUNDARY_16		 (1L<<8)
1565
#define BCE_PCI_CONFIG_1_READ_BOUNDARY_32		 (2L<<8)
1566
#define BCE_PCI_CONFIG_1_READ_BOUNDARY_64		 (3L<<8)
1567
#define BCE_PCI_CONFIG_1_READ_BOUNDARY_128		 (4L<<8)
1568
#define BCE_PCI_CONFIG_1_READ_BOUNDARY_256		 (5L<<8)
1569
#define BCE_PCI_CONFIG_1_READ_BOUNDARY_512		 (6L<<8)
1570
#define BCE_PCI_CONFIG_1_READ_BOUNDARY_1024		 (7L<<8)
1571
#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY		 (0x7L<<11)
1572
#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF		 (0L<<11)
1573
#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_16		 (1L<<11)
1574
#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_32		 (2L<<11)
1575
#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_64		 (3L<<11)
1576
#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_128		 (4L<<11)
1577
#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_256		 (5L<<11)
1578
#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_512		 (6L<<11)
1579
#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_1024		 (7L<<11)
1580

1581
#define BCE_PCI_CONFIG_2				0x00000408
1582
#define BCE_PCI_CONFIG_2_BAR1_SIZE			 (0xfL<<0)
1583
#define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED		 (0L<<0)
1584
#define BCE_PCI_CONFIG_2_BAR1_SIZE_64K			 (1L<<0)
1585
#define BCE_PCI_CONFIG_2_BAR1_SIZE_128K		 (2L<<0)
1586
#define BCE_PCI_CONFIG_2_BAR1_SIZE_256K		 (3L<<0)
1587
#define BCE_PCI_CONFIG_2_BAR1_SIZE_512K		 (4L<<0)
1588
#define BCE_PCI_CONFIG_2_BAR1_SIZE_1M			 (5L<<0)
1589
#define BCE_PCI_CONFIG_2_BAR1_SIZE_2M			 (6L<<0)
1590
#define BCE_PCI_CONFIG_2_BAR1_SIZE_4M			 (7L<<0)
1591
#define BCE_PCI_CONFIG_2_BAR1_SIZE_8M			 (8L<<0)
1592
#define BCE_PCI_CONFIG_2_BAR1_SIZE_16M			 (9L<<0)
1593
#define BCE_PCI_CONFIG_2_BAR1_SIZE_32M			 (10L<<0)
1594
#define BCE_PCI_CONFIG_2_BAR1_SIZE_64M			 (11L<<0)
1595
#define BCE_PCI_CONFIG_2_BAR1_SIZE_128M		 (12L<<0)
1596
#define BCE_PCI_CONFIG_2_BAR1_SIZE_256M		 (13L<<0)
1597
#define BCE_PCI_CONFIG_2_BAR1_SIZE_512M		 (14L<<0)
1598
#define BCE_PCI_CONFIG_2_BAR1_SIZE_1G			 (15L<<0)
1599
#define BCE_PCI_CONFIG_2_BAR1_64ENA			 (1L<<4)
1600
#define BCE_PCI_CONFIG_2_EXP_ROM_RETRY			 (1L<<5)
1601
#define BCE_PCI_CONFIG_2_CFG_CYCLE_RETRY		 (1L<<6)
1602
#define BCE_PCI_CONFIG_2_FIRST_CFG_DONE		 (1L<<7)
1603
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE			 (0xffL<<8)
1604
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED		 (0L<<8)
1605
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1K		 (1L<<8)
1606
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2K		 (2L<<8)
1607
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4K		 (3L<<8)
1608
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8K		 (4L<<8)
1609
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16K		 (5L<<8)
1610
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_32K		 (6L<<8)
1611
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_64K		 (7L<<8)
1612
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_128K		 (8L<<8)
1613
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_256K		 (9L<<8)
1614
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_512K		 (10L<<8)
1615
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1M		 (11L<<8)
1616
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2M		 (12L<<8)
1617
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4M		 (13L<<8)
1618
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8M		 (14L<<8)
1619
#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16M		 (15L<<8)
1620
#define BCE_PCI_CONFIG_2_MAX_SPLIT_LIMIT		 (0x1fL<<16)
1621
#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT		 (0x3L<<21)
1622
#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512		 (0L<<21)
1623
#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_1K		 (1L<<21)
1624
#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_2K		 (2L<<21)
1625
#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_4K		 (3L<<21)
1626
#define BCE_PCI_CONFIG_2_FORCE_32_BIT_MSTR		 (1L<<23)
1627
#define BCE_PCI_CONFIG_2_FORCE_32_BIT_TGT		 (1L<<24)
1628
#define BCE_PCI_CONFIG_2_KEEP_REQ_ASSERT		 (1L<<25)
1629

1630
#define BCE_PCI_CONFIG_3				0x0000040c
1631
#define BCE_PCI_CONFIG_3_STICKY_BYTE			 (0xffL<<0)
1632
#define BCE_PCI_CONFIG_3_FORCE_PME			 (1L<<24)
1633
#define BCE_PCI_CONFIG_3_PME_STATUS			 (1L<<25)
1634
#define BCE_PCI_CONFIG_3_PME_ENABLE			 (1L<<26)
1635
#define BCE_PCI_CONFIG_3_PM_STATE			 (0x3L<<27)
1636
#define BCE_PCI_CONFIG_3_VAUX_PRESET			 (1L<<30)
1637
#define BCE_PCI_CONFIG_3_PCI_POWER			 (1L<<31)
1638

1639
#define BCE_PCI_PM_DATA_A				0x00000410
1640
#define BCE_PCI_PM_DATA_A_PM_DATA_0_PRG		 (0xffL<<0)
1641
#define BCE_PCI_PM_DATA_A_PM_DATA_1_PRG		 (0xffL<<8)
1642
#define BCE_PCI_PM_DATA_A_PM_DATA_2_PRG		 (0xffL<<16)
1643
#define BCE_PCI_PM_DATA_A_PM_DATA_3_PRG		 (0xffL<<24)
1644

1645
#define BCE_PCI_PM_DATA_B				0x00000414
1646
#define BCE_PCI_PM_DATA_B_PM_DATA_4_PRG		 (0xffL<<0)
1647
#define BCE_PCI_PM_DATA_B_PM_DATA_5_PRG		 (0xffL<<8)
1648
#define BCE_PCI_PM_DATA_B_PM_DATA_6_PRG		 (0xffL<<16)
1649
#define BCE_PCI_PM_DATA_B_PM_DATA_7_PRG		 (0xffL<<24)
1650

1651
#define BCE_PCI_SWAP_DIAG0				0x00000418
1652
#define BCE_PCI_SWAP_DIAG1				0x0000041c
1653
#define BCE_PCI_EXP_ROM_ADDR				0x00000420
1654
#define BCE_PCI_EXP_ROM_ADDR_ADDRESS			 (0x3fffffL<<2)
1655
#define BCE_PCI_EXP_ROM_ADDR_REQ			 (1L<<31)
1656

1657
#define BCE_PCI_EXP_ROM_DATA				0x00000424
1658
#define BCE_PCI_VPD_INTF				0x00000428
1659
#define BCE_PCI_VPD_INTF_INTF_REQ			 (1L<<0)
1660

1661
#define BCE_PCI_VPD_ADDR_FLAG				0x0000042c
1662
#define BCE_PCI_VPD_ADDR_FLAG_ADDRESS			 (0x1fff<<2)
1663
#define BCE_PCI_VPD_ADDR_FLAG_WR			 (1<<15)
1664

1665
#define BCE_PCI_VPD_DATA				0x00000430
1666
#define BCE_PCI_ID_VAL1				0x00000434
1667
#define BCE_PCI_ID_VAL1_DEVICE_ID			 (0xffffL<<0)
1668
#define BCE_PCI_ID_VAL1_VENDOR_ID			 (0xffffL<<16)
1669

1670
#define BCE_PCI_ID_VAL2				0x00000438
1671
#define BCE_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID		 (0xffffL<<0)
1672
#define BCE_PCI_ID_VAL2_SUBSYSTEM_ID			 (0xffffL<<16)
1673

1674
#define BCE_PCI_ID_VAL3				0x0000043c
1675
#define BCE_PCI_ID_VAL3_CLASS_CODE			 (0xffffffL<<0)
1676
#define BCE_PCI_ID_VAL3_REVISION_ID			 (0xffL<<24)
1677

1678
#define BCE_PCI_ID_VAL4				0x00000440
1679
#define BCE_PCI_ID_VAL4_CAP_ENA			 (0xfL<<0)
1680
#define BCE_PCI_ID_VAL4_CAP_ENA_0			 (0L<<0)
1681
#define BCE_PCI_ID_VAL4_CAP_ENA_1			 (1L<<0)
1682
#define BCE_PCI_ID_VAL4_CAP_ENA_2			 (2L<<0)
1683
#define BCE_PCI_ID_VAL4_CAP_ENA_3			 (3L<<0)
1684
#define BCE_PCI_ID_VAL4_CAP_ENA_4			 (4L<<0)
1685
#define BCE_PCI_ID_VAL4_CAP_ENA_5			 (5L<<0)
1686
#define BCE_PCI_ID_VAL4_CAP_ENA_6			 (6L<<0)
1687
#define BCE_PCI_ID_VAL4_CAP_ENA_7			 (7L<<0)
1688
#define BCE_PCI_ID_VAL4_CAP_ENA_8			 (8L<<0)
1689
#define BCE_PCI_ID_VAL4_CAP_ENA_9			 (9L<<0)
1690
#define BCE_PCI_ID_VAL4_CAP_ENA_10			 (10L<<0)
1691
#define BCE_PCI_ID_VAL4_CAP_ENA_11			 (11L<<0)
1692
#define BCE_PCI_ID_VAL4_CAP_ENA_12			 (12L<<0)
1693
#define BCE_PCI_ID_VAL4_CAP_ENA_13			 (13L<<0)
1694
#define BCE_PCI_ID_VAL4_CAP_ENA_14			 (14L<<0)
1695
#define BCE_PCI_ID_VAL4_CAP_ENA_15			 (15L<<0)
1696
#define BCE_PCI_ID_VAL4_PM_SCALE_PRG			 (0x3L<<6)
1697
#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0			 (0L<<6)
1698
#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_1			 (1L<<6)
1699
#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_2			 (2L<<6)
1700
#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_3			 (3L<<6)
1701
#define BCE_PCI_ID_VAL4_MSI_LIMIT			 (0x7L<<9)
1702
#define BCE_PCI_ID_VAL4_MSI_ADVERTIZE			 (0x7L<<12)
1703
#define BCE_PCI_ID_VAL4_MSI_ENABLE			 (1L<<15)
1704
#define BCE_PCI_ID_VAL4_MAX_64_ADVERTIZE		 (1L<<16)
1705
#define BCE_PCI_ID_VAL4_MAX_133_ADVERTIZE		 (1L<<17)
1706
#define BCE_PCI_ID_VAL4_MAX_MEM_READ_SIZE		 (0x3L<<21)
1707
#define BCE_PCI_ID_VAL4_MAX_SPLIT_SIZE			 (0x7L<<23)
1708
#define BCE_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE		 (0x7L<<26)
1709

1710
#define BCE_PCI_ID_VAL5				0x00000444
1711
#define BCE_PCI_ID_VAL5_D1_SUPPORT			 (1L<<0)
1712
#define BCE_PCI_ID_VAL5_D2_SUPPORT			 (1L<<1)
1713
#define BCE_PCI_ID_VAL5_PME_IN_D0			 (1L<<2)
1714
#define BCE_PCI_ID_VAL5_PME_IN_D1			 (1L<<3)
1715
#define BCE_PCI_ID_VAL5_PME_IN_D2			 (1L<<4)
1716
#define BCE_PCI_ID_VAL5_PME_IN_D3_HOT			 (1L<<5)
1717

1718
#define BCE_PCI_PCIX_EXTENDED_STATUS			0x00000448
1719
#define BCE_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP		 (1L<<8)
1720
#define BCE_PCI_PCIX_EXTENDED_STATUS_LONG_BURST	 (1L<<9)
1721
#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS	 (0xfL<<16)
1722
#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX	 (0xffL<<24)
1723

1724
#define BCE_PCI_ID_VAL6				0x0000044c
1725
#define BCE_PCI_ID_VAL6_MAX_LAT			 (0xffL<<0)
1726
#define BCE_PCI_ID_VAL6_MIN_GNT			 (0xffL<<8)
1727
#define BCE_PCI_ID_VAL6_BIST				 (0xffL<<16)
1728

1729
#define BCE_PCI_MSI_DATA				0x00000450
1730
#define BCE_PCI_MSI_DATA_PCI_MSI_DATA			 (0xffffL<<0)
1731

1732
#define BCE_PCI_MSI_ADDR_H				0x00000454
1733
#define BCE_PCI_MSI_ADDR_L				0x00000458
1734

1735
/*
1736
 *  misc_reg definition
1737
 *  offset: 0x800
1738
 */
1739
#define BCE_MISC_COMMAND						0x00000800
1740
#define BCE_MISC_COMMAND_ENABLE_ALL				(1L<<0)
1741
#define BCE_MISC_COMMAND_DISABLE_ALL			(1L<<1)
1742
#define BCE_MISC_COMMAND_SW_RESET				(1L<<4)
1743
#define BCE_MISC_COMMAND_POR_RESET				(1L<<5)
1744
#define BCE_MISC_COMMAND_HD_RESET				(1L<<6)
1745
#define BCE_MISC_COMMAND_CMN_SW_RESET			(1L<<7)
1746
#define BCE_MISC_COMMAND_PAR_ERROR				(1L<<8)
1747
#define BCE_MISC_COMMAND_CS16_ERR				(1L<<9)
1748
#define BCE_MISC_COMMAND_CS16_ERR_LOC			(0xfL<<12)
1749
#define BCE_MISC_COMMAND_PAR_ERR_RAM			(0x7fL<<16)
1750
#define BCE_MISC_COMMAND_POWERDOWN_EVENT		(1L<<23)
1751
#define BCE_MISC_COMMAND_SW_SHUTDOWN			(1L<<24)
1752
#define BCE_MISC_COMMAND_SHUTDOWN_EN			(1L<<25)
1753
#define BCE_MISC_COMMAND_DINTEG_ATTN_EN			(1L<<26)
1754
#define BCE_MISC_COMMAND_PCIE_LINK_IN_L23		(1L<<27)
1755
#define BCE_MISC_COMMAND_PCIE_DIS				(1L<<28)
1756

1757
#define BCE_MISC_CFG							0x00000804
1758
#define BCE_MISC_CFG_GRC_TMOUT					(1L<<0)
1759
#define BCE_MISC_CFG_NVM_WR_EN					(0x3L<<1)
1760
#define BCE_MISC_CFG_NVM_WR_EN_PROTECT			(0L<<1)
1761
#define BCE_MISC_CFG_NVM_WR_EN_PCI				(1L<<1)
1762
#define BCE_MISC_CFG_NVM_WR_EN_ALLOW			(2L<<1)
1763
#define BCE_MISC_CFG_NVM_WR_EN_ALLOW2			(3L<<1)
1764
#define BCE_MISC_CFG_BIST_EN					(1L<<3)
1765
#define BCE_MISC_CFG_CK25_OUT_ALT_SRC			(1L<<4)
1766
#define BCE_MISC_CFG_RESERVED5_TE				(1L<<5)
1767
#define BCE_MISC_CFG_RESERVED6_TE				(1L<<6)
1768
#define BCE_MISC_CFG_CLK_CTL_OVERRIDE			(1L<<7)
1769
#define BCE_MISC_CFG_LEDMODE					(0x7L<<8)
1770
#define BCE_MISC_CFG_LEDMODE_MAC				(0L<<8)
1771
#define BCE_MISC_CFG_LEDMODE_PHY1_TE			(1L<<8)
1772
#define BCE_MISC_CFG_LEDMODE_PHY2_TE			(2L<<8)
1773
#define BCE_MISC_CFG_LEDMODE_PHY3_TE			(3L<<8)
1774
#define BCE_MISC_CFG_LEDMODE_PHY4_TE			(4L<<8)
1775
#define BCE_MISC_CFG_LEDMODE_PHY5_TE			(5L<<8)
1776
#define BCE_MISC_CFG_LEDMODE_PHY6_TE			(6L<<8)
1777
#define BCE_MISC_CFG_LEDMODE_PHY7_TE			(7L<<8)
1778
#define BCE_MISC_CFG_MCP_GRC_TMOUT_TE			(1L<<11)
1779
#define BCE_MISC_CFG_DBU_GRC_TMOUT_TE			(1L<<12)
1780
#define BCE_MISC_CFG_LEDMODE_XI					(0xfL<<8)
1781
#define BCE_MISC_CFG_LEDMODE_MAC_XI				(0L<<8)
1782
#define BCE_MISC_CFG_LEDMODE_PHY1_XI			(1L<<8)
1783
#define BCE_MISC_CFG_LEDMODE_PHY2_XI			(2L<<8)
1784
#define BCE_MISC_CFG_LEDMODE_PHY3_XI			(3L<<8)
1785
#define BCE_MISC_CFG_LEDMODE_MAC2_XI			(4L<<8)
1786
#define BCE_MISC_CFG_LEDMODE_PHY4_XI			(5L<<8)
1787
#define BCE_MISC_CFG_LEDMODE_PHY5_XI			(6L<<8)
1788
#define BCE_MISC_CFG_LEDMODE_PHY6_XI			(7L<<8)
1789
#define BCE_MISC_CFG_LEDMODE_MAC3_XI			(8L<<8)
1790
#define BCE_MISC_CFG_LEDMODE_PHY7_XI			(9L<<8)
1791
#define BCE_MISC_CFG_LEDMODE_PHY8_XI			(10L<<8)
1792
#define BCE_MISC_CFG_LEDMODE_PHY9_XI			(11L<<8)
1793
#define BCE_MISC_CFG_LEDMODE_MAC4_XI			(12L<<8)
1794
#define BCE_MISC_CFG_LEDMODE_PHY10_XI			(13L<<8)
1795
#define BCE_MISC_CFG_LEDMODE_PHY11_XI			(14L<<8)
1796
#define BCE_MISC_CFG_LEDMODE_UNUSED_XI			(15L<<8)
1797
#define BCE_MISC_CFG_PORT_SELECT_XI				(1L<<13)
1798
#define BCE_MISC_CFG_PARITY_MODE_XI				(1L<<14)
1799

1800
#define BCE_MISC_ID								0x00000808
1801
#define BCE_MISC_ID_BOND_ID						(0xfL<<0)
1802
#define BCE_MISC_ID_BOND_ID_X					(0L<<0)
1803
#define BCE_MISC_ID_BOND_ID_C					(3L<<0)
1804
#define BCE_MISC_ID_BOND_ID_S					(12L<<0)
1805
#define BCE_MISC_ID_CHIP_METAL					(0xffL<<4)
1806
#define BCE_MISC_ID_CHIP_REV					(0xfL<<12)
1807
#define BCE_MISC_ID_CHIP_NUM					(0xffffL<<16)
1808

1809
#define BCE_MISC_ENABLE_STATUS_BITS				0x0000080c
1810
#define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1811
#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE	 (1L<<1)
1812
#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)
1813
#define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)
1814
#define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE		 (1L<<4)
1815
#define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE	 (1L<<5)
1816
#define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)
1817
#define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)
1818
#define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)
1819
#define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE			 (1L<<9)
1820
#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1821
#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)
1822
#define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE		(1L<<12)
1823
#define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE	(1L<<13)
1824
#define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE	(1L<<14)
1825
#define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE		(1L<<15)
1826
#define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE	(1L<<16)
1827
#define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE		(1L<<17)
1828
#define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE	(1L<<18)
1829
#define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE	 (1L<<19)
1830
#define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)
1831
#define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE		(1L<<21)
1832
#define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)
1833
#define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)
1834
#define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)
1835
#define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE		(1L<<25)
1836
#define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE	(1L<<26)
1837
#define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE			(1L<<27)
1838
#define BCE_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE	 (1L<<28)
1839
#define BCE_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE	(0x7L<<29)
1840

1841
#define BCE_MISC_ENABLE_SET_BITS						0x00000810
1842
#define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE	(1L<<0)
1843
#define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE		(1L<<1)
1844
#define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE		(1L<<2)
1845
#define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE	(1L<<3)
1846
#define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE			(1L<<4)
1847
#define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE		(1L<<5)
1848
#define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE	(1L<<6)
1849
#define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE		(1L<<7)
1850
#define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE	(1L<<8)
1851
#define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE			(1L<<9)
1852
#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE	(1L<<10)
1853
#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE	(1L<<11)
1854
#define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE			(1L<<12)
1855
#define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE		(1L<<13)
1856
#define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE	(1L<<14)
1857
#define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE			(1L<<15)
1858
#define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE		(1L<<16)
1859
#define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE			(1L<<17)
1860
#define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE		(1L<<18)
1861
#define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE	(1L<<19)
1862
#define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE	(1L<<20)
1863
#define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE			(1L<<21)
1864
#define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE	(1L<<22)
1865
#define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE	(1L<<23)
1866
#define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE	(1L<<24)
1867
#define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE			(1L<<25)
1868
#define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE		(1L<<26)
1869
#define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE				(1L<<27)
1870
#define BCE_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE	(1L<<28)
1871
#define BCE_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE		(0x7L<<29)
1872

1873
#define BCE_MISC_ENABLE_DEFAULT							0x05ffffff
1874
#define BCE_MISC_ENABLE_DEFAULT_XI			  			0x17ffffff
1875

1876
#define BCE_MISC_ENABLE_CLR_BITS						0x00000814
1877
#define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE	(1L<<0)
1878
#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE		(1L<<1)
1879
#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE		(1L<<2)
1880
#define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE	(1L<<3)
1881
#define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE			(1L<<4)
1882
#define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE		(1L<<5)
1883
#define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE	(1L<<6)
1884
#define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE		(1L<<7)
1885
#define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE	(1L<<8)
1886
#define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE			(1L<<9)
1887
#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE	(1L<<10)
1888
#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE	(1L<<11)
1889
#define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE			(1L<<12)
1890
#define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE		(1L<<13)
1891
#define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE	(1L<<14)
1892
#define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE			(1L<<15)
1893
#define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE		(1L<<16)
1894
#define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE			(1L<<17)
1895
#define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE		(1L<<18)
1896
#define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE	(1L<<19)
1897
#define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE	(1L<<20)
1898
#define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE			(1L<<21)
1899
#define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE	(1L<<22)
1900
#define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE	(1L<<23)
1901
#define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE	(1L<<24)
1902
#define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE			(1L<<25)
1903
#define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE		(1L<<26)
1904
#define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE				(1L<<27)
1905
#define BCE_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE	(1L<<28)
1906
#define BCE_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE		(0x7L<<29)
1907

1908
#define BCE_MISC_ENABLE_CLR_DEFAULT						0x17ffffff
1909

1910
#define BCE_MISC_CLOCK_CONTROL_BITS			0x00000818
1911
#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET	 (0xfL<<0)
1912
#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ	 (0L<<0)
1913
#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ	 (1L<<0)
1914
#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ	 (2L<<0)
1915
#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ	 (3L<<0)
1916
#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ	 (4L<<0)
1917
#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ	 (5L<<0)
1918
#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ	 (6L<<0)
1919
#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ	 (7L<<0)
1920
#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW	 (0xfL<<0)
1921
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE	 (1L<<6)
1922
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT	 (1L<<7)
1923
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC	 (0x7L<<8)
1924
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF	 (0L<<8)
1925
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12	 (1L<<8)
1926
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6	 (2L<<8)
1927
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62	 (4L<<8)
1928
#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI	 (0x7L<<8)
1929
#define BCE_MISC_CLOCK_CONTROL_BITS_MIN_POWER		 (1L<<11)
1930
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED	 (0xfL<<12)
1931
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100	 (0L<<12)
1932
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80	 (1L<<12)
1933
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50	 (2L<<12)
1934
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40	 (4L<<12)
1935
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25	 (8L<<12)
1936
#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI	 (0xfL<<12)
1937
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP	 (1L<<16)
1938
#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE	 (1L<<17)
1939
#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE	 (1L<<18)
1940
#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE	 (1L<<19)
1941
#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_TE	 (0xfffL<<20)
1942
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI	 (1L<<17)
1943
#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI	 (0x3fL<<18)
1944
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI	 (0x7L<<24)
1945
#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI	 (1L<<27)
1946
#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI	 (0xfL<<28)
1947

1948
#define BCE_MISC_SPIO					0x0000081c
1949
#define BCE_MISC_SPIO_VALUE				 (0xffL<<0)
1950
#define BCE_MISC_SPIO_SET				 (0xffL<<8)
1951
#define BCE_MISC_SPIO_CLR				 (0xffL<<16)
1952
#define BCE_MISC_SPIO_FLOAT				 (0xffL<<24)
1953

1954
#define BCE_MISC_SPIO_INT				0x00000820
1955
#define BCE_MISC_SPIO_INT_INT_STATE_TE			 (0xfL<<0)
1956
#define BCE_MISC_SPIO_INT_OLD_VALUE_TE			 (0xfL<<8)
1957
#define BCE_MISC_SPIO_INT_OLD_SET_TE			 (0xfL<<16)
1958
#define BCE_MISC_SPIO_INT_OLD_CLR_TE			 (0xfL<<24)
1959
#define BCE_MISC_SPIO_INT_INT_STATE_XI			 (0xffL<<0)
1960
#define BCE_MISC_SPIO_INT_OLD_VALUE_XI			 (0xffL<<8)
1961
#define BCE_MISC_SPIO_INT_OLD_SET_XI			 (0xffL<<16)
1962
#define BCE_MISC_SPIO_INT_OLD_CLR_XI			 (0xffL<<24)
1963

1964
#define BCE_MISC_CONFIG_LFSR				0x00000824
1965
#define BCE_MISC_CONFIG_LFSR_DIV			 (0xffffL<<0)
1966

1967
#define BCE_MISC_LFSR_MASK_BITS			0x00000828
1968
#define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1969
#define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE	 (1L<<1)
1970
#define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)
1971
#define BCE_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)
1972
#define BCE_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE		 (1L<<4)
1973
#define BCE_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE	 (1L<<5)
1974
#define BCE_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)
1975
#define BCE_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)
1976
#define BCE_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)
1977
#define BCE_MISC_LFSR_MASK_BITS_EMAC_ENABLE		 (1L<<9)
1978
#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)
1979
#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)
1980
#define BCE_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE		 (1L<<12)
1981
#define BCE_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE	 (1L<<13)
1982
#define BCE_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)
1983
#define BCE_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE		 (1L<<15)
1984
#define BCE_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)
1985
#define BCE_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE		 (1L<<17)
1986
#define BCE_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE	 (1L<<18)
1987
#define BCE_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE	 (1L<<19)
1988
#define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)
1989
#define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE		 (1L<<21)
1990
#define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)
1991
#define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)
1992
#define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)
1993
#define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE		 (1L<<25)
1994
#define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE	 (1L<<26)
1995
#define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE		 (1L<<27)
1996
#define BCE_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE	 (1L<<28)
1997
#define BCE_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE	 (0x7L<<29)
1998

1999
#define BCE_MISC_ARB_REQ0				0x0000082c
2000
#define BCE_MISC_ARB_REQ1				0x00000830
2001
#define BCE_MISC_ARB_REQ2				0x00000834
2002
#define BCE_MISC_ARB_REQ3				0x00000838
2003
#define BCE_MISC_ARB_REQ4				0x0000083c
2004
#define BCE_MISC_ARB_FREE0				0x00000840
2005
#define BCE_MISC_ARB_FREE1				0x00000844
2006
#define BCE_MISC_ARB_FREE2				0x00000848
2007
#define BCE_MISC_ARB_FREE3				0x0000084c
2008
#define BCE_MISC_ARB_FREE4				0x00000850
2009
#define BCE_MISC_ARB_REQ_STATUS0			0x00000854
2010
#define BCE_MISC_ARB_REQ_STATUS1			0x00000858
2011
#define BCE_MISC_ARB_REQ_STATUS2			0x0000085c
2012
#define BCE_MISC_ARB_REQ_STATUS3			0x00000860
2013
#define BCE_MISC_ARB_REQ_STATUS4			0x00000864
2014
#define BCE_MISC_ARB_GNT0				0x00000868
2015
#define BCE_MISC_ARB_GNT0_0				 (0x7L<<0)
2016
#define BCE_MISC_ARB_GNT0_1				 (0x7L<<4)
2017
#define BCE_MISC_ARB_GNT0_2				 (0x7L<<8)
2018
#define BCE_MISC_ARB_GNT0_3				 (0x7L<<12)
2019
#define BCE_MISC_ARB_GNT0_4				 (0x7L<<16)
2020
#define BCE_MISC_ARB_GNT0_5				 (0x7L<<20)
2021
#define BCE_MISC_ARB_GNT0_6				 (0x7L<<24)
2022
#define BCE_MISC_ARB_GNT0_7				 (0x7L<<28)
2023

2024
#define BCE_MISC_ARB_GNT1				0x0000086c
2025
#define BCE_MISC_ARB_GNT1_8				 (0x7L<<0)
2026
#define BCE_MISC_ARB_GNT1_9				 (0x7L<<4)
2027
#define BCE_MISC_ARB_GNT1_10				 (0x7L<<8)
2028
#define BCE_MISC_ARB_GNT1_11				 (0x7L<<12)
2029
#define BCE_MISC_ARB_GNT1_12				 (0x7L<<16)
2030
#define BCE_MISC_ARB_GNT1_13				 (0x7L<<20)
2031
#define BCE_MISC_ARB_GNT1_14				 (0x7L<<24)
2032
#define BCE_MISC_ARB_GNT1_15				 (0x7L<<28)
2033

2034
#define BCE_MISC_ARB_GNT2				0x00000870
2035
#define BCE_MISC_ARB_GNT2_16				 (0x7L<<0)
2036
#define BCE_MISC_ARB_GNT2_17				 (0x7L<<4)
2037
#define BCE_MISC_ARB_GNT2_18				 (0x7L<<8)
2038
#define BCE_MISC_ARB_GNT2_19				 (0x7L<<12)
2039
#define BCE_MISC_ARB_GNT2_20				 (0x7L<<16)
2040
#define BCE_MISC_ARB_GNT2_21				 (0x7L<<20)
2041
#define BCE_MISC_ARB_GNT2_22				 (0x7L<<24)
2042
#define BCE_MISC_ARB_GNT2_23				 (0x7L<<28)
2043

2044
#define BCE_MISC_ARB_GNT3				0x00000874
2045
#define BCE_MISC_ARB_GNT3_24				 (0x7L<<0)
2046
#define BCE_MISC_ARB_GNT3_25				 (0x7L<<4)
2047
#define BCE_MISC_ARB_GNT3_26				 (0x7L<<8)
2048
#define BCE_MISC_ARB_GNT3_27				 (0x7L<<12)
2049
#define BCE_MISC_ARB_GNT3_28				 (0x7L<<16)
2050
#define BCE_MISC_ARB_GNT3_29				 (0x7L<<20)
2051
#define BCE_MISC_ARB_GNT3_30				 (0x7L<<24)
2052
#define BCE_MISC_ARB_GNT3_31				 (0x7L<<28)
2053

2054
#define BCE_MISC_RESERVED1				0x00000878
2055
#define BCE_MISC_RESERVED1_MISC_RESERVED1_VALUE	 (0x3fL<<0)
2056

2057
#define BCE_MISC_RESERVED2				0x0000087c
2058
#define BCE_MISC_RESERVED2_PCIE_DIS			 (1L<<0)
2059
#define BCE_MISC_RESERVED2_LINK_IN_L23			 (1L<<1)
2060

2061
#define BCE_MISC_SM_ASF_CONTROL			0x00000880
2062
#define BCE_MISC_SM_ASF_CONTROL_ASF_RST		 (1L<<0)
2063
#define BCE_MISC_SM_ASF_CONTROL_TSC_EN			 (1L<<1)
2064
#define BCE_MISC_SM_ASF_CONTROL_WG_TO			 (1L<<2)
2065
#define BCE_MISC_SM_ASF_CONTROL_HB_TO			 (1L<<3)
2066
#define BCE_MISC_SM_ASF_CONTROL_PA_TO			 (1L<<4)
2067
#define BCE_MISC_SM_ASF_CONTROL_PL_TO			 (1L<<5)
2068
#define BCE_MISC_SM_ASF_CONTROL_RT_TO			 (1L<<6)
2069
#define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT		 (1L<<7)
2070
#define BCE_MISC_SM_ASF_CONTROL_STRETCH_EN		 (1L<<8)
2071
#define BCE_MISC_SM_ASF_CONTROL_STRETCH_PULSE		 (1L<<9)
2072
#define BCE_MISC_SM_ASF_CONTROL_RES			 (0x3L<<10)
2073
#define BCE_MISC_SM_ASF_CONTROL_SMB_EN			 (1L<<12)
2074
#define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN		 (1L<<13)
2075
#define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT	 (1L<<14)
2076
#define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD		 (1L<<15)
2077
#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1		 (0x7fL<<16)
2078
#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2		 (0x7fL<<23)
2079
#define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0	 (1L<<30)
2080
#define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN		 (1L<<31)
2081

2082
#define BCE_MISC_SMB_IN				0x00000884
2083
#define BCE_MISC_SMB_IN_DAT_IN				 (0xffL<<0)
2084
#define BCE_MISC_SMB_IN_RDY				 (1L<<8)
2085
#define BCE_MISC_SMB_IN_DONE				 (1L<<9)
2086
#define BCE_MISC_SMB_IN_FIRSTBYTE			 (1L<<10)
2087
#define BCE_MISC_SMB_IN_STATUS				 (0x7L<<11)
2088
#define BCE_MISC_SMB_IN_STATUS_OK			 (0x0L<<11)
2089
#define BCE_MISC_SMB_IN_STATUS_PEC			 (0x1L<<11)
2090
#define BCE_MISC_SMB_IN_STATUS_OFLOW			 (0x2L<<11)
2091
#define BCE_MISC_SMB_IN_STATUS_STOP			 (0x3L<<11)
2092
#define BCE_MISC_SMB_IN_STATUS_TIMEOUT			 (0x4L<<11)
2093

2094
#define BCE_MISC_SMB_OUT				0x00000888
2095
#define BCE_MISC_SMB_OUT_DAT_OUT			 (0xffL<<0)
2096
#define BCE_MISC_SMB_OUT_RDY				 (1L<<8)
2097
#define BCE_MISC_SMB_OUT_START				 (1L<<9)
2098
#define BCE_MISC_SMB_OUT_LAST				 (1L<<10)
2099
#define BCE_MISC_SMB_OUT_ACC_TYPE			 (1L<<11)
2100
#define BCE_MISC_SMB_OUT_ENB_PEC			 (1L<<12)
2101
#define BCE_MISC_SMB_OUT_GET_RX_LEN			 (1L<<13)
2102
#define BCE_MISC_SMB_OUT_SMB_READ_LEN			 (0x3fL<<14)
2103
#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS		 (0xfL<<20)
2104
#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK		 (0L<<20)
2105
#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK	 (1L<<20)
2106
#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW		 (2L<<20)
2107
#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP		 (3L<<20)
2108
#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT	 (4L<<20)
2109
#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST	 (5L<<20)
2110
#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK		 (6L<<20)
2111
#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK	 (9L<<20)
2112
#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST	 (0xdL<<20)
2113
#define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE		 (1L<<24)
2114
#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN		 (1L<<25)
2115
#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN		 (1L<<26)
2116
#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN		 (1L<<27)
2117
#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN		 (1L<<28)
2118

2119
#define BCE_MISC_SMB_WATCHDOG				0x0000088c
2120
#define BCE_MISC_SMB_WATCHDOG_WATCHDOG			 (0xffffL<<0)
2121

2122
#define BCE_MISC_SMB_HEARTBEAT				0x00000890
2123
#define BCE_MISC_SMB_HEARTBEAT_HEARTBEAT		 (0xffffL<<0)
2124

2125
#define BCE_MISC_SMB_POLL_ASF				0x00000894
2126
#define BCE_MISC_SMB_POLL_ASF_POLL_ASF			 (0xffffL<<0)
2127

2128
#define BCE_MISC_SMB_POLL_LEGACY			0x00000898
2129
#define BCE_MISC_SMB_POLL_LEGACY_POLL_LEGACY		 (0xffffL<<0)
2130

2131
#define BCE_MISC_SMB_RETRAN				0x0000089c
2132
#define BCE_MISC_SMB_RETRAN_RETRAN			 (0xffL<<0)
2133

2134
#define BCE_MISC_SMB_TIMESTAMP				0x000008a0
2135
#define BCE_MISC_SMB_TIMESTAMP_TIMESTAMP		 (0xffffffffL<<0)
2136

2137
#define BCE_MISC_PERR_ENA0				0x000008a4
2138
#define BCE_MISC_PERR_ENA0_COM_MISC_CTXC		 (1L<<0)
2139
#define BCE_MISC_PERR_ENA0_COM_MISC_REGF		 (1L<<1)
2140
#define BCE_MISC_PERR_ENA0_COM_MISC_SCPAD		 (1L<<2)
2141
#define BCE_MISC_PERR_ENA0_CP_MISC_CTXC		 (1L<<3)
2142
#define BCE_MISC_PERR_ENA0_CP_MISC_REGF		 (1L<<4)
2143
#define BCE_MISC_PERR_ENA0_CP_MISC_SCPAD		 (1L<<5)
2144
#define BCE_MISC_PERR_ENA0_CS_MISC_TMEM		 (1L<<6)
2145
#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM0		 (1L<<7)
2146
#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM1		 (1L<<8)
2147
#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM2		 (1L<<9)
2148
#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM3		 (1L<<10)
2149
#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM4		 (1L<<11)
2150
#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM5		 (1L<<12)
2151
#define BCE_MISC_PERR_ENA0_CTX_MISC_PGTBL		 (1L<<13)
2152
#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR0		 (1L<<14)
2153
#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR1		 (1L<<15)
2154
#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR2		 (1L<<16)
2155
#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR3		 (1L<<17)
2156
#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR4		 (1L<<18)
2157
#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW0		 (1L<<19)
2158
#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW1		 (1L<<20)
2159
#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW2		 (1L<<21)
2160
#define BCE_MISC_PERR_ENA0_HC_MISC_DMA			 (1L<<22)
2161
#define BCE_MISC_PERR_ENA0_MCP_MISC_REGF		 (1L<<23)
2162
#define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD		 (1L<<24)
2163
#define BCE_MISC_PERR_ENA0_MQ_MISC_CTX			 (1L<<25)
2164
#define BCE_MISC_PERR_ENA0_RBDC_MISC			 (1L<<26)
2165
#define BCE_MISC_PERR_ENA0_RBUF_MISC_MB		 (1L<<27)
2166
#define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR		 (1L<<28)
2167
#define BCE_MISC_PERR_ENA0_RDE_MISC_RPC		 (1L<<29)
2168
#define BCE_MISC_PERR_ENA0_RDE_MISC_RPM		 (1L<<30)
2169
#define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS		 (1L<<31)
2170
#define BCE_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI		 (1L<<0)
2171
#define BCE_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI		 (1L<<1)
2172
#define BCE_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI	 (1L<<2)
2173
#define BCE_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI	 (1L<<3)
2174
#define BCE_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI	 (1L<<4)
2175
#define BCE_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI	 (1L<<5)
2176
#define BCE_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI	 (1L<<6)
2177
#define BCE_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI		 (1L<<7)
2178
#define BCE_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI	 (1L<<8)
2179
#define BCE_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI		 (1L<<9)
2180
#define BCE_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI		 (1L<<10)
2181
#define BCE_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI	 (1L<<11)
2182
#define BCE_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI		 (1L<<12)
2183
#define BCE_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI	 (1L<<13)
2184
#define BCE_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI	 (1L<<14)
2185
#define BCE_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI		 (1L<<15)
2186
#define BCE_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI	 (1L<<16)
2187
#define BCE_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI		 (1L<<17)
2188
#define BCE_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI		 (1L<<18)
2189
#define BCE_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI	 (1L<<19)
2190
#define BCE_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI	 (1L<<20)
2191
#define BCE_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI	 (1L<<21)
2192
#define BCE_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI	 (1L<<22)
2193
#define BCE_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI	 (1L<<23)
2194
#define BCE_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI	 (1L<<24)
2195
#define BCE_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI	 (1L<<25)
2196
#define BCE_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI	 (1L<<26)
2197
#define BCE_MISC_PERR_ENA0_TPBUF_PERR_EN_XI		 (1L<<27)
2198
#define BCE_MISC_PERR_ENA0_THBUF_PERR_EN_XI		 (1L<<28)
2199
#define BCE_MISC_PERR_ENA0_TDMA_PERR_EN_XI		 (1L<<29)
2200
#define BCE_MISC_PERR_ENA0_TBDC_PERR_EN_XI		 (1L<<30)
2201
#define BCE_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI		 (1L<<31)
2202

2203
#define BCE_MISC_PERR_ENA1				0x000008a8
2204
#define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS		 (1L<<0)
2205
#define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM		 (1L<<1)
2206
#define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM		 (1L<<2)
2207
#define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC		 (1L<<3)
2208
#define BCE_MISC_PERR_ENA1_RXP_MISC_REGF		 (1L<<4)
2209
#define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD		 (1L<<5)
2210
#define BCE_MISC_PERR_ENA1_RXP_MISC_RBUFC		 (1L<<6)
2211
#define BCE_MISC_PERR_ENA1_TBDC_MISC			 (1L<<7)
2212
#define BCE_MISC_PERR_ENA1_TDMA_MISC			 (1L<<8)
2213
#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB0		 (1L<<9)
2214
#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB1		 (1L<<10)
2215
#define BCE_MISC_PERR_ENA1_TPAT_MISC_REGF		 (1L<<11)
2216
#define BCE_MISC_PERR_ENA1_TPAT_MISC_SCPAD		 (1L<<12)
2217
#define BCE_MISC_PERR_ENA1_TPBUF_MISC_MB		 (1L<<13)
2218
#define BCE_MISC_PERR_ENA1_TSCH_MISC_LR		 (1L<<14)
2219
#define BCE_MISC_PERR_ENA1_TXP_MISC_CTXC		 (1L<<15)
2220
#define BCE_MISC_PERR_ENA1_TXP_MISC_REGF		 (1L<<16)
2221
#define BCE_MISC_PERR_ENA1_TXP_MISC_SCPAD		 (1L<<17)
2222
#define BCE_MISC_PERR_ENA1_UMP_MISC_FIORX		 (1L<<18)
2223
#define BCE_MISC_PERR_ENA1_UMP_MISC_FIOTX		 (1L<<19)
2224
#define BCE_MISC_PERR_ENA1_UMP_MISC_RX			 (1L<<20)
2225
#define BCE_MISC_PERR_ENA1_UMP_MISC_TX			 (1L<<21)
2226
#define BCE_MISC_PERR_ENA1_RDMAQ_MISC			 (1L<<22)
2227
#define BCE_MISC_PERR_ENA1_CSQ_MISC			 (1L<<23)
2228
#define BCE_MISC_PERR_ENA1_CPQ_MISC			 (1L<<24)
2229
#define BCE_MISC_PERR_ENA1_MCPQ_MISC			 (1L<<25)
2230
#define BCE_MISC_PERR_ENA1_RV2PMQ_MISC			 (1L<<26)
2231
#define BCE_MISC_PERR_ENA1_RV2PPQ_MISC			 (1L<<27)
2232
#define BCE_MISC_PERR_ENA1_RV2PTQ_MISC			 (1L<<28)
2233
#define BCE_MISC_PERR_ENA1_RXPQ_MISC			 (1L<<29)
2234
#define BCE_MISC_PERR_ENA1_RXPCQ_MISC			 (1L<<30)
2235
#define BCE_MISC_PERR_ENA1_RLUPQ_MISC			 (1L<<31)
2236
#define BCE_MISC_PERR_ENA1_RBDC_PERR_EN_XI		 (1L<<0)
2237
#define BCE_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI	 (1L<<2)
2238
#define BCE_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI		 (1L<<3)
2239
#define BCE_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI		 (1L<<4)
2240
#define BCE_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI	 (1L<<5)
2241
#define BCE_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI	 (1L<<6)
2242
#define BCE_MISC_PERR_ENA1_TPATQ_PERR_EN_XI		 (1L<<7)
2243
#define BCE_MISC_PERR_ENA1_MCPQ_PERR_EN_XI		 (1L<<8)
2244
#define BCE_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI		 (1L<<9)
2245
#define BCE_MISC_PERR_ENA1_TXPQ_PERR_EN_XI		 (1L<<10)
2246
#define BCE_MISC_PERR_ENA1_COMTQ_PERR_EN_XI		 (1L<<11)
2247
#define BCE_MISC_PERR_ENA1_COMQ_PERR_EN_XI		 (1L<<12)
2248
#define BCE_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI		 (1L<<13)
2249
#define BCE_MISC_PERR_ENA1_RXPQ_PERR_EN_XI		 (1L<<14)
2250
#define BCE_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI		 (1L<<15)
2251
#define BCE_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI		 (1L<<16)
2252
#define BCE_MISC_PERR_ENA1_TASQ_PERR_EN_XI		 (1L<<17)
2253
#define BCE_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI		 (1L<<18)
2254
#define BCE_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI		 (1L<<19)
2255
#define BCE_MISC_PERR_ENA1_COMXQ_PERR_EN_XI		 (1L<<20)
2256
#define BCE_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI		 (1L<<21)
2257
#define BCE_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI		 (1L<<22)
2258
#define BCE_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI		 (1L<<23)
2259
#define BCE_MISC_PERR_ENA1_CPQ_PERR_EN_XI		 (1L<<24)
2260
#define BCE_MISC_PERR_ENA1_CSQ_PERR_EN_XI		 (1L<<25)
2261
#define BCE_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI		 (1L<<26)
2262
#define BCE_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI	 (1L<<27)
2263
#define BCE_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI		 (1L<<28)
2264
#define BCE_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI		 (1L<<29)
2265

2266
#define BCE_MISC_PERR_ENA2				0x000008ac
2267
#define BCE_MISC_PERR_ENA2_COMQ_MISC			 (1L<<0)
2268
#define BCE_MISC_PERR_ENA2_COMXQ_MISC			 (1L<<1)
2269
#define BCE_MISC_PERR_ENA2_COMTQ_MISC			 (1L<<2)
2270
#define BCE_MISC_PERR_ENA2_TSCHQ_MISC			 (1L<<3)
2271
#define BCE_MISC_PERR_ENA2_TBDRQ_MISC			 (1L<<4)
2272
#define BCE_MISC_PERR_ENA2_TXPQ_MISC			 (1L<<5)
2273
#define BCE_MISC_PERR_ENA2_TDMAQ_MISC			 (1L<<6)
2274
#define BCE_MISC_PERR_ENA2_TPATQ_MISC			 (1L<<7)
2275
#define BCE_MISC_PERR_ENA2_TASQ_MISC			 (1L<<8)
2276
#define BCE_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI		 (1L<<0)
2277
#define BCE_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI		 (1L<<1)
2278
#define BCE_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI		 (1L<<2)
2279
#define BCE_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI		 (1L<<3)
2280
#define BCE_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI	 (1L<<4)
2281
#define BCE_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI		 (1L<<5)
2282
#define BCE_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI	 (1L<<6)
2283

2284
#define BCE_MISC_DEBUG_VECTOR_SEL			0x000008b0
2285
#define BCE_MISC_DEBUG_VECTOR_SEL_0			 (0xfffL<<0)
2286
#define BCE_MISC_DEBUG_VECTOR_SEL_1			 (0xfffL<<12)
2287
#define BCE_MISC_DEBUG_VECTOR_SEL_1_XI			 (0xfffL<<15)
2288

2289
#define BCE_MISC_VREG_CONTROL				0x000008b4
2290
#define BCE_MISC_VREG_CONTROL_1_2			 (0xfL<<0)
2291
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_XI		 (0xfL<<0)
2292
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI	 (0L<<0)
2293
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI	 (1L<<0)
2294
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI	 (2L<<0)
2295
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI	 (3L<<0)
2296
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI	 (4L<<0)
2297
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI	 (5L<<0)
2298
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI	 (6L<<0)
2299
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI		 (7L<<0)
2300
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI	 (8L<<0)
2301
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI	 (9L<<0)
2302
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI	 (10L<<0)
2303
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI	 (11L<<0)
2304
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI	 (12L<<0)
2305
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI	 (13L<<0)
2306
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI	 (14L<<0)
2307
#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI	 (15L<<0)
2308
#define BCE_MISC_VREG_CONTROL_2_5			 (0xfL<<4)
2309
#define BCE_MISC_VREG_CONTROL_2_5_PLUS14		 (0L<<4)
2310
#define BCE_MISC_VREG_CONTROL_2_5_PLUS12		 (1L<<4)
2311
#define BCE_MISC_VREG_CONTROL_2_5_PLUS10		 (2L<<4)
2312
#define BCE_MISC_VREG_CONTROL_2_5_PLUS8		 (3L<<4)
2313
#define BCE_MISC_VREG_CONTROL_2_5_PLUS6		 (4L<<4)
2314
#define BCE_MISC_VREG_CONTROL_2_5_PLUS4		 (5L<<4)
2315
#define BCE_MISC_VREG_CONTROL_2_5_PLUS2		 (6L<<4)
2316
#define BCE_MISC_VREG_CONTROL_2_5_NOM			 (7L<<4)
2317
#define BCE_MISC_VREG_CONTROL_2_5_MINUS2		 (8L<<4)
2318
#define BCE_MISC_VREG_CONTROL_2_5_MINUS4		 (9L<<4)
2319
#define BCE_MISC_VREG_CONTROL_2_5_MINUS6		 (10L<<4)
2320
#define BCE_MISC_VREG_CONTROL_2_5_MINUS8		 (11L<<4)
2321
#define BCE_MISC_VREG_CONTROL_2_5_MINUS10		 (12L<<4)
2322
#define BCE_MISC_VREG_CONTROL_2_5_MINUS12		 (13L<<4)
2323
#define BCE_MISC_VREG_CONTROL_2_5_MINUS14		 (14L<<4)
2324
#define BCE_MISC_VREG_CONTROL_2_5_MINUS16		 (15L<<4)
2325
#define BCE_MISC_VREG_CONTROL_1_0_MGMT			 (0xfL<<8)
2326
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS14		 (0L<<8)
2327
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS12		 (1L<<8)
2328
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS10		 (2L<<8)
2329
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS8		 (3L<<8)
2330
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS6		 (4L<<8)
2331
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS4		 (5L<<8)
2332
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS2		 (6L<<8)
2333
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_NOM		 (7L<<8)
2334
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS2		 (8L<<8)
2335
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS4		 (9L<<8)
2336
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS6		 (10L<<8)
2337
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS8		 (11L<<8)
2338
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS10		 (12L<<8)
2339
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS12		 (13L<<8)
2340
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS14		 (14L<<8)
2341
#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS16		 (15L<<8)
2342

2343
#define BCE_MISC_FINAL_CLK_CTL_VAL			0x000008b8
2344
#define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL	 (0x3ffffffL<<6)
2345

2346
#define BCE_MISC_GP_HW_CTL0				0x000008bc
2347
#define BCE_MISC_GP_HW_CTL0_TX_DRIVE			 (1L<<0)
2348
#define BCE_MISC_GP_HW_CTL0_RMII_MODE			 (1L<<1)
2349
#define BCE_MISC_GP_HW_CTL0_RMII_CRSDV_SEL		 (1L<<2)
2350
#define BCE_MISC_GP_HW_CTL0_RVMII_MODE			 (1L<<3)
2351
#define BCE_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE	 (1L<<4)
2352
#define BCE_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE	 (1L<<5)
2353
#define BCE_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE	 (1L<<6)
2354
#define BCE_MISC_GP_HW_CTL0_RESERVED1_XI		 (0x7L<<4)
2355
#define BCE_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY	 (1L<<7)
2356
#define BCE_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE	 (1L<<8)
2357
#define BCE_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE	 (1L<<9)
2358
#define BCE_MISC_GP_HW_CTL0_LED_ACT_SEL_TE		 (1L<<10)
2359
#define BCE_MISC_GP_HW_CTL0_RESERVED2_XI		 (0x7L<<8)
2360
#define BCE_MISC_GP_HW_CTL0_UP1_DEF0			 (1L<<11)
2361
#define BCE_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF		 (1L<<12)
2362
#define BCE_MISC_GP_HW_CTL0_FORCE2500_DEF		 (1L<<13)
2363
#define BCE_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF		 (1L<<14)
2364
#define BCE_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF	 (1L<<15)
2365
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI		 (0xfL<<16)
2366
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA		 (0L<<16)
2367
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA		 (1L<<16)
2368
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA		 (3L<<16)
2369
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA		 (5L<<16)
2370
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA		 (7L<<16)
2371
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN		 (15L<<16)
2372
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS		 (1L<<20)
2373
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS		 (1L<<21)
2374
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT		 (0x3L<<22)
2375
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P		 (0L<<22)
2376
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P		 (1L<<22)
2377
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P		 (2L<<22)
2378
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P		 (3L<<22)
2379
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT		 (0x3L<<24)
2380
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P		 (0L<<24)
2381
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P		 (1L<<24)
2382
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P		 (2L<<24)
2383
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P		 (3L<<24)
2384
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ		 (0x3L<<26)
2385
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA	 (0L<<26)
2386
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA	 (1L<<26)
2387
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA	 (2L<<26)
2388
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA	 (3L<<26)
2389
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ		 (0x3L<<28)
2390
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA	 (0L<<28)
2391
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA	 (1L<<28)
2392
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA	 (2L<<28)
2393
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA	 (3L<<28)
2394
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ		 (0x3L<<30)
2395
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57	 (0L<<30)
2396
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45	 (1L<<30)
2397
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62	 (2L<<30)
2398
#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66	 (3L<<30)
2399

2400
#define BCE_MISC_GP_HW_CTL1				0x000008c0
2401
#define BCE_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE	 (1L<<0)
2402
#define BCE_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE	 (1L<<1)
2403
#define BCE_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE		 (1L<<2)
2404
#define BCE_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE		 (1L<<3)
2405
#define BCE_MISC_GP_HW_CTL1_RESERVED_SOFT_XI		 (0xffffL<<0)
2406
#define BCE_MISC_GP_HW_CTL1_RESERVED_HARD_XI		 (0xffffL<<16)
2407

2408
#define BCE_MISC_NEW_HW_CTL				0x000008c4
2409
#define BCE_MISC_NEW_HW_CTL_MAIN_POR_BYPASS		 (1L<<0)
2410
#define BCE_MISC_NEW_HW_CTL_RINGOSC_ENABLE		 (1L<<1)
2411
#define BCE_MISC_NEW_HW_CTL_RINGOSC_SEL0		 (1L<<2)
2412
#define BCE_MISC_NEW_HW_CTL_RINGOSC_SEL1		 (1L<<3)
2413
#define BCE_MISC_NEW_HW_CTL_RESERVED_SHARED		 (0xfffL<<4)
2414
#define BCE_MISC_NEW_HW_CTL_RESERVED_SPLIT		 (0xffffL<<16)
2415

2416
#define BCE_MISC_NEW_CORE_CTL				0x000008c8
2417
#define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS	 (1L<<0)
2418
#define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ		 (1L<<1)
2419
#define BCE_MISC_NEW_CORE_CTL_DMA_ENABLE		 (1L<<16)
2420
#define BCE_MISC_NEW_CORE_CTL_RESERVED_CMN		 (0x3fffL<<2)
2421
#define BCE_MISC_NEW_CORE_CTL_RESERVED_TC		 (0xffffL<<16)
2422

2423
#define BCE_MISC_ECO_HW_CTL				0x000008cc
2424
#define BCE_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN		 (1L<<0)
2425
#define BCE_MISC_ECO_HW_CTL_RESERVED_SOFT		 (0x7fffL<<1)
2426
#define BCE_MISC_ECO_HW_CTL_RESERVED_HARD		 (0xffffL<<16)
2427

2428
#define BCE_MISC_ECO_CORE_CTL				0x000008d0
2429
#define BCE_MISC_ECO_CORE_CTL_RESERVED_SOFT		 (0xffffL<<0)
2430
#define BCE_MISC_ECO_CORE_CTL_RESERVED_HARD		 (0xffffL<<16)
2431

2432
#define BCE_MISC_PPIO					0x000008d4
2433
#define BCE_MISC_PPIO_VALUE				 (0xfL<<0)
2434
#define BCE_MISC_PPIO_SET				 (0xfL<<8)
2435
#define BCE_MISC_PPIO_CLR				 (0xfL<<16)
2436
#define BCE_MISC_PPIO_FLOAT				 (0xfL<<24)
2437

2438
#define BCE_MISC_PPIO_INT				0x000008d8
2439
#define BCE_MISC_PPIO_INT_INT_STATE			 (0xfL<<0)
2440
#define BCE_MISC_PPIO_INT_OLD_VALUE			 (0xfL<<8)
2441
#define BCE_MISC_PPIO_INT_OLD_SET			 (0xfL<<16)
2442
#define BCE_MISC_PPIO_INT_OLD_CLR			 (0xfL<<24)
2443

2444
#define BCE_MISC_RESET_NUMS				0x000008dc
2445
#define BCE_MISC_RESET_NUMS_NUM_HARD_RESETS		 (0x7L<<0)
2446
#define BCE_MISC_RESET_NUMS_NUM_PCIE_RESETS		 (0x7L<<4)
2447
#define BCE_MISC_RESET_NUMS_NUM_PERSTB_RESETS		 (0x7L<<8)
2448
#define BCE_MISC_RESET_NUMS_NUM_CMN_RESETS		 (0x7L<<12)
2449
#define BCE_MISC_RESET_NUMS_NUM_PORT_RESETS		 (0x7L<<16)
2450

2451
#define BCE_MISC_CS16_ERR				0x000008e0
2452
#define BCE_MISC_CS16_ERR_ENA_PCI			 (1L<<0)
2453
#define BCE_MISC_CS16_ERR_ENA_RDMA			 (1L<<1)
2454
#define BCE_MISC_CS16_ERR_ENA_TDMA			 (1L<<2)
2455
#define BCE_MISC_CS16_ERR_ENA_EMAC			 (1L<<3)
2456
#define BCE_MISC_CS16_ERR_ENA_CTX			 (1L<<4)
2457
#define BCE_MISC_CS16_ERR_ENA_TBDR			 (1L<<5)
2458
#define BCE_MISC_CS16_ERR_ENA_RBDC			 (1L<<6)
2459
#define BCE_MISC_CS16_ERR_ENA_COM			 (1L<<7)
2460
#define BCE_MISC_CS16_ERR_ENA_CP			 (1L<<8)
2461
#define BCE_MISC_CS16_ERR_STA_PCI			 (1L<<16)
2462
#define BCE_MISC_CS16_ERR_STA_RDMA			 (1L<<17)
2463
#define BCE_MISC_CS16_ERR_STA_TDMA			 (1L<<18)
2464
#define BCE_MISC_CS16_ERR_STA_EMAC			 (1L<<19)
2465
#define BCE_MISC_CS16_ERR_STA_CTX			 (1L<<20)
2466
#define BCE_MISC_CS16_ERR_STA_TBDR			 (1L<<21)
2467
#define BCE_MISC_CS16_ERR_STA_RBDC			 (1L<<22)
2468
#define BCE_MISC_CS16_ERR_STA_COM			 (1L<<23)
2469
#define BCE_MISC_CS16_ERR_STA_CP			 (1L<<24)
2470

2471
#define BCE_MISC_SPIO_EVENT				0x000008e4
2472
#define BCE_MISC_SPIO_EVENT_ENABLE			 (0xffL<<0)
2473

2474
#define BCE_MISC_PPIO_EVENT				0x000008e8
2475
#define BCE_MISC_PPIO_EVENT_ENABLE			 (0xfL<<0)
2476

2477
#define BCE_MISC_DUAL_MEDIA_CTRL			0x000008ec
2478
#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID		 (0xffL<<0)
2479
#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_X		 (0L<<0)
2480
#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C		 (3L<<0)
2481
#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S		 (12L<<0)
2482
#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP	 (0x7L<<8)
2483
#define BCE_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN		 (1L<<11)
2484
#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET	 (1L<<12)
2485
#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET	 (1L<<13)
2486
#define BCE_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET		 (1L<<14)
2487
#define BCE_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET		 (1L<<15)
2488
#define BCE_MISC_DUAL_MEDIA_CTRL_LCPLL_RST		 (1L<<16)
2489
#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES1_RST		 (1L<<17)
2490
#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES0_RST		 (1L<<18)
2491
#define BCE_MISC_DUAL_MEDIA_CTRL_PHY1_RST		 (1L<<19)
2492
#define BCE_MISC_DUAL_MEDIA_CTRL_PHY0_RST		 (1L<<20)
2493
#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL		 (0x7L<<21)
2494
#define BCE_MISC_DUAL_MEDIA_CTRL_PORT_SWAP		 (1L<<24)
2495
#define BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE	 (1L<<25)
2496
#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ	 (0xfL<<26)
2497
#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ	 (1L<<26)
2498
#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ	 (2L<<26)
2499
#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ	 (4L<<26)
2500
#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ	 (8L<<26)
2501

2502
#define BCE_MISC_OTP_CMD1				0x000008f0
2503
#define BCE_MISC_OTP_CMD1_FMODE			 (0x7L<<0)
2504
#define BCE_MISC_OTP_CMD1_FMODE_IDLE			 (0L<<0)
2505
#define BCE_MISC_OTP_CMD1_FMODE_WRITE			 (1L<<0)
2506
#define BCE_MISC_OTP_CMD1_FMODE_INIT			 (2L<<0)
2507
#define BCE_MISC_OTP_CMD1_FMODE_SET			 (3L<<0)
2508
#define BCE_MISC_OTP_CMD1_FMODE_RST			 (4L<<0)
2509
#define BCE_MISC_OTP_CMD1_FMODE_VERIFY			 (5L<<0)
2510
#define BCE_MISC_OTP_CMD1_FMODE_RESERVED0		 (6L<<0)
2511
#define BCE_MISC_OTP_CMD1_FMODE_RESERVED1		 (7L<<0)
2512
#define BCE_MISC_OTP_CMD1_USEPINS			 (1L<<8)
2513
#define BCE_MISC_OTP_CMD1_PROGSEL			 (1L<<9)
2514
#define BCE_MISC_OTP_CMD1_PROGSTART			 (1L<<10)
2515
#define BCE_MISC_OTP_CMD1_PCOUNT			 (0x7L<<16)
2516
#define BCE_MISC_OTP_CMD1_PBYP				 (1L<<19)
2517
#define BCE_MISC_OTP_CMD1_VSEL				 (0xfL<<20)
2518
#define BCE_MISC_OTP_CMD1_TM				 (0x7L<<27)
2519
#define BCE_MISC_OTP_CMD1_SADBYP			 (1L<<30)
2520
#define BCE_MISC_OTP_CMD1_DEBUG			 (1L<<31)
2521

2522
#define BCE_MISC_OTP_CMD2				0x000008f4
2523
#define BCE_MISC_OTP_CMD2_OTP_ROM_ADDR			 (0x3ffL<<0)
2524
#define BCE_MISC_OTP_CMD2_DOSEL			 (0x7fL<<16)
2525
#define BCE_MISC_OTP_CMD2_DOSEL_0			 (0L<<16)
2526
#define BCE_MISC_OTP_CMD2_DOSEL_1			 (1L<<16)
2527
#define BCE_MISC_OTP_CMD2_DOSEL_127			 (127L<<16)
2528

2529
#define BCE_MISC_OTP_STATUS				0x000008f8
2530
#define BCE_MISC_OTP_STATUS_DATA			 (0xffL<<0)
2531
#define BCE_MISC_OTP_STATUS_VALID			 (1L<<8)
2532
#define BCE_MISC_OTP_STATUS_BUSY			 (1L<<9)
2533
#define BCE_MISC_OTP_STATUS_BUSYSM			 (1L<<10)
2534
#define BCE_MISC_OTP_STATUS_DONE			 (1L<<11)
2535

2536
#define BCE_MISC_OTP_SHIFT1_CMD			0x000008fc
2537
#define BCE_MISC_OTP_SHIFT1_CMD_RESET_MODE_N		 (1L<<0)
2538
#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_DONE		 (1L<<1)
2539
#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_START		 (1L<<2)
2540
#define BCE_MISC_OTP_SHIFT1_CMD_LOAD_DATA		 (1L<<3)
2541
#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT		 (0x1fL<<8)
2542

2543
#define BCE_MISC_OTP_SHIFT1_DATA			0x00000900
2544
#define BCE_MISC_OTP_SHIFT2_CMD			0x00000904
2545
#define BCE_MISC_OTP_SHIFT2_CMD_RESET_MODE_N		 (1L<<0)
2546
#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_DONE		 (1L<<1)
2547
#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_START		 (1L<<2)
2548
#define BCE_MISC_OTP_SHIFT2_CMD_LOAD_DATA		 (1L<<3)
2549
#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT		 (0x1fL<<8)
2550

2551
#define BCE_MISC_OTP_SHIFT2_DATA			0x00000908
2552
#define BCE_MISC_BIST_CS0				0x0000090c
2553
#define BCE_MISC_BIST_CS0_MBIST_EN			 (1L<<0)
2554
#define BCE_MISC_BIST_CS0_BIST_SETUP			 (0x3L<<1)
2555
#define BCE_MISC_BIST_CS0_MBIST_ASYNC_RESET		 (1L<<3)
2556
#define BCE_MISC_BIST_CS0_MBIST_DONE			 (1L<<8)
2557
#define BCE_MISC_BIST_CS0_MBIST_GO			 (1L<<9)
2558
#define BCE_MISC_BIST_CS0_BIST_OVERRIDE		 (1L<<31)
2559

2560
#define BCE_MISC_BIST_MEMSTATUS0			0x00000910
2561
#define BCE_MISC_BIST_CS1				0x00000914
2562
#define BCE_MISC_BIST_CS1_MBIST_EN			 (1L<<0)
2563
#define BCE_MISC_BIST_CS1_BIST_SETUP			 (0x3L<<1)
2564
#define BCE_MISC_BIST_CS1_MBIST_ASYNC_RESET		 (1L<<3)
2565
#define BCE_MISC_BIST_CS1_MBIST_DONE			 (1L<<8)
2566
#define BCE_MISC_BIST_CS1_MBIST_GO			 (1L<<9)
2567

2568
#define BCE_MISC_BIST_MEMSTATUS1			0x00000918
2569
#define BCE_MISC_BIST_CS2				0x0000091c
2570
#define BCE_MISC_BIST_CS2_MBIST_EN			 (1L<<0)
2571
#define BCE_MISC_BIST_CS2_BIST_SETUP			 (0x3L<<1)
2572
#define BCE_MISC_BIST_CS2_MBIST_ASYNC_RESET		 (1L<<3)
2573
#define BCE_MISC_BIST_CS2_MBIST_DONE			 (1L<<8)
2574
#define BCE_MISC_BIST_CS2_MBIST_GO			 (1L<<9)
2575

2576
#define BCE_MISC_BIST_MEMSTATUS2			0x00000920
2577
#define BCE_MISC_BIST_CS3				0x00000924
2578
#define BCE_MISC_BIST_CS3_MBIST_EN			 (1L<<0)
2579
#define BCE_MISC_BIST_CS3_BIST_SETUP			 (0x3L<<1)
2580
#define BCE_MISC_BIST_CS3_MBIST_ASYNC_RESET		 (1L<<3)
2581
#define BCE_MISC_BIST_CS3_MBIST_DONE			 (1L<<8)
2582
#define BCE_MISC_BIST_CS3_MBIST_GO			 (1L<<9)
2583

2584
#define BCE_MISC_BIST_MEMSTATUS3			0x00000928
2585
#define BCE_MISC_BIST_CS4				0x0000092c
2586
#define BCE_MISC_BIST_CS4_MBIST_EN			 (1L<<0)
2587
#define BCE_MISC_BIST_CS4_BIST_SETUP			 (0x3L<<1)
2588
#define BCE_MISC_BIST_CS4_MBIST_ASYNC_RESET		 (1L<<3)
2589
#define BCE_MISC_BIST_CS4_MBIST_DONE			 (1L<<8)
2590
#define BCE_MISC_BIST_CS4_MBIST_GO			 (1L<<9)
2591

2592
#define BCE_MISC_BIST_MEMSTATUS4			0x00000930
2593
#define BCE_MISC_BIST_CS5				0x00000934
2594
#define BCE_MISC_BIST_CS5_MBIST_EN			 (1L<<0)
2595
#define BCE_MISC_BIST_CS5_BIST_SETUP			 (0x3L<<1)
2596
#define BCE_MISC_BIST_CS5_MBIST_ASYNC_RESET		 (1L<<3)
2597
#define BCE_MISC_BIST_CS5_MBIST_DONE			 (1L<<8)
2598
#define BCE_MISC_BIST_CS5_MBIST_GO			 (1L<<9)
2599

2600
#define BCE_MISC_BIST_MEMSTATUS5			0x00000938
2601
#define BCE_MISC_MEM_TM0				0x0000093c
2602
#define BCE_MISC_MEM_TM0_PCIE_REPLAY_TM		 (0xfL<<0)
2603
#define BCE_MISC_MEM_TM0_MCP_SCPAD			 (0xfL<<8)
2604
#define BCE_MISC_MEM_TM0_UMP_TM			 (0xffL<<16)
2605
#define BCE_MISC_MEM_TM0_HB_MEM_TM			 (0xfL<<24)
2606

2607
#define BCE_MISC_USPLL_CTRL				0x00000940
2608
#define BCE_MISC_USPLL_CTRL_PH_DET_DIS			 (1L<<0)
2609
#define BCE_MISC_USPLL_CTRL_FREQ_DET_DIS		 (1L<<1)
2610
#define BCE_MISC_USPLL_CTRL_LCPX			 (0x3fL<<2)
2611
#define BCE_MISC_USPLL_CTRL_RX				 (0x3L<<8)
2612
#define BCE_MISC_USPLL_CTRL_VC_EN			 (1L<<10)
2613
#define BCE_MISC_USPLL_CTRL_VCO_MG			 (0x3L<<11)
2614
#define BCE_MISC_USPLL_CTRL_KVCO_XF			 (0x7L<<13)
2615
#define BCE_MISC_USPLL_CTRL_KVCO_XS			 (0x7L<<16)
2616
#define BCE_MISC_USPLL_CTRL_TESTD_EN			 (1L<<19)
2617
#define BCE_MISC_USPLL_CTRL_TESTD_SEL			 (0x7L<<20)
2618
#define BCE_MISC_USPLL_CTRL_TESTA_EN			 (1L<<23)
2619
#define BCE_MISC_USPLL_CTRL_TESTA_SEL			 (0x3L<<24)
2620
#define BCE_MISC_USPLL_CTRL_ATTEN_FREF			 (1L<<26)
2621
#define BCE_MISC_USPLL_CTRL_DIGITAL_RST		 (1L<<27)
2622
#define BCE_MISC_USPLL_CTRL_ANALOG_RST			 (1L<<28)
2623
#define BCE_MISC_USPLL_CTRL_LOCK			 (1L<<29)
2624

2625
#define BCE_MISC_PERR_STATUS0				0x00000944
2626
#define BCE_MISC_PERR_STATUS0_COM_DMAE_PERR		 (1L<<0)
2627
#define BCE_MISC_PERR_STATUS0_CP_DMAE_PERR		 (1L<<1)
2628
#define BCE_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR	 (1L<<2)
2629
#define BCE_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR	 (1L<<3)
2630
#define BCE_MISC_PERR_STATUS0_CTX_PGTBL_PERR		 (1L<<4)
2631
#define BCE_MISC_PERR_STATUS0_CTX_CACHE_PERR		 (1L<<5)
2632
#define BCE_MISC_PERR_STATUS0_CTX_MIRROR_PERR		 (1L<<6)
2633
#define BCE_MISC_PERR_STATUS0_COM_CTXC_PERR		 (1L<<7)
2634
#define BCE_MISC_PERR_STATUS0_COM_SCPAD_PERR		 (1L<<8)
2635
#define BCE_MISC_PERR_STATUS0_CP_CTXC_PERR		 (1L<<9)
2636
#define BCE_MISC_PERR_STATUS0_CP_SCPAD_PERR		 (1L<<10)
2637
#define BCE_MISC_PERR_STATUS0_RXP_RBUFC_PERR		 (1L<<11)
2638
#define BCE_MISC_PERR_STATUS0_RXP_CTXC_PERR		 (1L<<12)
2639
#define BCE_MISC_PERR_STATUS0_RXP_SCPAD_PERR		 (1L<<13)
2640
#define BCE_MISC_PERR_STATUS0_TPAT_SCPAD_PERR		 (1L<<14)
2641
#define BCE_MISC_PERR_STATUS0_TXP_CTXC_PERR		 (1L<<15)
2642
#define BCE_MISC_PERR_STATUS0_TXP_SCPAD_PERR		 (1L<<16)
2643
#define BCE_MISC_PERR_STATUS0_CS_TMEM_PERR		 (1L<<17)
2644
#define BCE_MISC_PERR_STATUS0_MQ_CTX_PERR		 (1L<<18)
2645
#define BCE_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR	 (1L<<19)
2646
#define BCE_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR	 (1L<<20)
2647
#define BCE_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR		 (1L<<21)
2648
#define BCE_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR	 (1L<<22)
2649
#define BCE_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR		 (1L<<23)
2650
#define BCE_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR		 (1L<<24)
2651
#define BCE_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR	 (1L<<25)
2652
#define BCE_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR	 (1L<<26)
2653
#define BCE_MISC_PERR_STATUS0_TPBUF_PERR		 (1L<<27)
2654
#define BCE_MISC_PERR_STATUS0_THBUF_PERR		 (1L<<28)
2655
#define BCE_MISC_PERR_STATUS0_TDMA_PERR		 (1L<<29)
2656
#define BCE_MISC_PERR_STATUS0_TBDC_PERR		 (1L<<30)
2657
#define BCE_MISC_PERR_STATUS0_TSCH_LR_PERR		 (1L<<31)
2658

2659
#define BCE_MISC_PERR_STATUS1				0x00000948
2660
#define BCE_MISC_PERR_STATUS1_RBDC_PERR		 (1L<<0)
2661
#define BCE_MISC_PERR_STATUS1_RDMA_DFIFO_PERR		 (1L<<2)
2662
#define BCE_MISC_PERR_STATUS1_HC_STATS_PERR		 (1L<<3)
2663
#define BCE_MISC_PERR_STATUS1_HC_MSIX_PERR		 (1L<<4)
2664
#define BCE_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR	 (1L<<5)
2665
#define BCE_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR	 (1L<<6)
2666
#define BCE_MISC_PERR_STATUS1_TPATQ_PERR		 (1L<<7)
2667
#define BCE_MISC_PERR_STATUS1_MCPQ_PERR		 (1L<<8)
2668
#define BCE_MISC_PERR_STATUS1_TDMAQ_PERR		 (1L<<9)
2669
#define BCE_MISC_PERR_STATUS1_TXPQ_PERR		 (1L<<10)
2670
#define BCE_MISC_PERR_STATUS1_COMTQ_PERR		 (1L<<11)
2671
#define BCE_MISC_PERR_STATUS1_COMQ_PERR		 (1L<<12)
2672
#define BCE_MISC_PERR_STATUS1_RLUPQ_PERR		 (1L<<13)
2673
#define BCE_MISC_PERR_STATUS1_RXPQ_PERR		 (1L<<14)
2674
#define BCE_MISC_PERR_STATUS1_RV2PPQ_PERR		 (1L<<15)
2675
#define BCE_MISC_PERR_STATUS1_RDMAQ_PERR		 (1L<<16)
2676
#define BCE_MISC_PERR_STATUS1_TASQ_PERR		 (1L<<17)
2677
#define BCE_MISC_PERR_STATUS1_TBDRQ_PERR		 (1L<<18)
2678
#define BCE_MISC_PERR_STATUS1_TSCHQ_PERR		 (1L<<19)
2679
#define BCE_MISC_PERR_STATUS1_COMXQ_PERR		 (1L<<20)
2680
#define BCE_MISC_PERR_STATUS1_RXPCQ_PERR		 (1L<<21)
2681
#define BCE_MISC_PERR_STATUS1_RV2PTQ_PERR		 (1L<<22)
2682
#define BCE_MISC_PERR_STATUS1_RV2PMQ_PERR		 (1L<<23)
2683
#define BCE_MISC_PERR_STATUS1_CPQ_PERR			 (1L<<24)
2684
#define BCE_MISC_PERR_STATUS1_CSQ_PERR			 (1L<<25)
2685
#define BCE_MISC_PERR_STATUS1_RLUP_CID_PERR		 (1L<<26)
2686
#define BCE_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR		 (1L<<27)
2687
#define BCE_MISC_PERR_STATUS1_RV2PCSQ_PERR		 (1L<<28)
2688
#define BCE_MISC_PERR_STATUS1_MQ_IDX_PERR		 (1L<<29)
2689

2690
#define BCE_MISC_PERR_STATUS2				0x0000094c
2691
#define BCE_MISC_PERR_STATUS2_TGT_FIFO_PERR		 (1L<<0)
2692
#define BCE_MISC_PERR_STATUS2_UMP_TX_PERR		 (1L<<1)
2693
#define BCE_MISC_PERR_STATUS2_UMP_RX_PERR		 (1L<<2)
2694
#define BCE_MISC_PERR_STATUS2_MCP_ROM_PERR		 (1L<<3)
2695
#define BCE_MISC_PERR_STATUS2_MCP_SCPAD_PERR		 (1L<<4)
2696
#define BCE_MISC_PERR_STATUS2_HB_MEM_PERR		 (1L<<5)
2697
#define BCE_MISC_PERR_STATUS2_PCIE_REPLAY_PERR		 (1L<<6)
2698

2699
#define BCE_MISC_LCPLL_CTRL0				0x00000950
2700
#define BCE_MISC_LCPLL_CTRL0_OAC			 (0x7L<<0)
2701
#define BCE_MISC_LCPLL_CTRL0_OAC_NEGTWENTY		 (0L<<0)
2702
#define BCE_MISC_LCPLL_CTRL0_OAC_ZERO			 (1L<<0)
2703
#define BCE_MISC_LCPLL_CTRL0_OAC_TWENTY		 (3L<<0)
2704
#define BCE_MISC_LCPLL_CTRL0_OAC_FORTY			 (7L<<0)
2705
#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL			 (0x7L<<3)
2706
#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_360		 (0L<<3)
2707
#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_480		 (1L<<3)
2708
#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_600		 (3L<<3)
2709
#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_720		 (7L<<3)
2710
#define BCE_MISC_LCPLL_CTRL0_BIAS_CTRL			 (0x3L<<6)
2711
#define BCE_MISC_LCPLL_CTRL0_PLL_OBSERVE		 (0x7L<<8)
2712
#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL			 (0x3L<<11)
2713
#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_0		 (0L<<11)
2714
#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_1		 (1L<<11)
2715
#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_2		 (2L<<11)
2716
#define BCE_MISC_LCPLL_CTRL0_PLLSEQSTART		 (1L<<13)
2717
#define BCE_MISC_LCPLL_CTRL0_RESERVED			 (1L<<14)
2718
#define BCE_MISC_LCPLL_CTRL0_CAPRETRY_EN		 (1L<<15)
2719
#define BCE_MISC_LCPLL_CTRL0_FREQMONITOR_EN		 (1L<<16)
2720
#define BCE_MISC_LCPLL_CTRL0_FREQDETRESTART_EN		 (1L<<17)
2721
#define BCE_MISC_LCPLL_CTRL0_FREQDETRETRY_EN		 (1L<<18)
2722
#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN		 (1L<<19)
2723
#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFDONE		 (1L<<20)
2724
#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFPASS		 (1L<<21)
2725
#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN	 (1L<<22)
2726
#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPDONE		 (1L<<23)
2727
#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN	 (1L<<24)
2728
#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPPASS		 (1L<<25)
2729
#define BCE_MISC_LCPLL_CTRL0_CAPRESTART		 (1L<<26)
2730
#define BCE_MISC_LCPLL_CTRL0_CAPSELECTM_EN		 (1L<<27)
2731

2732
#define BCE_MISC_LCPLL_CTRL1				0x00000954
2733
#define BCE_MISC_LCPLL_CTRL1_CAPSELECTM		 (0x1fL<<0)
2734
#define BCE_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN	 (1L<<5)
2735
#define BCE_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN		 (1L<<6)
2736
#define BCE_MISC_LCPLL_CTRL1_SLOWDN_XOR		 (1L<<7)
2737

2738
#define BCE_MISC_LCPLL_STATUS				0x00000958
2739
#define BCE_MISC_LCPLL_STATUS_FREQDONE_SM		 (1L<<0)
2740
#define BCE_MISC_LCPLL_STATUS_FREQPASS_SM		 (1L<<1)
2741
#define BCE_MISC_LCPLL_STATUS_PLLSEQDONE		 (1L<<2)
2742
#define BCE_MISC_LCPLL_STATUS_PLLSEQPASS		 (1L<<3)
2743
#define BCE_MISC_LCPLL_STATUS_PLLSTATE			 (0x7L<<4)
2744
#define BCE_MISC_LCPLL_STATUS_CAPSTATE			 (0x7L<<7)
2745
#define BCE_MISC_LCPLL_STATUS_CAPSELECT		 (0x1fL<<10)
2746
#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR		 (1L<<15)
2747
#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0	 (0L<<15)
2748
#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1	 (1L<<15)
2749

2750
#define BCE_MISC_OSCFUNDS_CTRL				0x0000095c
2751
#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON		 (1L<<5)
2752
#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF		 (0L<<5)
2753
#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_ON		 (1L<<5)
2754
#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM		 (0x3L<<6)
2755
#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0		 (0L<<6)
2756
#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1		 (1L<<6)
2757
#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2		 (2L<<6)
2758
#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3		 (3L<<6)
2759
#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ		 (0x3L<<8)
2760
#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0		 (0L<<8)
2761
#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1		 (1L<<8)
2762
#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2		 (2L<<8)
2763
#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3		 (3L<<8)
2764
#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ		 (0x3L<<10)
2765
#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0		 (0L<<10)
2766
#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1		 (1L<<10)
2767
#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2		 (2L<<10)
2768
#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3		 (3L<<10)
2769

2770
/*
2771
 *  dma_reg definition
2772
 *  offset: 0xc00
2773
 */
2774
#define BCE_DMA_COMMAND				0x00000c00
2775
#define BCE_DMA_COMMAND_ENABLE				 (1L<<0)
2776

2777
#define BCE_DMA_STATUS					0x00000c04
2778
#define BCE_DMA_STATUS_PAR_ERROR_STATE			 (1L<<0)
2779
#define BCE_DMA_STATUS_READ_TRANSFERS_STAT		 (1L<<16)
2780
#define BCE_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT	 (1L<<17)
2781
#define BCE_DMA_STATUS_BIG_READ_TRANSFERS_STAT		 (1L<<18)
2782
#define BCE_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT	 (1L<<19)
2783
#define BCE_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT	 (1L<<20)
2784
#define BCE_DMA_STATUS_WRITE_TRANSFERS_STAT		 (1L<<21)
2785
#define BCE_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT	 (1L<<22)
2786
#define BCE_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT	 (1L<<23)
2787
#define BCE_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT	 (1L<<24)
2788
#define BCE_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT	 (1L<<25)
2789

2790
#define BCE_DMA_CONFIG					0x00000c08
2791
#define BCE_DMA_CONFIG_DATA_BYTE_SWAP			 (1L<<0)
2792
#define BCE_DMA_CONFIG_DATA_WORD_SWAP			 (1L<<1)
2793
#define BCE_DMA_CONFIG_CNTL_BYTE_SWAP			 (1L<<4)
2794
#define BCE_DMA_CONFIG_CNTL_WORD_SWAP			 (1L<<5)
2795
#define BCE_DMA_CONFIG_ONE_DMA				 (1L<<6)
2796
#define BCE_DMA_CONFIG_CNTL_TWO_DMA			 (1L<<7)
2797
#define BCE_DMA_CONFIG_CNTL_FPGA_MODE			 (1L<<8)
2798
#define BCE_DMA_CONFIG_CNTL_PING_PONG_DMA		 (1L<<10)
2799
#define BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY		 (1L<<11)
2800
#define BCE_DMA_CONFIG_NO_RCHANS_IN_USE		 (0xfL<<12)
2801
#define BCE_DMA_CONFIG_NO_WCHANS_IN_USE		 (0xfL<<16)
2802
#define BCE_DMA_CONFIG_PCI_CLK_CMP_BITS		 (0x7L<<20)
2803
#define BCE_DMA_CONFIG_PCI_FAST_CLK_CMP		 (1L<<23)
2804
#define BCE_DMA_CONFIG_BIG_SIZE			 (0xfL<<24)
2805
#define BCE_DMA_CONFIG_BIG_SIZE_NONE			 (0x0L<<24)
2806
#define BCE_DMA_CONFIG_BIG_SIZE_64			 (0x1L<<24)
2807
#define BCE_DMA_CONFIG_BIG_SIZE_128			 (0x2L<<24)
2808
#define BCE_DMA_CONFIG_BIG_SIZE_256			 (0x4L<<24)
2809
#define BCE_DMA_CONFIG_BIG_SIZE_512			 (0x8L<<24)
2810

2811
#define BCE_DMA_BLACKOUT				0x00000c0c
2812
#define BCE_DMA_BLACKOUT_RD_RETRY_BLACKOUT		 (0xffL<<0)
2813
#define BCE_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT		 (0xffL<<8)
2814
#define BCE_DMA_BLACKOUT_WR_RETRY_BLACKOUT		 (0xffL<<16)
2815

2816
#define BCE_DMA_RCHAN_STAT				0x00000c30
2817
#define BCE_DMA_RCHAN_STAT_COMP_CODE_0			 (0x7L<<0)
2818
#define BCE_DMA_RCHAN_STAT_PAR_ERR_0			 (1L<<3)
2819
#define BCE_DMA_RCHAN_STAT_COMP_CODE_1			 (0x7L<<4)
2820
#define BCE_DMA_RCHAN_STAT_PAR_ERR_1			 (1L<<7)
2821
#define BCE_DMA_RCHAN_STAT_COMP_CODE_2			 (0x7L<<8)
2822
#define BCE_DMA_RCHAN_STAT_PAR_ERR_2			 (1L<<11)
2823
#define BCE_DMA_RCHAN_STAT_COMP_CODE_3			 (0x7L<<12)
2824
#define BCE_DMA_RCHAN_STAT_PAR_ERR_3			 (1L<<15)
2825
#define BCE_DMA_RCHAN_STAT_COMP_CODE_4			 (0x7L<<16)
2826
#define BCE_DMA_RCHAN_STAT_PAR_ERR_4			 (1L<<19)
2827
#define BCE_DMA_RCHAN_STAT_COMP_CODE_5			 (0x7L<<20)
2828
#define BCE_DMA_RCHAN_STAT_PAR_ERR_5			 (1L<<23)
2829
#define BCE_DMA_RCHAN_STAT_COMP_CODE_6			 (0x7L<<24)
2830
#define BCE_DMA_RCHAN_STAT_PAR_ERR_6			 (1L<<27)
2831
#define BCE_DMA_RCHAN_STAT_COMP_CODE_7			 (0x7L<<28)
2832
#define BCE_DMA_RCHAN_STAT_PAR_ERR_7			 (1L<<31)
2833

2834
#define BCE_DMA_WCHAN_STAT				0x00000c34
2835
#define BCE_DMA_WCHAN_STAT_COMP_CODE_0			 (0x7L<<0)
2836
#define BCE_DMA_WCHAN_STAT_PAR_ERR_0			 (1L<<3)
2837
#define BCE_DMA_WCHAN_STAT_COMP_CODE_1			 (0x7L<<4)
2838
#define BCE_DMA_WCHAN_STAT_PAR_ERR_1			 (1L<<7)
2839
#define BCE_DMA_WCHAN_STAT_COMP_CODE_2			 (0x7L<<8)
2840
#define BCE_DMA_WCHAN_STAT_PAR_ERR_2			 (1L<<11)
2841
#define BCE_DMA_WCHAN_STAT_COMP_CODE_3			 (0x7L<<12)
2842
#define BCE_DMA_WCHAN_STAT_PAR_ERR_3			 (1L<<15)
2843
#define BCE_DMA_WCHAN_STAT_COMP_CODE_4			 (0x7L<<16)
2844
#define BCE_DMA_WCHAN_STAT_PAR_ERR_4			 (1L<<19)
2845
#define BCE_DMA_WCHAN_STAT_COMP_CODE_5			 (0x7L<<20)
2846
#define BCE_DMA_WCHAN_STAT_PAR_ERR_5			 (1L<<23)
2847
#define BCE_DMA_WCHAN_STAT_COMP_CODE_6			 (0x7L<<24)
2848
#define BCE_DMA_WCHAN_STAT_PAR_ERR_6			 (1L<<27)
2849
#define BCE_DMA_WCHAN_STAT_COMP_CODE_7			 (0x7L<<28)
2850
#define BCE_DMA_WCHAN_STAT_PAR_ERR_7			 (1L<<31)
2851

2852
#define BCE_DMA_RCHAN_ASSIGNMENT			0x00000c38
2853
#define BCE_DMA_RCHAN_ASSIGNMENT_0			 (0xfL<<0)
2854
#define BCE_DMA_RCHAN_ASSIGNMENT_1			 (0xfL<<4)
2855
#define BCE_DMA_RCHAN_ASSIGNMENT_2			 (0xfL<<8)
2856
#define BCE_DMA_RCHAN_ASSIGNMENT_3			 (0xfL<<12)
2857
#define BCE_DMA_RCHAN_ASSIGNMENT_4			 (0xfL<<16)
2858
#define BCE_DMA_RCHAN_ASSIGNMENT_5			 (0xfL<<20)
2859
#define BCE_DMA_RCHAN_ASSIGNMENT_6			 (0xfL<<24)
2860
#define BCE_DMA_RCHAN_ASSIGNMENT_7			 (0xfL<<28)
2861

2862
#define BCE_DMA_WCHAN_ASSIGNMENT			0x00000c3c
2863
#define BCE_DMA_WCHAN_ASSIGNMENT_0			 (0xfL<<0)
2864
#define BCE_DMA_WCHAN_ASSIGNMENT_1			 (0xfL<<4)
2865
#define BCE_DMA_WCHAN_ASSIGNMENT_2			 (0xfL<<8)
2866
#define BCE_DMA_WCHAN_ASSIGNMENT_3			 (0xfL<<12)
2867
#define BCE_DMA_WCHAN_ASSIGNMENT_4			 (0xfL<<16)
2868
#define BCE_DMA_WCHAN_ASSIGNMENT_5			 (0xfL<<20)
2869
#define BCE_DMA_WCHAN_ASSIGNMENT_6			 (0xfL<<24)
2870
#define BCE_DMA_WCHAN_ASSIGNMENT_7			 (0xfL<<28)
2871

2872
#define BCE_DMA_RCHAN_STAT_00				0x00000c40
2873
#define BCE_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW	 (0xffffffffL<<0)
2874

2875
#define BCE_DMA_RCHAN_STAT_01				0x00000c44
2876
#define BCE_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH	 (0xffffffffL<<0)
2877

2878
#define BCE_DMA_RCHAN_STAT_02				0x00000c48
2879
#define BCE_DMA_RCHAN_STAT_02_LENGTH			 (0xffffL<<0)
2880
#define BCE_DMA_RCHAN_STAT_02_WORD_SWAP		 (1L<<16)
2881
#define BCE_DMA_RCHAN_STAT_02_BYTE_SWAP		 (1L<<17)
2882
#define BCE_DMA_RCHAN_STAT_02_PRIORITY_LVL		 (1L<<18)
2883

2884
#define BCE_DMA_RCHAN_STAT_10				0x00000c4c
2885
#define BCE_DMA_RCHAN_STAT_11				0x00000c50
2886
#define BCE_DMA_RCHAN_STAT_12				0x00000c54
2887
#define BCE_DMA_RCHAN_STAT_20				0x00000c58
2888
#define BCE_DMA_RCHAN_STAT_21				0x00000c5c
2889
#define BCE_DMA_RCHAN_STAT_22				0x00000c60
2890
#define BCE_DMA_RCHAN_STAT_30				0x00000c64
2891
#define BCE_DMA_RCHAN_STAT_31				0x00000c68
2892
#define BCE_DMA_RCHAN_STAT_32				0x00000c6c
2893
#define BCE_DMA_RCHAN_STAT_40				0x00000c70
2894
#define BCE_DMA_RCHAN_STAT_41				0x00000c74
2895
#define BCE_DMA_RCHAN_STAT_42				0x00000c78
2896
#define BCE_DMA_RCHAN_STAT_50				0x00000c7c
2897
#define BCE_DMA_RCHAN_STAT_51				0x00000c80
2898
#define BCE_DMA_RCHAN_STAT_52				0x00000c84
2899
#define BCE_DMA_RCHAN_STAT_60				0x00000c88
2900
#define BCE_DMA_RCHAN_STAT_61				0x00000c8c
2901
#define BCE_DMA_RCHAN_STAT_62				0x00000c90
2902
#define BCE_DMA_RCHAN_STAT_70				0x00000c94
2903
#define BCE_DMA_RCHAN_STAT_71				0x00000c98
2904
#define BCE_DMA_RCHAN_STAT_72				0x00000c9c
2905
#define BCE_DMA_WCHAN_STAT_00				0x00000ca0
2906
#define BCE_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW	 (0xffffffffL<<0)
2907

2908
#define BCE_DMA_WCHAN_STAT_01				0x00000ca4
2909
#define BCE_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH	 (0xffffffffL<<0)
2910

2911
#define BCE_DMA_WCHAN_STAT_02				0x00000ca8
2912
#define BCE_DMA_WCHAN_STAT_02_LENGTH			 (0xffffL<<0)
2913
#define BCE_DMA_WCHAN_STAT_02_WORD_SWAP		 (1L<<16)
2914
#define BCE_DMA_WCHAN_STAT_02_BYTE_SWAP		 (1L<<17)
2915
#define BCE_DMA_WCHAN_STAT_02_PRIORITY_LVL		 (1L<<18)
2916

2917
#define BCE_DMA_WCHAN_STAT_10				0x00000cac
2918
#define BCE_DMA_WCHAN_STAT_11				0x00000cb0
2919
#define BCE_DMA_WCHAN_STAT_12				0x00000cb4
2920
#define BCE_DMA_WCHAN_STAT_20				0x00000cb8
2921
#define BCE_DMA_WCHAN_STAT_21				0x00000cbc
2922
#define BCE_DMA_WCHAN_STAT_22				0x00000cc0
2923
#define BCE_DMA_WCHAN_STAT_30				0x00000cc4
2924
#define BCE_DMA_WCHAN_STAT_31				0x00000cc8
2925
#define BCE_DMA_WCHAN_STAT_32				0x00000ccc
2926
#define BCE_DMA_WCHAN_STAT_40				0x00000cd0
2927
#define BCE_DMA_WCHAN_STAT_41				0x00000cd4
2928
#define BCE_DMA_WCHAN_STAT_42				0x00000cd8
2929
#define BCE_DMA_WCHAN_STAT_50				0x00000cdc
2930
#define BCE_DMA_WCHAN_STAT_51				0x00000ce0
2931
#define BCE_DMA_WCHAN_STAT_52				0x00000ce4
2932
#define BCE_DMA_WCHAN_STAT_60				0x00000ce8
2933
#define BCE_DMA_WCHAN_STAT_61				0x00000cec
2934
#define BCE_DMA_WCHAN_STAT_62				0x00000cf0
2935
#define BCE_DMA_WCHAN_STAT_70				0x00000cf4
2936
#define BCE_DMA_WCHAN_STAT_71				0x00000cf8
2937
#define BCE_DMA_WCHAN_STAT_72				0x00000cfc
2938
#define BCE_DMA_ARB_STAT_00				0x00000d00
2939
#define BCE_DMA_ARB_STAT_00_MASTER			 (0xffffL<<0)
2940
#define BCE_DMA_ARB_STAT_00_MASTER_ENC			 (0xffL<<16)
2941
#define BCE_DMA_ARB_STAT_00_CUR_BINMSTR		 (0xffL<<24)
2942

2943
#define BCE_DMA_ARB_STAT_01				0x00000d04
2944
#define BCE_DMA_ARB_STAT_01_LPR_RPTR			 (0xfL<<0)
2945
#define BCE_DMA_ARB_STAT_01_LPR_WPTR			 (0xfL<<4)
2946
#define BCE_DMA_ARB_STAT_01_LPB_RPTR			 (0xfL<<8)
2947
#define BCE_DMA_ARB_STAT_01_LPB_WPTR			 (0xfL<<12)
2948
#define BCE_DMA_ARB_STAT_01_HPR_RPTR			 (0xfL<<16)
2949
#define BCE_DMA_ARB_STAT_01_HPR_WPTR			 (0xfL<<20)
2950
#define BCE_DMA_ARB_STAT_01_HPB_RPTR			 (0xfL<<24)
2951
#define BCE_DMA_ARB_STAT_01_HPB_WPTR			 (0xfL<<28)
2952

2953
#define BCE_DMA_FUSE_CTRL0_CMD				0x00000f00
2954
#define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE		 (1L<<0)
2955
#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT_DONE		 (1L<<1)
2956
#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT			 (1L<<2)
2957
#define BCE_DMA_FUSE_CTRL0_CMD_LOAD			 (1L<<3)
2958
#define BCE_DMA_FUSE_CTRL0_CMD_SEL			 (0xfL<<8)
2959

2960
#define BCE_DMA_FUSE_CTRL0_DATA			0x00000f04
2961
#define BCE_DMA_FUSE_CTRL1_CMD				0x00000f08
2962
#define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE		 (1L<<0)
2963
#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT_DONE		 (1L<<1)
2964
#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT			 (1L<<2)
2965
#define BCE_DMA_FUSE_CTRL1_CMD_LOAD			 (1L<<3)
2966
#define BCE_DMA_FUSE_CTRL1_CMD_SEL			 (0xfL<<8)
2967

2968
#define BCE_DMA_FUSE_CTRL1_DATA			0x00000f0c
2969
#define BCE_DMA_FUSE_CTRL2_CMD				0x00000f10
2970
#define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE		 (1L<<0)
2971
#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT_DONE		 (1L<<1)
2972
#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT			 (1L<<2)
2973
#define BCE_DMA_FUSE_CTRL2_CMD_LOAD			 (1L<<3)
2974
#define BCE_DMA_FUSE_CTRL2_CMD_SEL			 (0xfL<<8)
2975

2976
#define BCE_DMA_FUSE_CTRL2_DATA			0x00000f14
2977

2978
/*
2979
 *  context_reg definition
2980
 *  offset: 0x1000
2981
 */
2982
#define BCE_CTX_COMMAND									0x00001000
2983
#define BCE_CTX_COMMAND_ENABLED							(1L<<0)
2984
#define BCE_CTX_COMMAND_DISABLE_USAGE_CNT				(1L<<1)
2985
#define BCE_CTX_COMMAND_DISABLE_PLRU					(1L<<2)
2986
#define BCE_CTX_COMMAND_DISABLE_COMBINE_READ			(1L<<3)
2987
#define BCE_CTX_COMMAND_FLUSH_AHEAD						(0x1fL<<8)
2988
#define BCE_CTX_COMMAND_MEM_INIT						(1L<<13)
2989
#define BCE_CTX_COMMAND_PAGE_SIZE						(0xfL<<16)
2990
#define BCE_CTX_COMMAND_PAGE_SIZE_256					(0L<<16)
2991
#define BCE_CTX_COMMAND_PAGE_SIZE_512					(1L<<16)
2992
#define BCE_CTX_COMMAND_PAGE_SIZE_1K					(2L<<16)
2993
#define BCE_CTX_COMMAND_PAGE_SIZE_2K					(3L<<16)
2994
#define BCE_CTX_COMMAND_PAGE_SIZE_4K					(4L<<16)
2995
#define BCE_CTX_COMMAND_PAGE_SIZE_8K					(5L<<16)
2996
#define BCE_CTX_COMMAND_PAGE_SIZE_16K					(6L<<16)
2997
#define BCE_CTX_COMMAND_PAGE_SIZE_32K					(7L<<16)
2998
#define BCE_CTX_COMMAND_PAGE_SIZE_64K					(8L<<16)
2999
#define BCE_CTX_COMMAND_PAGE_SIZE_128K					(9L<<16)
3000
#define BCE_CTX_COMMAND_PAGE_SIZE_256K					(10L<<16)
3001
#define BCE_CTX_COMMAND_PAGE_SIZE_512K					(11L<<16)
3002
#define BCE_CTX_COMMAND_PAGE_SIZE_1M					(12L<<16)
3003

3004
#define BCE_CTX_STATUS									0x00001004
3005
#define BCE_CTX_STATUS_LOCK_WAIT						(1L<<0)
3006
#define BCE_CTX_STATUS_READ_STAT						(1L<<16)
3007
#define BCE_CTX_STATUS_WRITE_STAT						(1L<<17)
3008
#define BCE_CTX_STATUS_ACC_STALL_STAT					(1L<<18)
3009
#define BCE_CTX_STATUS_LOCK_STALL_STAT					(1L<<19)
3010
#define BCE_CTX_STATUS_EXT_READ_STAT					(1L<<20)
3011
#define BCE_CTX_STATUS_EXT_WRITE_STAT					(1L<<21)
3012
#define BCE_CTX_STATUS_MISS_STAT						(1L<<22)
3013
#define BCE_CTX_STATUS_HIT_STAT							(1L<<23)
3014
#define BCE_CTX_STATUS_DEAD_LOCK						(1L<<24)
3015
#define BCE_CTX_STATUS_USAGE_CNT_ERR					(1L<<25)
3016
#define BCE_CTX_STATUS_INVALID_PAGE						(1L<<26)
3017

3018
#define BCE_CTX_VIRT_ADDR								0x00001008
3019
#define BCE_CTX_VIRT_ADDR_VIRT_ADDR						(0x7fffL<<6)
3020

3021
#define BCE_CTX_PAGE_TBL								0x0000100c
3022
#define BCE_CTX_PAGE_TBL_PAGE_TBL						(0x3fffL<<6)
3023

3024
#define BCE_CTX_DATA_ADR								0x00001010
3025
#define BCE_CTX_DATA_ADR_DATA_ADR						(0x7ffffL<<2)
3026

3027
#define BCE_CTX_DATA									0x00001014
3028
#define BCE_CTX_LOCK									0x00001018
3029
#define BCE_CTX_LOCK_TYPE								(0x7L<<0)
3030
#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID				(0x0L<<0)
3031
#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL			(0x1L<<0)
3032
#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX					(0x2L<<0)
3033
#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER				(0x4L<<0)
3034
#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE			(0x7L<<0)
3035
#define BCE_CTX_LOCK_TYPE_VOID_XI						(0L<<0)
3036
#define BCE_CTX_LOCK_TYPE_PROTOCOL_XI					(1L<<0)
3037
#define BCE_CTX_LOCK_TYPE_TX_XI							(2L<<0)
3038
#define BCE_CTX_LOCK_TYPE_TIMER_XI						(4L<<0)
3039
#define BCE_CTX_LOCK_TYPE_COMPLETE_XI					(7L<<0)
3040
#define BCE_CTX_LOCK_CID_VALUE							(0x3fffL<<7)
3041
#define BCE_CTX_LOCK_GRANTED							(1L<<26)
3042
#define BCE_CTX_LOCK_MODE								(0x7L<<27)
3043
#define BCE_CTX_LOCK_MODE_UNLOCK						(0x0L<<27)
3044
#define BCE_CTX_LOCK_MODE_IMMEDIATE						(0x1L<<27)
3045
#define BCE_CTX_LOCK_MODE_SURE							(0x2L<<27)
3046
#define BCE_CTX_LOCK_STATUS								(1L<<30)
3047
#define BCE_CTX_LOCK_REQ								(1L<<31)
3048

3049
#define BCE_CTX_CTX_CTRL								0x0000101c
3050
#define BCE_CTX_CTX_CTRL_CTX_ADDR						(0x7ffffL<<2)
3051
#define BCE_CTX_CTX_CTRL_MOD_USAGE_CNT					(0x3L<<21)
3052
#define BCE_CTX_CTX_CTRL_NO_RAM_ACC						(1L<<23)
3053
#define BCE_CTX_CTX_CTRL_PREFETCH_SIZE					(0x3L<<24)
3054
#define BCE_CTX_CTX_CTRL_ATTR							(1L<<26)
3055
#define BCE_CTX_CTX_CTRL_WRITE_REQ						(1L<<30)
3056
#define BCE_CTX_CTX_CTRL_READ_REQ						(1L<<31)
3057

3058
#define BCE_CTX_CTX_DATA								0x00001020
3059
#define BCE_CTX_ACCESS_STATUS							0x00001040
3060
#define BCE_CTX_ACCESS_STATUS_MASTERENCODED				(0xfL<<0)
3061
#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM			(0x3L<<10)
3062
#define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM			(0x3L<<12)
3063
#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM		(0x3L<<14)
3064
#define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST			(0x7ffL<<17)
3065
#define BCE_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI		(0x1fL<<0)
3066
#define BCE_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI		(0x1fL<<5)
3067
#define BCE_CTX_ACCESS_STATUS_REQUEST_XI				(0x3fffffL<<10)
3068

3069
#define BCE_CTX_DBG_LOCK_STATUS							0x00001044
3070
#define BCE_CTX_DBG_LOCK_STATUS_SM						(0x3ffL<<0)
3071
#define BCE_CTX_DBG_LOCK_STATUS_MATCH					(0x3ffL<<22)
3072

3073
#define BCE_CTX_CACHE_CTRL_STATUS						0x00001048
3074
#define BCE_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW		(1L<<0)
3075
#define BCE_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP		(1L<<1)
3076
#define BCE_CTX_CACHE_CTRL_STATUS_FLUSH_START			(1L<<6)
3077
#define BCE_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT		(0x3fL<<7)
3078
#define BCE_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED	(0x3fL<<13)
3079
#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE		(1L<<19)
3080
#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE		(1L<<20)
3081
#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE		(1L<<21)
3082
#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE		(1L<<22)
3083
#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE		(1L<<23)
3084
#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE		(1L<<24)
3085
#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE		(1L<<25)
3086
#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE		(1L<<26)
3087
#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE		(1L<<27)
3088
#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE		(1L<<28)
3089
#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE		(1L<<29)
3090

3091
#define BCE_CTX_CACHE_CTRL_SM_STATUS					0x0000104c
3092
#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_DWC				(0x7L<<0)
3093
#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC			(0x7L<<3)
3094
#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC			(0x7L<<6)
3095
#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC			(0x7L<<9)
3096
#define BCE_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR	(0x7fffL<<16)
3097

3098
#define BCE_CTX_CACHE_STATUS							0x00001050
3099
#define BCE_CTX_CACHE_STATUS_HELD_ENTRIES				(0x3ffL<<0)
3100
#define BCE_CTX_CACHE_STATUS_MAX_HELD_ENTRIES			(0x3ffL<<16)
3101

3102
#define BCE_CTX_DMA_STATUS								0x00001054
3103
#define BCE_CTX_DMA_STATUS_RD_CHAN0_STATUS				(0x3L<<0)
3104
#define BCE_CTX_DMA_STATUS_RD_CHAN1_STATUS				(0x3L<<2)
3105
#define BCE_CTX_DMA_STATUS_RD_CHAN2_STATUS				(0x3L<<4)
3106
#define BCE_CTX_DMA_STATUS_RD_CHAN3_STATUS				(0x3L<<6)
3107
#define BCE_CTX_DMA_STATUS_RD_CHAN4_STATUS				(0x3L<<8)
3108
#define BCE_CTX_DMA_STATUS_RD_CHAN5_STATUS				(0x3L<<10)
3109
#define BCE_CTX_DMA_STATUS_RD_CHAN6_STATUS				(0x3L<<12)
3110
#define BCE_CTX_DMA_STATUS_RD_CHAN7_STATUS				(0x3L<<14)
3111
#define BCE_CTX_DMA_STATUS_RD_CHAN8_STATUS				(0x3L<<16)
3112
#define BCE_CTX_DMA_STATUS_RD_CHAN9_STATUS				(0x3L<<18)
3113
#define BCE_CTX_DMA_STATUS_RD_CHAN10_STATUS				(0x3L<<20)
3114

3115
#define BCE_CTX_REP_STATUS								0x00001058
3116
#define BCE_CTX_REP_STATUS_ERROR_ENTRY					(0x3ffL<<0)
3117
#define BCE_CTX_REP_STATUS_ERROR_CLIENT_ID				(0x1fL<<10)
3118
#define BCE_CTX_REP_STATUS_USAGE_CNT_MAX_ERR			(1L<<16)
3119
#define BCE_CTX_REP_STATUS_USAGE_CNT_MIN_ERR			(1L<<17)
3120
#define BCE_CTX_REP_STATUS_USAGE_CNT_MISS_ERR			(1L<<18)
3121

3122
#define BCE_CTX_CKSUM_ERROR_STATUS						0x0000105c
3123
#define BCE_CTX_CKSUM_ERROR_STATUS_CALCULATED			(0xffffL<<0)
3124
#define BCE_CTX_CKSUM_ERROR_STATUS_EXPECTED				(0xffffL<<16)
3125

3126
#define BCE_CTX_CHNL_LOCK_STATUS_0						0x00001080
3127
#define BCE_CTX_CHNL_LOCK_STATUS_0_CID					(0x3fffL<<0)
3128
#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE					(0x3L<<14)
3129
#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE					(1L<<16)
3130
#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE_XI				(1L<<14)
3131
#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE_XI				(0x7L<<15)
3132

3133
#define BCE_CTX_CHNL_LOCK_STATUS_1						0x00001084
3134
#define BCE_CTX_CHNL_LOCK_STATUS_2						0x00001088
3135
#define BCE_CTX_CHNL_LOCK_STATUS_3						0x0000108c
3136
#define BCE_CTX_CHNL_LOCK_STATUS_4						0x00001090
3137
#define BCE_CTX_CHNL_LOCK_STATUS_5						0x00001094
3138
#define BCE_CTX_CHNL_LOCK_STATUS_6						0x00001098
3139
#define BCE_CTX_CHNL_LOCK_STATUS_7						0x0000109c
3140
#define BCE_CTX_CHNL_LOCK_STATUS_8						0x000010a0
3141
#define BCE_CTX_CHNL_LOCK_STATUS_9						0x000010a4
3142

3143
#define BCE_CTX_CACHE_DATA								0x000010c4
3144
#define BCE_CTX_HOST_PAGE_TBL_CTRL						0x000010c8
3145
#define BCE_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR		(0x1ffL<<0)
3146
#define BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ			(1L<<30)
3147
#define BCE_CTX_HOST_PAGE_TBL_CTRL_READ_REQ				(1L<<31)
3148

3149
#define BCE_CTX_HOST_PAGE_TBL_DATA0						0x000010cc
3150
#define BCE_CTX_HOST_PAGE_TBL_DATA0_VALID				(1L<<0)
3151
#define BCE_CTX_HOST_PAGE_TBL_DATA0_VALUE				(0xffffffL<<8)
3152

3153
#define BCE_CTX_HOST_PAGE_TBL_DATA1						0x000010d0
3154
#define BCE_CTX_CAM_CTRL								0x000010d4
3155
#define BCE_CTX_CAM_CTRL_CAM_ADDR						(0x3ffL<<0)
3156
#define BCE_CTX_CAM_CTRL_RESET							(1L<<27)
3157
#define BCE_CTX_CAM_CTRL_INVALIDATE						(1L<<28)
3158
#define BCE_CTX_CAM_CTRL_SEARCH							(1L<<29)
3159
#define BCE_CTX_CAM_CTRL_WRITE_REQ						(1L<<30)
3160
#define BCE_CTX_CAM_CTRL_READ_REQ						(1L<<31)
3161

3162
/*
3163
 *  emac_reg definition
3164
 *  offset: 0x1400
3165
 */
3166
#define BCE_EMAC_MODE					0x00001400
3167
#define BCE_EMAC_MODE_RESET				 (1L<<0)
3168
#define BCE_EMAC_MODE_HALF_DUPLEX			 (1L<<1)
3169
#define BCE_EMAC_MODE_PORT				 (0x3L<<2)
3170
#define BCE_EMAC_MODE_PORT_NONE			 (0L<<2)
3171
#define BCE_EMAC_MODE_PORT_MII				 (1L<<2)
3172
#define BCE_EMAC_MODE_PORT_GMII			 (2L<<2)
3173
#define BCE_EMAC_MODE_PORT_MII_10			 (3L<<2)
3174
#define BCE_EMAC_MODE_MAC_LOOP				 (1L<<4)
3175
#define BCE_EMAC_MODE_25G				 (1L<<5)
3176
#define BCE_EMAC_MODE_TAGGED_MAC_CTL			 (1L<<7)
3177
#define BCE_EMAC_MODE_TX_BURST				 (1L<<8)
3178
#define BCE_EMAC_MODE_MAX_DEFER_DROP_ENA		 (1L<<9)
3179
#define BCE_EMAC_MODE_EXT_LINK_POL			 (1L<<10)
3180
#define BCE_EMAC_MODE_FORCE_LINK			 (1L<<11)
3181
#define BCE_EMAC_MODE_MPKT				 (1L<<18)
3182
#define BCE_EMAC_MODE_MPKT_RCVD			 (1L<<19)
3183
#define BCE_EMAC_MODE_ACPI_RCVD			 (1L<<20)
3184

3185
#define BCE_EMAC_STATUS				0x00001404
3186
#define BCE_EMAC_STATUS_LINK				 (1L<<11)
3187
#define BCE_EMAC_STATUS_LINK_CHANGE			 (1L<<12)
3188
#define BCE_EMAC_STATUS_MI_COMPLETE			 (1L<<22)
3189
#define BCE_EMAC_STATUS_MI_INT				 (1L<<23)
3190
#define BCE_EMAC_STATUS_AP_ERROR			 (1L<<24)
3191
#define BCE_EMAC_STATUS_PARITY_ERROR_STATE		 (1L<<31)
3192

3193
#define BCE_EMAC_ATTENTION_ENA				0x00001408
3194
#define BCE_EMAC_ATTENTION_ENA_LINK			 (1L<<11)
3195
#define BCE_EMAC_ATTENTION_ENA_MI_COMPLETE		 (1L<<22)
3196
#define BCE_EMAC_ATTENTION_ENA_MI_INT			 (1L<<23)
3197
#define BCE_EMAC_ATTENTION_ENA_AP_ERROR		 (1L<<24)
3198

3199
#define BCE_EMAC_LED					0x0000140c
3200
#define BCE_EMAC_LED_OVERRIDE				 (1L<<0)
3201
#define BCE_EMAC_LED_1000MB_OVERRIDE			 (1L<<1)
3202
#define BCE_EMAC_LED_100MB_OVERRIDE			 (1L<<2)
3203
#define BCE_EMAC_LED_10MB_OVERRIDE			 (1L<<3)
3204
#define BCE_EMAC_LED_TRAFFIC_OVERRIDE			 (1L<<4)
3205
#define BCE_EMAC_LED_BLNK_TRAFFIC			 (1L<<5)
3206
#define BCE_EMAC_LED_TRAFFIC				 (1L<<6)
3207
#define BCE_EMAC_LED_1000MB				 (1L<<7)
3208
#define BCE_EMAC_LED_100MB				 (1L<<8)
3209
#define BCE_EMAC_LED_10MB				 (1L<<9)
3210
#define BCE_EMAC_LED_TRAFFIC_STAT			 (1L<<10)
3211
#define BCE_EMAC_LED_BLNK_RATE				 (0xfffL<<19)
3212
#define BCE_EMAC_LED_BLNK_RATE_ENA			 (1L<<31)
3213

3214
#define BCE_EMAC_MAC_MATCH0				0x00001410
3215
#define BCE_EMAC_MAC_MATCH1				0x00001414
3216
#define BCE_EMAC_MAC_MATCH2				0x00001418
3217
#define BCE_EMAC_MAC_MATCH3				0x0000141c
3218
#define BCE_EMAC_MAC_MATCH4				0x00001420
3219
#define BCE_EMAC_MAC_MATCH5				0x00001424
3220
#define BCE_EMAC_MAC_MATCH6				0x00001428
3221
#define BCE_EMAC_MAC_MATCH7				0x0000142c
3222
#define BCE_EMAC_MAC_MATCH8				0x00001430
3223
#define BCE_EMAC_MAC_MATCH9				0x00001434
3224
#define BCE_EMAC_MAC_MATCH10				0x00001438
3225
#define BCE_EMAC_MAC_MATCH11				0x0000143c
3226
#define BCE_EMAC_MAC_MATCH12				0x00001440
3227
#define BCE_EMAC_MAC_MATCH13				0x00001444
3228
#define BCE_EMAC_MAC_MATCH14				0x00001448
3229
#define BCE_EMAC_MAC_MATCH15				0x0000144c
3230
#define BCE_EMAC_MAC_MATCH16				0x00001450
3231
#define BCE_EMAC_MAC_MATCH17				0x00001454
3232
#define BCE_EMAC_MAC_MATCH18				0x00001458
3233
#define BCE_EMAC_MAC_MATCH19				0x0000145c
3234
#define BCE_EMAC_MAC_MATCH20				0x00001460
3235
#define BCE_EMAC_MAC_MATCH21				0x00001464
3236
#define BCE_EMAC_MAC_MATCH22				0x00001468
3237
#define BCE_EMAC_MAC_MATCH23				0x0000146c
3238
#define BCE_EMAC_MAC_MATCH24				0x00001470
3239
#define BCE_EMAC_MAC_MATCH25				0x00001474
3240
#define BCE_EMAC_MAC_MATCH26				0x00001478
3241
#define BCE_EMAC_MAC_MATCH27				0x0000147c
3242
#define BCE_EMAC_MAC_MATCH28				0x00001480
3243
#define BCE_EMAC_MAC_MATCH29				0x00001484
3244
#define BCE_EMAC_MAC_MATCH30				0x00001488
3245
#define BCE_EMAC_MAC_MATCH31				0x0000148c
3246
#define BCE_EMAC_BACKOFF_SEED				0x00001498
3247
#define BCE_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED	 (0x3ffL<<0)
3248

3249
#define BCE_EMAC_RX_MTU_SIZE				0x0000149c
3250
#define BCE_EMAC_RX_MTU_SIZE_MTU_SIZE			 (0xffffL<<0)
3251
#define BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA			 (1L<<31)
3252

3253
#define BCE_EMAC_SERDES_CNTL				0x000014a4
3254
#define BCE_EMAC_SERDES_CNTL_RXR			 (0x7L<<0)
3255
#define BCE_EMAC_SERDES_CNTL_RXG			 (0x3L<<3)
3256
#define BCE_EMAC_SERDES_CNTL_RXCKSEL			 (1L<<6)
3257
#define BCE_EMAC_SERDES_CNTL_TXBIAS			 (0x7L<<7)
3258
#define BCE_EMAC_SERDES_CNTL_BGMAX			 (1L<<10)
3259
#define BCE_EMAC_SERDES_CNTL_BGMIN			 (1L<<11)
3260
#define BCE_EMAC_SERDES_CNTL_TXMODE			 (1L<<12)
3261
#define BCE_EMAC_SERDES_CNTL_TXEDGE			 (1L<<13)
3262
#define BCE_EMAC_SERDES_CNTL_SERDES_MODE		 (1L<<14)
3263
#define BCE_EMAC_SERDES_CNTL_PLLTEST			 (1L<<15)
3264
#define BCE_EMAC_SERDES_CNTL_CDET_EN			 (1L<<16)
3265
#define BCE_EMAC_SERDES_CNTL_TBI_LBK			 (1L<<17)
3266
#define BCE_EMAC_SERDES_CNTL_REMOTE_LBK		 (1L<<18)
3267
#define BCE_EMAC_SERDES_CNTL_REV_PHASE			 (1L<<19)
3268
#define BCE_EMAC_SERDES_CNTL_REGCTL12			 (0x3L<<20)
3269
#define BCE_EMAC_SERDES_CNTL_REGCTL25			 (0x3L<<22)
3270

3271
#define BCE_EMAC_SERDES_STATUS				0x000014a8
3272
#define BCE_EMAC_SERDES_STATUS_RX_STAT			 (0xffL<<0)
3273
#define BCE_EMAC_SERDES_STATUS_COMMA_DET		 (1L<<8)
3274

3275
#define BCE_EMAC_MDIO_COMM				0x000014ac
3276
#define BCE_EMAC_MDIO_COMM_DATA			 (0xffffL<<0)
3277
#define BCE_EMAC_MDIO_COMM_REG_ADDR			 (0x1fL<<16)
3278
#define BCE_EMAC_MDIO_COMM_PHY_ADDR			 (0x1fL<<21)
3279
#define BCE_EMAC_MDIO_COMM_COMMAND			 (0x3L<<26)
3280
#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0		 (0L<<26)
3281
#define BCE_EMAC_MDIO_COMM_COMMAND_WRITE		 (1L<<26)
3282
#define BCE_EMAC_MDIO_COMM_COMMAND_READ		 (2L<<26)
3283
#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3		 (3L<<26)
3284
#define BCE_EMAC_MDIO_COMM_FAIL			 (1L<<28)
3285
#define BCE_EMAC_MDIO_COMM_START_BUSY			 (1L<<29)
3286
#define BCE_EMAC_MDIO_COMM_DISEXT			 (1L<<30)
3287

3288
#define BCE_EMAC_MDIO_STATUS				0x000014b0
3289
#define BCE_EMAC_MDIO_STATUS_LINK			 (1L<<0)
3290
#define BCE_EMAC_MDIO_STATUS_10MB			 (1L<<1)
3291

3292
#define BCE_EMAC_MDIO_MODE				0x000014b4
3293
#define BCE_EMAC_MDIO_MODE_SHORT_PREAMBLE		 (1L<<1)
3294
#define BCE_EMAC_MDIO_MODE_AUTO_POLL			 (1L<<4)
3295
#define BCE_EMAC_MDIO_MODE_BIT_BANG			 (1L<<8)
3296
#define BCE_EMAC_MDIO_MODE_MDIO			 (1L<<9)
3297
#define BCE_EMAC_MDIO_MODE_MDIO_OE			 (1L<<10)
3298
#define BCE_EMAC_MDIO_MODE_MDC				 (1L<<11)
3299
#define BCE_EMAC_MDIO_MODE_MDINT			 (1L<<12)
3300
#define BCE_EMAC_MDIO_MODE_CLOCK_CNT			 (0x1fL<<16)
3301

3302
#define BCE_EMAC_MDIO_AUTO_STATUS			0x000014b8
3303
#define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR		 (1L<<0)
3304

3305
#define BCE_EMAC_TX_MODE				0x000014bc
3306
#define BCE_EMAC_TX_MODE_RESET				 (1L<<0)
3307
#define BCE_EMAC_TX_MODE_EXT_PAUSE_EN			 (1L<<3)
3308
#define BCE_EMAC_TX_MODE_FLOW_EN			 (1L<<4)
3309
#define BCE_EMAC_TX_MODE_BIG_BACKOFF			 (1L<<5)
3310
#define BCE_EMAC_TX_MODE_LONG_PAUSE			 (1L<<6)
3311
#define BCE_EMAC_TX_MODE_LINK_AWARE			 (1L<<7)
3312

3313
#define BCE_EMAC_TX_STATUS				0x000014c0
3314
#define BCE_EMAC_TX_STATUS_XOFFED			 (1L<<0)
3315
#define BCE_EMAC_TX_STATUS_XOFF_SENT			 (1L<<1)
3316
#define BCE_EMAC_TX_STATUS_XON_SENT			 (1L<<2)
3317
#define BCE_EMAC_TX_STATUS_LINK_UP			 (1L<<3)
3318
#define BCE_EMAC_TX_STATUS_UNDERRUN			 (1L<<4)
3319

3320
#define BCE_EMAC_TX_LENGTHS				0x000014c4
3321
#define BCE_EMAC_TX_LENGTHS_SLOT			 (0xffL<<0)
3322
#define BCE_EMAC_TX_LENGTHS_IPG			 (0xfL<<8)
3323
#define BCE_EMAC_TX_LENGTHS_IPG_CRS			 (0x3L<<12)
3324

3325
#define BCE_EMAC_RX_MODE				0x000014c8
3326
#define BCE_EMAC_RX_MODE_RESET				 (1L<<0)
3327
#define BCE_EMAC_RX_MODE_FLOW_EN			 (1L<<2)
3328
#define BCE_EMAC_RX_MODE_KEEP_MAC_CONTROL		 (1L<<3)
3329
#define BCE_EMAC_RX_MODE_KEEP_PAUSE			 (1L<<4)
3330
#define BCE_EMAC_RX_MODE_ACCEPT_OVERSIZE		 (1L<<5)
3331
#define BCE_EMAC_RX_MODE_ACCEPT_RUNTS			 (1L<<6)
3332
#define BCE_EMAC_RX_MODE_LLC_CHK			 (1L<<7)
3333
#define BCE_EMAC_RX_MODE_PROMISCUOUS			 (1L<<8)
3334
#define BCE_EMAC_RX_MODE_NO_CRC_CHK			 (1L<<9)
3335
#define BCE_EMAC_RX_MODE_KEEP_VLAN_TAG			 (1L<<10)
3336
#define BCE_EMAC_RX_MODE_FILT_BROADCAST		 (1L<<11)
3337
#define BCE_EMAC_RX_MODE_SORT_MODE			 (1L<<12)
3338

3339
#define BCE_EMAC_RX_STATUS				0x000014cc
3340
#define BCE_EMAC_RX_STATUS_FFED			 (1L<<0)
3341
#define BCE_EMAC_RX_STATUS_FF_RECEIVED			 (1L<<1)
3342
#define BCE_EMAC_RX_STATUS_N_RECEIVED			 (1L<<2)
3343

3344
#define BCE_EMAC_MULTICAST_HASH0			0x000014d0
3345
#define BCE_EMAC_MULTICAST_HASH1			0x000014d4
3346
#define BCE_EMAC_MULTICAST_HASH2			0x000014d8
3347
#define BCE_EMAC_MULTICAST_HASH3			0x000014dc
3348
#define BCE_EMAC_MULTICAST_HASH4			0x000014e0
3349
#define BCE_EMAC_MULTICAST_HASH5			0x000014e4
3350
#define BCE_EMAC_MULTICAST_HASH6			0x000014e8
3351
#define BCE_EMAC_MULTICAST_HASH7			0x000014ec
3352
#define BCE_EMAC_RX_STAT_IFHCINOCTETS			0x00001500
3353
#define BCE_EMAC_RX_STAT_IFHCINBADOCTETS		0x00001504
3354
#define BCE_EMAC_RX_STAT_ETHERSTATSFRAGMENTS		0x00001508
3355
#define BCE_EMAC_RX_STAT_IFHCINUCASTPKTS		0x0000150c
3356
#define BCE_EMAC_RX_STAT_IFHCINMULTICASTPKTS		0x00001510
3357
#define BCE_EMAC_RX_STAT_IFHCINBROADCASTPKTS		0x00001514
3358
#define BCE_EMAC_RX_STAT_DOT3STATSFCSERRORS		0x00001518
3359
#define BCE_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS	0x0000151c
3360
#define BCE_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS	0x00001520
3361
#define BCE_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED	0x00001524
3362
#define BCE_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED	0x00001528
3363
#define BCE_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED	0x0000152c
3364
#define BCE_EMAC_RX_STAT_XOFFSTATEENTERED		0x00001530
3365
#define BCE_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG	0x00001534
3366
#define BCE_EMAC_RX_STAT_ETHERSTATSJABBERS		0x00001538
3367
#define BCE_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS	0x0000153c
3368
#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS	0x00001540
3369
#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS	0x00001544
3370
#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS	0x00001548
3371
#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS	0x0000154c
3372
#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS	0x00001550
3373
#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS	0x00001554
3374
#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS	0x00001558
3375
#define BCE_EMAC_RXMAC_DEBUG0				0x0000155c
3376
#define BCE_EMAC_RXMAC_DEBUG1				0x00001560
3377
#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT	 (1L<<0)
3378
#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE		 (1L<<1)
3379
#define BCE_EMAC_RXMAC_DEBUG1_BAD_CRC			 (1L<<2)
3380
#define BCE_EMAC_RXMAC_DEBUG1_RX_ERROR			 (1L<<3)
3381
#define BCE_EMAC_RXMAC_DEBUG1_ALIGN_ERROR		 (1L<<4)
3382
#define BCE_EMAC_RXMAC_DEBUG1_LAST_DATA		 (1L<<5)
3383
#define BCE_EMAC_RXMAC_DEBUG1_ODD_BYTE_START		 (1L<<6)
3384
#define BCE_EMAC_RXMAC_DEBUG1_BYTE_COUNT		 (0xffffL<<7)
3385
#define BCE_EMAC_RXMAC_DEBUG1_SLOT_TIME		 (0xffL<<23)
3386

3387
#define BCE_EMAC_RXMAC_DEBUG2				0x00001564
3388
#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE			 (0x7L<<0)
3389
#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE		 (0x0L<<0)
3390
#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SFD		 (0x1L<<0)
3391
#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DATA		 (0x2L<<0)
3392
#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP		 (0x3L<<0)
3393
#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_EXT		 (0x4L<<0)
3394
#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DROP		 (0x5L<<0)
3395
#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP		 (0x6L<<0)
3396
#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_FC		 (0x7L<<0)
3397
#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE		 (0xfL<<3)
3398
#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE		 (0x0L<<3)
3399
#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0		 (0x1L<<3)
3400
#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1		 (0x2L<<3)
3401
#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2		 (0x3L<<3)
3402
#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3		 (0x4L<<3)
3403
#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT		 (0x5L<<3)
3404
#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT		 (0x6L<<3)
3405
#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS		 (0x7L<<3)
3406
#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST		 (0x8L<<3)
3407
#define BCE_EMAC_RXMAC_DEBUG2_BYTE_IN			 (0xffL<<7)
3408
#define BCE_EMAC_RXMAC_DEBUG2_FALSEC			 (1L<<15)
3409
#define BCE_EMAC_RXMAC_DEBUG2_TAGGED			 (1L<<16)
3410
#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE		 (1L<<18)
3411
#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE		 (0L<<18)
3412
#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED	 (1L<<18)
3413
#define BCE_EMAC_RXMAC_DEBUG2_SE_COUNTER		 (0xfL<<19)
3414
#define BCE_EMAC_RXMAC_DEBUG2_QUANTA			 (0x1fL<<23)
3415

3416
#define BCE_EMAC_RXMAC_DEBUG3				0x00001568
3417
#define BCE_EMAC_RXMAC_DEBUG3_PAUSE_CTR		 (0xffffL<<0)
3418
#define BCE_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR		 (0xffffL<<16)
3419

3420
#define BCE_EMAC_RXMAC_DEBUG4				0x0000156c
3421
#define BCE_EMAC_RXMAC_DEBUG4_TYPE_FIELD		 (0xffffL<<0)
3422
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE		 (0x3fL<<16)
3423
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE		 (0x0L<<16)
3424
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2		 (0x1L<<16)
3425
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3		 (0x2L<<16)
3426
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI		 (0x3L<<16)
3427
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2		 (0x7L<<16)
3428
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3		 (0x5L<<16)
3429
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1		 (0x6L<<16)
3430
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2		 (0x7L<<16)
3431
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3		 (0x8L<<16)
3432
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2		 (0x9L<<16)
3433
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3		 (0xaL<<16)
3434
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1	 (0xeL<<16)
3435
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2	 (0xfL<<16)
3436
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK	 (0x10L<<16)
3437
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC		 (0x11L<<16)
3438
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2		 (0x12L<<16)
3439
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3		 (0x13L<<16)
3440
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1		 (0x14L<<16)
3441
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2		 (0x15L<<16)
3442
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3		 (0x16L<<16)
3443
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE		 (0x17L<<16)
3444
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC		 (0x18L<<16)
3445
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE		 (0x19L<<16)
3446
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD		 (0x1aL<<16)
3447
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC		 (0x1bL<<16)
3448
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH		 (0x1cL<<16)
3449
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF		 (0x1dL<<16)
3450
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XON		 (0x1eL<<16)
3451
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED	 (0x1fL<<16)
3452
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED	 (0x20L<<16)
3453
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE		 (0x21L<<16)
3454
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL		 (0x22L<<16)
3455
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1		 (0x23L<<16)
3456
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2		 (0x24L<<16)
3457
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3		 (0x25L<<16)
3458
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE		 (0x26L<<16)
3459
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE	 (0x27L<<16)
3460
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL		 (0x28L<<16)
3461
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE		 (0x29L<<16)
3462
#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP		 (0x2aL<<16)
3463
#define BCE_EMAC_RXMAC_DEBUG4_DROP_PKT			 (1L<<22)
3464
#define BCE_EMAC_RXMAC_DEBUG4_SLOT_FILLED		 (1L<<23)
3465
#define BCE_EMAC_RXMAC_DEBUG4_FALSE_CARRIER		 (1L<<24)
3466
#define BCE_EMAC_RXMAC_DEBUG4_LAST_DATA		 (1L<<25)
3467
#define BCE_EMAC_RXMAC_DEBUG4_sfd_FOUND		 (1L<<26)
3468
#define BCE_EMAC_RXMAC_DEBUG4_ADVANCE			 (1L<<27)
3469
#define BCE_EMAC_RXMAC_DEBUG4_START			 (1L<<28)
3470

3471
#define BCE_EMAC_RXMAC_DEBUG5				0x00001570
3472
#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM			 (0x7L<<0)
3473
#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE		 (0L<<0)
3474
#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF	 (1L<<0)
3475
#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT	 (2L<<0)
3476
#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC	 (3L<<0)
3477
#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE	 (4L<<0)
3478
#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL	 (5L<<0)
3479
#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT	 (6L<<0)
3480
#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1		 (0x7L<<4)
3481
#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW		 (0x0L<<4)
3482
#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT		 (0x1L<<4)
3483
#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF		 (0x2L<<4)
3484
#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF		 (0x3L<<4)
3485
#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF		 (0x4L<<4)
3486
#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF		 (0x6L<<4)
3487
#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF		 (0x7L<<4)
3488
#define BCE_EMAC_RXMAC_DEBUG5_EOF_DETECTED		 (1L<<7)
3489
#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF0		 (0x7L<<8)
3490
#define BCE_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL	 (1L<<11)
3491
#define BCE_EMAC_RXMAC_DEBUG5_LOAD_CCODE		 (1L<<12)
3492
#define BCE_EMAC_RXMAC_DEBUG5_LOAD_DATA		 (1L<<13)
3493
#define BCE_EMAC_RXMAC_DEBUG5_LOAD_STAT		 (1L<<14)
3494
#define BCE_EMAC_RXMAC_DEBUG5_CLR_STAT			 (1L<<15)
3495
#define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE		 (0x3L<<16)
3496
#define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT		 (1L<<19)
3497
#define BCE_EMAC_RXMAC_DEBUG5_FMLEN			 (0xfffL<<20)
3498

3499
#define BCE_EMAC_RX_STAT_AC0				0x00001580
3500
#define BCE_EMAC_RX_STAT_AC1				0x00001584
3501
#define BCE_EMAC_RX_STAT_AC2				0x00001588
3502
#define BCE_EMAC_RX_STAT_AC3				0x0000158c
3503
#define BCE_EMAC_RX_STAT_AC4				0x00001590
3504
#define BCE_EMAC_RX_STAT_AC5				0x00001594
3505
#define BCE_EMAC_RX_STAT_AC6				0x00001598
3506
#define BCE_EMAC_RX_STAT_AC7				0x0000159c
3507
#define BCE_EMAC_RX_STAT_AC8				0x000015a0
3508
#define BCE_EMAC_RX_STAT_AC9				0x000015a4
3509
#define BCE_EMAC_RX_STAT_AC10				0x000015a8
3510
#define BCE_EMAC_RX_STAT_AC11				0x000015ac
3511
#define BCE_EMAC_RX_STAT_AC12				0x000015b0
3512
#define BCE_EMAC_RX_STAT_AC13				0x000015b4
3513
#define BCE_EMAC_RX_STAT_AC14				0x000015b8
3514
#define BCE_EMAC_RX_STAT_AC15				0x000015bc
3515
#define BCE_EMAC_RX_STAT_AC16				0x000015c0
3516
#define BCE_EMAC_RX_STAT_AC17				0x000015c4
3517
#define BCE_EMAC_RX_STAT_AC18				0x000015c8
3518
#define BCE_EMAC_RX_STAT_AC19				0x000015cc
3519
#define BCE_EMAC_RX_STAT_AC20				0x000015d0
3520
#define BCE_EMAC_RX_STAT_AC21				0x000015d4
3521
#define BCE_EMAC_RX_STAT_AC22				0x000015d8
3522
#define BCE_EMAC_RXMAC_SUC_DBG_OVERRUNVEC		0x000015dc
3523
#define BCE_EMAC_TX_STAT_IFHCOUTOCTETS			0x00001600
3524
#define BCE_EMAC_TX_STAT_IFHCOUTBADOCTETS		0x00001604
3525
#define BCE_EMAC_TX_STAT_ETHERSTATSCOLLISIONS		0x00001608
3526
#define BCE_EMAC_TX_STAT_OUTXONSENT			0x0000160c
3527
#define BCE_EMAC_TX_STAT_OUTXOFFSENT			0x00001610
3528
#define BCE_EMAC_TX_STAT_FLOWCONTROLDONE		0x00001614
3529
#define BCE_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES	0x00001618
3530
#define BCE_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES	0x0000161c
3531
#define BCE_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS	0x00001620
3532
#define BCE_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS	0x00001624
3533
#define BCE_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS	0x00001628
3534
#define BCE_EMAC_TX_STAT_IFHCOUTUCASTPKTS		0x0000162c
3535
#define BCE_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS		0x00001630
3536
#define BCE_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS		0x00001634
3537
#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS	0x00001638
3538
#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS	0x0000163c
3539
#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS	0x00001640
3540
#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS	0x00001644
3541
#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS	0x00001648
3542
#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS	0x0000164c
3543
#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS	0x00001650
3544
#define BCE_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS	0x00001654
3545
#define BCE_EMAC_TXMAC_DEBUG0				0x00001658
3546
#define BCE_EMAC_TXMAC_DEBUG1				0x0000165c
3547
#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE		 (0xfL<<0)
3548
#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE		 (0x0L<<0)
3549
#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_START0		 (0x1L<<0)
3550
#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0		 (0x4L<<0)
3551
#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1		 (0x5L<<0)
3552
#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2		 (0x6L<<0)
3553
#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3		 (0x7L<<0)
3554
#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0		 (0x8L<<0)
3555
#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1		 (0x9L<<0)
3556
#define BCE_EMAC_TXMAC_DEBUG1_CRS_ENABLE		 (1L<<4)
3557
#define BCE_EMAC_TXMAC_DEBUG1_BAD_CRC			 (1L<<5)
3558
#define BCE_EMAC_TXMAC_DEBUG1_SE_COUNTER		 (0xfL<<6)
3559
#define BCE_EMAC_TXMAC_DEBUG1_SEND_PAUSE		 (1L<<10)
3560
#define BCE_EMAC_TXMAC_DEBUG1_LATE_COLLISION		 (1L<<11)
3561
#define BCE_EMAC_TXMAC_DEBUG1_MAX_DEFER		 (1L<<12)
3562
#define BCE_EMAC_TXMAC_DEBUG1_DEFERRED			 (1L<<13)
3563
#define BCE_EMAC_TXMAC_DEBUG1_ONE_BYTE			 (1L<<14)
3564
#define BCE_EMAC_TXMAC_DEBUG1_IPG_TIME			 (0xfL<<15)
3565
#define BCE_EMAC_TXMAC_DEBUG1_SLOT_TIME		 (0xffL<<19)
3566

3567
#define BCE_EMAC_TXMAC_DEBUG2				0x00001660
3568
#define BCE_EMAC_TXMAC_DEBUG2_BACK_OFF			 (0x3ffL<<0)
3569
#define BCE_EMAC_TXMAC_DEBUG2_BYTE_COUNT		 (0xffffL<<10)
3570
#define BCE_EMAC_TXMAC_DEBUG2_COL_COUNT		 (0x1fL<<26)
3571
#define BCE_EMAC_TXMAC_DEBUG2_COL_BIT			 (1L<<31)
3572

3573
#define BCE_EMAC_TXMAC_DEBUG3				0x00001664
3574
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE			 (0xfL<<0)
3575
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE		 (0x0L<<0)
3576
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1		 (0x1L<<0)
3577
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2		 (0x2L<<0)
3578
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SFD		 (0x3L<<0)
3579
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_DATA		 (0x4L<<0)
3580
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1		 (0x5L<<0)
3581
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2		 (0x6L<<0)
3582
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EXT		 (0x7L<<0)
3583
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATB		 (0x8L<<0)
3584
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATG		 (0x9L<<0)
3585
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_JAM		 (0xaL<<0)
3586
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM		 (0xbL<<0)
3587
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM		 (0xcL<<0)
3588
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT		 (0xdL<<0)
3589
#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF		 (0xeL<<0)
3590
#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE		 (0x7L<<4)
3591
#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE		 (0x0L<<4)
3592
#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT		 (0x1L<<4)
3593
#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI		 (0x2L<<4)
3594
#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_MC		 (0x3L<<4)
3595
#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2		 (0x4L<<4)
3596
#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3		 (0x5L<<4)
3597
#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC		 (0x6L<<4)
3598
#define BCE_EMAC_TXMAC_DEBUG3_CRS_DONE			 (1L<<7)
3599
#define BCE_EMAC_TXMAC_DEBUG3_XOFF			 (1L<<8)
3600
#define BCE_EMAC_TXMAC_DEBUG3_SE_COUNTER		 (0xfL<<9)
3601
#define BCE_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER		 (0x1fL<<13)
3602

3603
#define BCE_EMAC_TXMAC_DEBUG4				0x00001668
3604
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER		 (0xffffL<<0)
3605
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE		 (0xfL<<16)
3606
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE		 (0x0L<<16)
3607
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1		 (0x2L<<16)
3608
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2		 (0x3L<<16)
3609
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3		 (0x6L<<16)
3610
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1		 (0x7L<<16)
3611
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2		 (0x5L<<16)
3612
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3		 (0x4L<<16)
3613
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE		 (0xcL<<16)
3614
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD		 (0xeL<<16)
3615
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME		 (0xaL<<16)
3616
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1		 (0x8L<<16)
3617
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2		 (0x9L<<16)
3618
#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT		 (0xdL<<16)
3619
#define BCE_EMAC_TXMAC_DEBUG4_STATS0_VALID		 (1L<<20)
3620
#define BCE_EMAC_TXMAC_DEBUG4_APPEND_CRC		 (1L<<21)
3621
#define BCE_EMAC_TXMAC_DEBUG4_SLOT_FILLED		 (1L<<22)
3622
#define BCE_EMAC_TXMAC_DEBUG4_MAX_DEFER		 (1L<<23)
3623
#define BCE_EMAC_TXMAC_DEBUG4_SEND_EXTEND		 (1L<<24)
3624
#define BCE_EMAC_TXMAC_DEBUG4_SEND_PADDING		 (1L<<25)
3625
#define BCE_EMAC_TXMAC_DEBUG4_EOF_LOC			 (1L<<26)
3626
#define BCE_EMAC_TXMAC_DEBUG4_COLLIDING		 (1L<<27)
3627
#define BCE_EMAC_TXMAC_DEBUG4_COL_IN			 (1L<<28)
3628
#define BCE_EMAC_TXMAC_DEBUG4_BURSTING			 (1L<<29)
3629
#define BCE_EMAC_TXMAC_DEBUG4_ADVANCE			 (1L<<30)
3630
#define BCE_EMAC_TXMAC_DEBUG4_GO			 (1L<<31)
3631

3632
#define BCE_EMAC_TX_STAT_AC0				0x00001680
3633
#define BCE_EMAC_TX_STAT_AC1				0x00001684
3634
#define BCE_EMAC_TX_STAT_AC2				0x00001688
3635
#define BCE_EMAC_TX_STAT_AC3				0x0000168c
3636
#define BCE_EMAC_TX_STAT_AC4				0x00001690
3637
#define BCE_EMAC_TX_STAT_AC5				0x00001694
3638
#define BCE_EMAC_TX_STAT_AC6				0x00001698
3639
#define BCE_EMAC_TX_STAT_AC7				0x0000169c
3640
#define BCE_EMAC_TX_STAT_AC8				0x000016a0
3641
#define BCE_EMAC_TX_STAT_AC9				0x000016a4
3642
#define BCE_EMAC_TX_STAT_AC10				0x000016a8
3643
#define BCE_EMAC_TX_STAT_AC11				0x000016ac
3644
#define BCE_EMAC_TX_STAT_AC12				0x000016b0
3645
#define BCE_EMAC_TX_STAT_AC13				0x000016b4
3646
#define BCE_EMAC_TX_STAT_AC14				0x000016b8
3647
#define BCE_EMAC_TX_STAT_AC15				0x000016bc
3648
#define BCE_EMAC_TX_STAT_AC16				0x000016c0
3649
#define BCE_EMAC_TX_STAT_AC17				0x000016c4
3650
#define BCE_EMAC_TX_STAT_AC18				0x000016c8
3651
#define BCE_EMAC_TX_STAT_AC19				0x000016cc
3652
#define BCE_EMAC_TX_STAT_AC20				0x000016d0
3653
#define BCE_EMAC_TX_STAT_AC21				0x000016d4
3654
#define BCE_EMAC_TXMAC_SUC_DBG_OVERRUNVEC		0x000016d8
3655

3656
/*
3657
 *  rpm_reg definition
3658
 *  offset: 0x1800
3659
 */
3660
#define BCE_RPM_COMMAND				0x00001800
3661
#define BCE_RPM_COMMAND_ENABLED			 (1L<<0)
3662
#define BCE_RPM_COMMAND_OVERRUN_ABORT			 (1L<<4)
3663

3664
#define BCE_RPM_STATUS					0x00001804
3665
#define BCE_RPM_STATUS_MBUF_WAIT			 (1L<<0)
3666
#define BCE_RPM_STATUS_FREE_WAIT			 (1L<<1)
3667

3668
#define BCE_RPM_CONFIG					0x00001808
3669
#define BCE_RPM_CONFIG_NO_PSD_HDR_CKSUM		 (1L<<0)
3670
#define BCE_RPM_CONFIG_ACPI_ENA			 (1L<<1)
3671
#define BCE_RPM_CONFIG_ACPI_KEEP			 (1L<<2)
3672
#define BCE_RPM_CONFIG_MP_KEEP				 (1L<<3)
3673
#define BCE_RPM_CONFIG_SORT_VECT_VAL			 (0xfL<<4)
3674
#define BCE_RPM_CONFIG_IGNORE_VLAN			 (1L<<31)
3675

3676
#define BCE_RPM_MGMT_PKT_CTRL					0x0000180c
3677
#define BCE_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN	 (1L<<30)
3678
#define BCE_RPM_MGMT_PKT_CTRL_MGMT_EN   		 (1L<<31)
3679

3680
#define BCE_RPM_VLAN_MATCH0				0x00001810
3681
#define BCE_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE	 (0xfffL<<0)
3682

3683
#define BCE_RPM_VLAN_MATCH1				0x00001814
3684
#define BCE_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE	 (0xfffL<<0)
3685

3686
#define BCE_RPM_VLAN_MATCH2				0x00001818
3687
#define BCE_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE	 (0xfffL<<0)
3688

3689
#define BCE_RPM_VLAN_MATCH3				0x0000181c
3690
#define BCE_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE	 (0xfffL<<0)
3691

3692
#define BCE_RPM_SORT_USER0				0x00001820
3693
#define BCE_RPM_SORT_USER0_PM_EN			 (0xffffL<<0)
3694
#define BCE_RPM_SORT_USER0_BC_EN			 (1L<<16)
3695
#define BCE_RPM_SORT_USER0_MC_EN			 (1L<<17)
3696
#define BCE_RPM_SORT_USER0_MC_HSH_EN			 (1L<<18)
3697
#define BCE_RPM_SORT_USER0_PROM_EN			 (1L<<19)
3698
#define BCE_RPM_SORT_USER0_VLAN_EN			 (0xfL<<20)
3699
#define BCE_RPM_SORT_USER0_PROM_VLAN			 (1L<<24)
3700
#define BCE_RPM_SORT_USER0_ENA				 (1L<<31)
3701

3702
#define BCE_RPM_SORT_USER1				0x00001824
3703
#define BCE_RPM_SORT_USER1_PM_EN			 (0xffffL<<0)
3704
#define BCE_RPM_SORT_USER1_BC_EN			 (1L<<16)
3705
#define BCE_RPM_SORT_USER1_MC_EN			 (1L<<17)
3706
#define BCE_RPM_SORT_USER1_MC_HSH_EN			 (1L<<18)
3707
#define BCE_RPM_SORT_USER1_PROM_EN			 (1L<<19)
3708
#define BCE_RPM_SORT_USER1_VLAN_EN			 (0xfL<<20)
3709
#define BCE_RPM_SORT_USER1_PROM_VLAN			 (1L<<24)
3710
#define BCE_RPM_SORT_USER1_ENA				 (1L<<31)
3711

3712
#define BCE_RPM_SORT_USER2				0x00001828
3713
#define BCE_RPM_SORT_USER2_PM_EN			 (0xffffL<<0)
3714
#define BCE_RPM_SORT_USER2_BC_EN			 (1L<<16)
3715
#define BCE_RPM_SORT_USER2_MC_EN			 (1L<<17)
3716
#define BCE_RPM_SORT_USER2_MC_HSH_EN			 (1L<<18)
3717
#define BCE_RPM_SORT_USER2_PROM_EN			 (1L<<19)
3718
#define BCE_RPM_SORT_USER2_VLAN_EN			 (0xfL<<20)
3719
#define BCE_RPM_SORT_USER2_PROM_VLAN			 (1L<<24)
3720
#define BCE_RPM_SORT_USER2_ENA				 (1L<<31)
3721

3722
#define BCE_RPM_SORT_USER3				0x0000182c
3723
#define BCE_RPM_SORT_USER3_PM_EN			 (0xffffL<<0)
3724
#define BCE_RPM_SORT_USER3_BC_EN			 (1L<<16)
3725
#define BCE_RPM_SORT_USER3_MC_EN			 (1L<<17)
3726
#define BCE_RPM_SORT_USER3_MC_HSH_EN			 (1L<<18)
3727
#define BCE_RPM_SORT_USER3_PROM_EN			 (1L<<19)
3728
#define BCE_RPM_SORT_USER3_VLAN_EN			 (0xfL<<20)
3729
#define BCE_RPM_SORT_USER3_PROM_VLAN			 (1L<<24)
3730
#define BCE_RPM_SORT_USER3_ENA				 (1L<<31)
3731

3732
#define BCE_RPM_STAT_L2_FILTER_DISCARDS		0x00001840
3733
#define BCE_RPM_STAT_RULE_CHECKER_DISCARDS		0x00001844
3734
#define BCE_RPM_STAT_IFINFTQDISCARDS			0x00001848
3735
#define BCE_RPM_STAT_IFINMBUFDISCARD			0x0000184c
3736
#define BCE_RPM_STAT_RULE_CHECKER_P4_HIT		0x00001850
3737
#define BCE_RPM_STAT_AC0				0x00001880
3738
#define BCE_RPM_STAT_AC1				0x00001884
3739
#define BCE_RPM_STAT_AC2				0x00001888
3740
#define BCE_RPM_STAT_AC3				0x0000188c
3741
#define BCE_RPM_STAT_AC4				0x00001890
3742
#define BCE_RPM_RC_CNTL_0				0x00001900
3743
#define BCE_RPM_RC_CNTL_0_OFFSET			 (0xffL<<0)
3744
#define BCE_RPM_RC_CNTL_0_CLASS			 (0x7L<<8)
3745
#define BCE_RPM_RC_CNTL_0_PRIORITY			 (1L<<11)
3746
#define BCE_RPM_RC_CNTL_0_P4				 (1L<<12)
3747
#define BCE_RPM_RC_CNTL_0_HDR_TYPE			 (0x7L<<13)
3748
#define BCE_RPM_RC_CNTL_0_HDR_TYPE_START		 (0L<<13)
3749
#define BCE_RPM_RC_CNTL_0_HDR_TYPE_IP			 (1L<<13)
3750
#define BCE_RPM_RC_CNTL_0_HDR_TYPE_TCP			 (2L<<13)
3751
#define BCE_RPM_RC_CNTL_0_HDR_TYPE_UDP			 (3L<<13)
3752
#define BCE_RPM_RC_CNTL_0_HDR_TYPE_DATA		 (4L<<13)
3753
#define BCE_RPM_RC_CNTL_0_COMP				 (0x3L<<16)
3754
#define BCE_RPM_RC_CNTL_0_COMP_EQUAL			 (0L<<16)
3755
#define BCE_RPM_RC_CNTL_0_COMP_NEQUAL			 (1L<<16)
3756
#define BCE_RPM_RC_CNTL_0_COMP_GREATER			 (2L<<16)
3757
#define BCE_RPM_RC_CNTL_0_COMP_LESS			 (3L<<16)
3758
#define BCE_RPM_RC_CNTL_0_SBIT				 (1L<<19)
3759
#define BCE_RPM_RC_CNTL_0_CMDSEL			 (0xfL<<20)
3760
#define BCE_RPM_RC_CNTL_0_MAP				 (1L<<24)
3761
#define BCE_RPM_RC_CNTL_0_DISCARD			 (1L<<25)
3762
#define BCE_RPM_RC_CNTL_0_MASK				 (1L<<26)
3763
#define BCE_RPM_RC_CNTL_0_P1				 (1L<<27)
3764
#define BCE_RPM_RC_CNTL_0_P2				 (1L<<28)
3765
#define BCE_RPM_RC_CNTL_0_P3				 (1L<<29)
3766
#define BCE_RPM_RC_CNTL_0_NBIT				 (1L<<30)
3767

3768
#define BCE_RPM_RC_VALUE_MASK_0			0x00001904
3769
#define BCE_RPM_RC_VALUE_MASK_0_VALUE			 (0xffffL<<0)
3770
#define BCE_RPM_RC_VALUE_MASK_0_MASK			 (0xffffL<<16)
3771

3772
#define BCE_RPM_RC_CNTL_1				0x00001908
3773
#define BCE_RPM_RC_CNTL_1_A				 (0x3ffffL<<0)
3774
#define BCE_RPM_RC_CNTL_1_B				 (0xfffL<<19)
3775

3776
#define BCE_RPM_RC_VALUE_MASK_1			0x0000190c
3777
#define BCE_RPM_RC_CNTL_2				0x00001910
3778
#define BCE_RPM_RC_CNTL_2_A				 (0x3ffffL<<0)
3779
#define BCE_RPM_RC_CNTL_2_B				 (0xfffL<<19)
3780

3781
#define BCE_RPM_RC_VALUE_MASK_2			0x00001914
3782
#define BCE_RPM_RC_CNTL_3				0x00001918
3783
#define BCE_RPM_RC_CNTL_3_A				 (0x3ffffL<<0)
3784
#define BCE_RPM_RC_CNTL_3_B				 (0xfffL<<19)
3785

3786
#define BCE_RPM_RC_VALUE_MASK_3			0x0000191c
3787
#define BCE_RPM_RC_CNTL_4				0x00001920
3788
#define BCE_RPM_RC_CNTL_4_A				 (0x3ffffL<<0)
3789
#define BCE_RPM_RC_CNTL_4_B				 (0xfffL<<19)
3790

3791
#define BCE_RPM_RC_VALUE_MASK_4			0x00001924
3792
#define BCE_RPM_RC_CNTL_5				0x00001928
3793
#define BCE_RPM_RC_CNTL_5_A				 (0x3ffffL<<0)
3794
#define BCE_RPM_RC_CNTL_5_B				 (0xfffL<<19)
3795

3796
#define BCE_RPM_RC_VALUE_MASK_5			0x0000192c
3797
#define BCE_RPM_RC_CNTL_6				0x00001930
3798
#define BCE_RPM_RC_CNTL_6_A				 (0x3ffffL<<0)
3799
#define BCE_RPM_RC_CNTL_6_B				 (0xfffL<<19)
3800

3801
#define BCE_RPM_RC_VALUE_MASK_6			0x00001934
3802
#define BCE_RPM_RC_CNTL_7				0x00001938
3803
#define BCE_RPM_RC_CNTL_7_A				 (0x3ffffL<<0)
3804
#define BCE_RPM_RC_CNTL_7_B				 (0xfffL<<19)
3805

3806
#define BCE_RPM_RC_VALUE_MASK_7			0x0000193c
3807
#define BCE_RPM_RC_CNTL_8				0x00001940
3808
#define BCE_RPM_RC_CNTL_8_A				 (0x3ffffL<<0)
3809
#define BCE_RPM_RC_CNTL_8_B				 (0xfffL<<19)
3810

3811
#define BCE_RPM_RC_VALUE_MASK_8			0x00001944
3812
#define BCE_RPM_RC_CNTL_9				0x00001948
3813
#define BCE_RPM_RC_CNTL_9_A				 (0x3ffffL<<0)
3814
#define BCE_RPM_RC_CNTL_9_B				 (0xfffL<<19)
3815

3816
#define BCE_RPM_RC_VALUE_MASK_9			0x0000194c
3817
#define BCE_RPM_RC_CNTL_10				0x00001950
3818
#define BCE_RPM_RC_CNTL_10_A				 (0x3ffffL<<0)
3819
#define BCE_RPM_RC_CNTL_10_B				 (0xfffL<<19)
3820

3821
#define BCE_RPM_RC_VALUE_MASK_10			0x00001954
3822
#define BCE_RPM_RC_CNTL_11				0x00001958
3823
#define BCE_RPM_RC_CNTL_11_A				 (0x3ffffL<<0)
3824
#define BCE_RPM_RC_CNTL_11_B				 (0xfffL<<19)
3825

3826
#define BCE_RPM_RC_VALUE_MASK_11			0x0000195c
3827
#define BCE_RPM_RC_CNTL_12				0x00001960
3828
#define BCE_RPM_RC_CNTL_12_A				 (0x3ffffL<<0)
3829
#define BCE_RPM_RC_CNTL_12_B				 (0xfffL<<19)
3830

3831
#define BCE_RPM_RC_VALUE_MASK_12			0x00001964
3832
#define BCE_RPM_RC_CNTL_13				0x00001968
3833
#define BCE_RPM_RC_CNTL_13_A				 (0x3ffffL<<0)
3834
#define BCE_RPM_RC_CNTL_13_B				 (0xfffL<<19)
3835

3836
#define BCE_RPM_RC_VALUE_MASK_13			0x0000196c
3837
#define BCE_RPM_RC_CNTL_14				0x00001970
3838
#define BCE_RPM_RC_CNTL_14_A				 (0x3ffffL<<0)
3839
#define BCE_RPM_RC_CNTL_14_B				 (0xfffL<<19)
3840

3841
#define BCE_RPM_RC_VALUE_MASK_14			0x00001974
3842
#define BCE_RPM_RC_CNTL_15				0x00001978
3843
#define BCE_RPM_RC_CNTL_15_A				 (0x3ffffL<<0)
3844
#define BCE_RPM_RC_CNTL_15_B				 (0xfffL<<19)
3845

3846
#define BCE_RPM_RC_VALUE_MASK_15			0x0000197c
3847
#define BCE_RPM_RC_CONFIG				0x00001980
3848
#define BCE_RPM_RC_CONFIG_RULE_ENABLE			 (0xffffL<<0)
3849
#define BCE_RPM_RC_CONFIG_DEF_CLASS			 (0x7L<<24)
3850

3851
#define BCE_RPM_DEBUG0					0x00001984
3852
#define BCE_RPM_DEBUG0_FM_BCNT				 (0xffffL<<0)
3853
#define BCE_RPM_DEBUG0_T_DATA_OFST_VLD			 (1L<<16)
3854
#define BCE_RPM_DEBUG0_T_UDP_OFST_VLD			 (1L<<17)
3855
#define BCE_RPM_DEBUG0_T_TCP_OFST_VLD			 (1L<<18)
3856
#define BCE_RPM_DEBUG0_T_IP_OFST_VLD			 (1L<<19)
3857
#define BCE_RPM_DEBUG0_IP_MORE_FRGMT			 (1L<<20)
3858
#define BCE_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR		 (1L<<21)
3859
#define BCE_RPM_DEBUG0_LLC_SNAP			 (1L<<22)
3860
#define BCE_RPM_DEBUG0_FM_STARTED			 (1L<<23)
3861
#define BCE_RPM_DEBUG0_DONE				 (1L<<24)
3862
#define BCE_RPM_DEBUG0_WAIT_4_DONE			 (1L<<25)
3863
#define BCE_RPM_DEBUG0_USE_TPBUF_CKSUM			 (1L<<26)
3864
#define BCE_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM		 (1L<<27)
3865
#define BCE_RPM_DEBUG0_IGNORE_VLAN			 (1L<<28)
3866
#define BCE_RPM_DEBUG0_RP_ENA_ACTIVE			 (1L<<31)
3867

3868
#define BCE_RPM_DEBUG1					0x00001988
3869
#define BCE_RPM_DEBUG1_FSM_CUR_ST			 (0xffffL<<0)
3870
#define BCE_RPM_DEBUG1_FSM_CUR_ST_IDLE			 (0L<<0)
3871
#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL		 (1L<<0)
3872
#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC	 (2L<<0)
3873
#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP		 (4L<<0)
3874
#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP		 (8L<<0)
3875
#define BCE_RPM_DEBUG1_FSM_CUR_ST_IP_START		 (16L<<0)
3876
#define BCE_RPM_DEBUG1_FSM_CUR_ST_IP			 (32L<<0)
3877
#define BCE_RPM_DEBUG1_FSM_CUR_ST_TCP			 (64L<<0)
3878
#define BCE_RPM_DEBUG1_FSM_CUR_ST_UDP			 (128L<<0)
3879
#define BCE_RPM_DEBUG1_FSM_CUR_ST_AH			 (256L<<0)
3880
#define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP			 (512L<<0)
3881
#define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD		 (1024L<<0)
3882
#define BCE_RPM_DEBUG1_FSM_CUR_ST_DATA			 (2048L<<0)
3883
#define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY		 (0x2000L<<0)
3884
#define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT		 (0x4000L<<0)
3885
#define BCE_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT		 (0x8000L<<0)
3886
#define BCE_RPM_DEBUG1_HDR_BCNT			 (0x7ffL<<16)
3887
#define BCE_RPM_DEBUG1_UNKNOWN_ETYPE_D			 (1L<<28)
3888
#define BCE_RPM_DEBUG1_VLAN_REMOVED_D2			 (1L<<29)
3889
#define BCE_RPM_DEBUG1_VLAN_REMOVED_D1			 (1L<<30)
3890
#define BCE_RPM_DEBUG1_EOF_0XTRA_WD			 (1L<<31)
3891

3892
#define BCE_RPM_DEBUG2					0x0000198c
3893
#define BCE_RPM_DEBUG2_CMD_HIT_VEC			 (0xffffL<<0)
3894
#define BCE_RPM_DEBUG2_IP_BCNT				 (0xffL<<16)
3895
#define BCE_RPM_DEBUG2_THIS_CMD_M4			 (1L<<24)
3896
#define BCE_RPM_DEBUG2_THIS_CMD_M3			 (1L<<25)
3897
#define BCE_RPM_DEBUG2_THIS_CMD_M2			 (1L<<26)
3898
#define BCE_RPM_DEBUG2_THIS_CMD_M1			 (1L<<27)
3899
#define BCE_RPM_DEBUG2_IPIPE_EMPTY			 (1L<<28)
3900
#define BCE_RPM_DEBUG2_FM_DISCARD			 (1L<<29)
3901
#define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D2		 (1L<<30)
3902
#define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D1		 (1L<<31)
3903

3904
#define BCE_RPM_DEBUG3					0x00001990
3905
#define BCE_RPM_DEBUG3_AVAIL_MBUF_PTR			 (0x1ffL<<0)
3906
#define BCE_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT		 (1L<<9)
3907
#define BCE_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT		 (1L<<10)
3908
#define BCE_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT		 (1L<<11)
3909
#define BCE_RPM_DEBUG3_RDE_RBUF_FREE_REQ		 (1L<<12)
3910
#define BCE_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ		 (1L<<13)
3911
#define BCE_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL		 (1L<<14)
3912
#define BCE_RPM_DEBUG3_RBUF_RDE_SOF_DROP		 (1L<<15)
3913
#define BCE_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT		 (0xfL<<16)
3914
#define BCE_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL		 (1L<<21)
3915
#define BCE_RPM_DEBUG3_DROP_NXT_VLD			 (1L<<22)
3916
#define BCE_RPM_DEBUG3_DROP_NXT			 (1L<<23)
3917
#define BCE_RPM_DEBUG3_FTQ_FSM				 (0x3L<<24)
3918
#define BCE_RPM_DEBUG3_FTQ_FSM_IDLE			 (0x0L<<24)
3919
#define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_ACK		 (0x1L<<24)
3920
#define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_FREE		 (0x2L<<24)
3921
#define BCE_RPM_DEBUG3_MBWRITE_FSM			 (0x3L<<26)
3922
#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF		 (0x0L<<26)
3923
#define BCE_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF		 (0x1L<<26)
3924
#define BCE_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA		 (0x2L<<26)
3925
#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA		 (0x3L<<26)
3926
#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF		 (0x4L<<26)
3927
#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK		 (0x5L<<26)
3928
#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD	 (0x6L<<26)
3929
#define BCE_RPM_DEBUG3_MBWRITE_FSM_DONE		 (0x7L<<26)
3930
#define BCE_RPM_DEBUG3_MBFREE_FSM			 (1L<<29)
3931
#define BCE_RPM_DEBUG3_MBFREE_FSM_IDLE			 (0L<<29)
3932
#define BCE_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK		 (1L<<29)
3933
#define BCE_RPM_DEBUG3_MBALLOC_FSM			 (1L<<30)
3934
#define BCE_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF		 (0x0L<<30)
3935
#define BCE_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF		 (0x1L<<30)
3936
#define BCE_RPM_DEBUG3_CCODE_EOF_ERROR			 (1L<<31)
3937

3938
#define BCE_RPM_DEBUG4					0x00001994
3939
#define BCE_RPM_DEBUG4_DFSM_MBUF_CLUSTER		 (0x1ffffffL<<0)
3940
#define BCE_RPM_DEBUG4_DFIFO_CUR_CCODE			 (0x7L<<25)
3941
#define BCE_RPM_DEBUG4_MBWRITE_FSM			 (0x7L<<28)
3942
#define BCE_RPM_DEBUG4_DFIFO_EMPTY			 (1L<<31)
3943

3944
#define BCE_RPM_DEBUG5					0x00001998
3945
#define BCE_RPM_DEBUG5_RDROP_WPTR			 (0x1fL<<0)
3946
#define BCE_RPM_DEBUG5_RDROP_ACPI_RPTR			 (0x1fL<<5)
3947
#define BCE_RPM_DEBUG5_RDROP_MC_RPTR			 (0x1fL<<10)
3948
#define BCE_RPM_DEBUG5_RDROP_RC_RPTR			 (0x1fL<<15)
3949
#define BCE_RPM_DEBUG5_RDROP_ACPI_EMPTY		 (1L<<20)
3950
#define BCE_RPM_DEBUG5_RDROP_MC_EMPTY			 (1L<<21)
3951
#define BCE_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR	 (1L<<22)
3952
#define BCE_RPM_DEBUG5_HOLDREG_WOL_DROP_INT		 (1L<<23)
3953
#define BCE_RPM_DEBUG5_HOLDREG_DISCARD			 (1L<<24)
3954
#define BCE_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL		 (1L<<25)
3955
#define BCE_RPM_DEBUG5_HOLDREG_MC_EMPTY		 (1L<<26)
3956
#define BCE_RPM_DEBUG5_HOLDREG_RC_EMPTY		 (1L<<27)
3957
#define BCE_RPM_DEBUG5_HOLDREG_FC_EMPTY		 (1L<<28)
3958
#define BCE_RPM_DEBUG5_HOLDREG_ACPI_EMPTY		 (1L<<29)
3959
#define BCE_RPM_DEBUG5_HOLDREG_FULL_T			 (1L<<30)
3960
#define BCE_RPM_DEBUG5_HOLDREG_RD			 (1L<<31)
3961

3962
#define BCE_RPM_DEBUG6					0x0000199c
3963
#define BCE_RPM_DEBUG6_ACPI_VEC			 (0xffffL<<0)
3964
#define BCE_RPM_DEBUG6_VEC				 (0xffffL<<16)
3965

3966
#define BCE_RPM_DEBUG7					0x000019a0
3967
#define BCE_RPM_DEBUG7_RPM_DBG7_LAST_CRC		 (0xffffffffL<<0)
3968

3969
#define BCE_RPM_DEBUG8					0x000019a4
3970
#define BCE_RPM_DEBUG8_PS_ACPI_FSM			 (0xfL<<0)
3971
#define BCE_RPM_DEBUG8_PS_ACPI_FSM_IDLE		 (0L<<0)
3972
#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR		 (1L<<0)
3973
#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR		 (2L<<0)
3974
#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR		 (3L<<0)
3975
#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF	 (4L<<0)
3976
#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA		 (5L<<0)
3977
#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR		 (6L<<0)
3978
#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR		 (7L<<0)
3979
#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR		 (8L<<0)
3980
#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR		 (9L<<0)
3981
#define BCE_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF		 (10L<<0)
3982
#define BCE_RPM_DEBUG8_COMPARE_AT_W0			 (1L<<4)
3983
#define BCE_RPM_DEBUG8_COMPARE_AT_W3_DATA		 (1L<<5)
3984
#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_WAIT		 (1L<<6)
3985
#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W3		 (1L<<7)
3986
#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W2		 (1L<<8)
3987
#define BCE_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES		 (1L<<9)
3988
#define BCE_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES		 (1L<<10)
3989
#define BCE_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES		 (1L<<11)
3990
#define BCE_RPM_DEBUG8_EOF_DET				 (1L<<12)
3991
#define BCE_RPM_DEBUG8_SOF_DET				 (1L<<13)
3992
#define BCE_RPM_DEBUG8_WAIT_4_SOF			 (1L<<14)
3993
#define BCE_RPM_DEBUG8_ALL_DONE			 (1L<<15)
3994
#define BCE_RPM_DEBUG8_THBUF_ADDR			 (0x7fL<<16)
3995
#define BCE_RPM_DEBUG8_BYTE_CTR			 (0xffL<<24)
3996

3997
#define BCE_RPM_DEBUG9					0x000019a8
3998
#define BCE_RPM_DEBUG9_OUTFIFO_COUNT			 (0x7L<<0)
3999
#define BCE_RPM_DEBUG9_RDE_ACPI_RDY			 (1L<<3)
4000
#define BCE_RPM_DEBUG9_VLD_RD_ENTRY_CT			 (0x7L<<4)
4001
#define BCE_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED	 (1L<<28)
4002
#define BCE_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED		 (1L<<29)
4003
#define BCE_RPM_DEBUG9_ACPI_MATCH_INT			 (1L<<30)
4004
#define BCE_RPM_DEBUG9_ACPI_ENABLE_SYN			 (1L<<31)
4005

4006
#define BCE_RPM_ACPI_DBG_BUF_W00			0x000019c0
4007
#define BCE_RPM_ACPI_DBG_BUF_W01			0x000019c4
4008
#define BCE_RPM_ACPI_DBG_BUF_W02			0x000019c8
4009
#define BCE_RPM_ACPI_DBG_BUF_W03			0x000019cc
4010
#define BCE_RPM_ACPI_DBG_BUF_W10			0x000019d0
4011
#define BCE_RPM_ACPI_DBG_BUF_W11			0x000019d4
4012
#define BCE_RPM_ACPI_DBG_BUF_W12			0x000019d8
4013
#define BCE_RPM_ACPI_DBG_BUF_W13			0x000019dc
4014
#define BCE_RPM_ACPI_DBG_BUF_W20			0x000019e0
4015
#define BCE_RPM_ACPI_DBG_BUF_W21			0x000019e4
4016
#define BCE_RPM_ACPI_DBG_BUF_W22			0x000019e8
4017
#define BCE_RPM_ACPI_DBG_BUF_W23			0x000019ec
4018
#define BCE_RPM_ACPI_DBG_BUF_W30			0x000019f0
4019
#define BCE_RPM_ACPI_DBG_BUF_W31			0x000019f4
4020
#define BCE_RPM_ACPI_DBG_BUF_W32			0x000019f8
4021
#define BCE_RPM_ACPI_DBG_BUF_W33			0x000019fc
4022

4023
/*
4024
 *  rlup_reg definition
4025
 *  offset: 0x2000
4026
 */
4027
#define BCE_RLUP_FTQ_CMD					0x000023f8
4028
#define BCE_RLUP_FTQ_CTL					0x000023fc
4029
#define BCE_RLUP_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
4030
#define BCE_RLUP_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
4031

4032
/*
4033
 *  rv2pcsr_reg definition
4034
 *  offset: 0x2400
4035
 */
4036
#define BCE_RV2PCSR_FTQ_CMD					0x000027f8
4037
#define BCE_RV2PCSR_FTQ_CTL					0x000027fc
4038
#define BCE_RV2PCSR_FTQ_CTL_MAX_DEPTH		(0x3ffL<<12)
4039
#define BCE_RV2PCSR_FTQ_CTL_CUR_DEPTH		(0x3ffL<<22)
4040

4041
/*
4042
 *  rdma_reg definition
4043
 *  offset: 0x2c00
4044
 */
4045
#define BCE_RDMA_FTQ_CMD					0x00002ff8
4046
#define BCE_RDMA_FTQ_CTL					0x00002ffc
4047
#define BCE_RDMA_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
4048
#define BCE_RDMA_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
4049

4050
/*
4051
 *  timer_reg definition
4052
 *  offset: 0x4400
4053
 */
4054

4055
#define BCE_TIMER_COMMAND					0x00004400
4056
#define BCE_TIMER_COMMAND_ENABLED			(1L<<0)
4057

4058
#define BCE_TIMER_STATUS					0x00004404
4059
#define BCE_TIMER_STATUS_CMP_FTQ_WAIT 		(1L<<0)
4060
#define BCE_TIMER_STATUS_POLL_PASS_CNT		(1L<<8)
4061
#define BCE_TIMER_STATUS_TMR1_CNT			(1L<<9)
4062
#define BCE_TIMER_STATUS_TMR2_CNT			(1L<<10)
4063
#define BCE_TIMER_STATUS_TMR3_CNT			(1L<<11)
4064
#define BCE_TIMER_STATUS_TMR4_CNT			(1L<<12)
4065
#define BCE_TIMER_STATUS_TMR5_CNT			(1L<<13)
4066

4067
#define BCE_TIMER_25MHZ_FREE_RUN			0x00004448
4068

4069
/*
4070
 *  tsch_reg definition
4071
 *  offset: 0x4c00
4072
 */
4073

4074
#define BCE_TSCH_FTQ_CMD					0x00004ff8
4075
#define BCE_TSCH_FTQ_CTL					0x00004ffc
4076
#define BCE_TSCH_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
4077
#define BCE_TSCH_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
4078

4079
/*
4080
 *  rbuf_reg definition
4081
 *  offset: 0x200000
4082
 */
4083
#define BCE_RBUF_COMMAND				0x00200000
4084
#define BCE_RBUF_COMMAND_ENABLED			 (1L<<0)
4085
#define BCE_RBUF_COMMAND_FREE_INIT			 (1L<<1)
4086
#define BCE_RBUF_COMMAND_RAM_INIT			 (1L<<2)
4087
#define BCE_RBUF_COMMAND_OVER_FREE			 (1L<<4)
4088
#define BCE_RBUF_COMMAND_ALLOC_REQ			 (1L<<5)
4089

4090
#define BCE_RBUF_STATUS1				0x00200004
4091
#define BCE_RBUF_STATUS1_FREE_COUNT			 (0x3ffL<<0)
4092

4093
#define BCE_RBUF_STATUS2				0x00200008
4094
#define BCE_RBUF_STATUS2_FREE_TAIL			 (0x3ffL<<0)
4095
#define BCE_RBUF_STATUS2_FREE_HEAD			 (0x3ffL<<16)
4096

4097
#define BCE_RBUF_CONFIG				0x0020000c
4098
#define BCE_RBUF_CONFIG_XOFF_TRIP			 (0x3ffL<<0)
4099
#define BCE_RBUF_CONFIG_XON_TRIP			 (0x3ffL<<16)
4100

4101
#define BCE_RBUF_FW_BUF_ALLOC				0x00200010
4102
#define BCE_RBUF_FW_BUF_ALLOC_VALUE			 (0x1ffL<<7)
4103

4104
#define BCE_RBUF_FW_BUF_FREE				0x00200014
4105
#define BCE_RBUF_FW_BUF_FREE_COUNT			 (0x7fL<<0)
4106
#define BCE_RBUF_FW_BUF_FREE_TAIL			 (0x1ffL<<7)
4107
#define BCE_RBUF_FW_BUF_FREE_HEAD			 (0x1ffL<<16)
4108

4109
#define BCE_RBUF_FW_BUF_SEL				0x00200018
4110
#define BCE_RBUF_FW_BUF_SEL_COUNT			 (0x7fL<<0)
4111
#define BCE_RBUF_FW_BUF_SEL_TAIL			 (0x1ffL<<7)
4112
#define BCE_RBUF_FW_BUF_SEL_HEAD			 (0x1ffL<<16)
4113

4114
#define BCE_RBUF_CONFIG2				0x0020001c
4115
#define BCE_RBUF_CONFIG2_MAC_DROP_TRIP			 (0x3ffL<<0)
4116
#define BCE_RBUF_CONFIG2_MAC_KEEP_TRIP			 (0x3ffL<<16)
4117

4118
#define BCE_RBUF_CONFIG3				0x00200020
4119
#define BCE_RBUF_CONFIG3_CU_DROP_TRIP			 (0x3ffL<<0)
4120
#define BCE_RBUF_CONFIG3_CU_KEEP_TRIP			 (0x3ffL<<16)
4121

4122
#define BCE_RBUF_PKT_DATA				0x00208000
4123
#define BCE_RBUF_CLIST_DATA				0x00210000
4124
#define BCE_RBUF_BUF_DATA				0x00220000
4125

4126
/*
4127
 *  rv2p_reg definition
4128
 *  offset: 0x2800
4129
 */
4130
#define BCE_RV2P_COMMAND				0x00002800
4131
#define BCE_RV2P_COMMAND_ENABLED			 (1L<<0)
4132
#define BCE_RV2P_COMMAND_PROC1_INTRPT			 (1L<<1)
4133
#define BCE_RV2P_COMMAND_PROC2_INTRPT			 (1L<<2)
4134
#define BCE_RV2P_COMMAND_ABORT0			 (1L<<4)
4135
#define BCE_RV2P_COMMAND_ABORT1			 (1L<<5)
4136
#define BCE_RV2P_COMMAND_ABORT2			 (1L<<6)
4137
#define BCE_RV2P_COMMAND_ABORT3			 (1L<<7)
4138
#define BCE_RV2P_COMMAND_ABORT4			 (1L<<8)
4139
#define BCE_RV2P_COMMAND_ABORT5			 (1L<<9)
4140
#define BCE_RV2P_COMMAND_PROC1_RESET			 (1L<<16)
4141
#define BCE_RV2P_COMMAND_PROC2_RESET			 (1L<<17)
4142
#define BCE_RV2P_COMMAND_CTXIF_RESET			 (1L<<18)
4143

4144
#define BCE_RV2P_STATUS				0x00002804
4145
#define BCE_RV2P_STATUS_ALWAYS_0			 (1L<<0)
4146
#define BCE_RV2P_STATUS_RV2P_GEN_STAT0_CNT		 (1L<<8)
4147
#define BCE_RV2P_STATUS_RV2P_GEN_STAT1_CNT		 (1L<<9)
4148
#define BCE_RV2P_STATUS_RV2P_GEN_STAT2_CNT		 (1L<<10)
4149
#define BCE_RV2P_STATUS_RV2P_GEN_STAT3_CNT		 (1L<<11)
4150
#define BCE_RV2P_STATUS_RV2P_GEN_STAT4_CNT		 (1L<<12)
4151
#define BCE_RV2P_STATUS_RV2P_GEN_STAT5_CNT		 (1L<<13)
4152

4153
#define BCE_RV2P_CONFIG				0x00002808
4154
#define BCE_RV2P_CONFIG_STALL_PROC1			 (1L<<0)
4155
#define BCE_RV2P_CONFIG_STALL_PROC2			 (1L<<1)
4156
#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT0		 (1L<<8)
4157
#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT1		 (1L<<9)
4158
#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT2		 (1L<<10)
4159
#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT3		 (1L<<11)
4160
#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT4		 (1L<<12)
4161
#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT5		 (1L<<13)
4162
#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT0		 (1L<<16)
4163
#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT1		 (1L<<17)
4164
#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT2		 (1L<<18)
4165
#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT3		 (1L<<19)
4166
#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT4		 (1L<<20)
4167
#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT5		 (1L<<21)
4168
#define BCE_RV2P_CONFIG_PAGE_SIZE			 (0xfL<<24)
4169
#define BCE_RV2P_CONFIG_PAGE_SIZE_256			 (0L<<24)
4170
#define BCE_RV2P_CONFIG_PAGE_SIZE_512			 (1L<<24)
4171
#define BCE_RV2P_CONFIG_PAGE_SIZE_1K			 (2L<<24)
4172
#define BCE_RV2P_CONFIG_PAGE_SIZE_2K			 (3L<<24)
4173
#define BCE_RV2P_CONFIG_PAGE_SIZE_4K			 (4L<<24)
4174
#define BCE_RV2P_CONFIG_PAGE_SIZE_8K			 (5L<<24)
4175
#define BCE_RV2P_CONFIG_PAGE_SIZE_16K			 (6L<<24)
4176
#define BCE_RV2P_CONFIG_PAGE_SIZE_32K			 (7L<<24)
4177
#define BCE_RV2P_CONFIG_PAGE_SIZE_64K			 (8L<<24)
4178
#define BCE_RV2P_CONFIG_PAGE_SIZE_128K			 (9L<<24)
4179
#define BCE_RV2P_CONFIG_PAGE_SIZE_256K			 (10L<<24)
4180
#define BCE_RV2P_CONFIG_PAGE_SIZE_512K			 (11L<<24)
4181
#define BCE_RV2P_CONFIG_PAGE_SIZE_1M			 (12L<<24)
4182

4183
#define BCE_RV2P_GEN_BFR_ADDR_0			0x00002810
4184
#define BCE_RV2P_GEN_BFR_ADDR_0_VALUE			 (0xffffL<<16)
4185

4186
#define BCE_RV2P_GEN_BFR_ADDR_1			0x00002814
4187
#define BCE_RV2P_GEN_BFR_ADDR_1_VALUE			 (0xffffL<<16)
4188

4189
#define BCE_RV2P_GEN_BFR_ADDR_2			0x00002818
4190
#define BCE_RV2P_GEN_BFR_ADDR_2_VALUE			 (0xffffL<<16)
4191

4192
#define BCE_RV2P_GEN_BFR_ADDR_3			0x0000281c
4193
#define BCE_RV2P_GEN_BFR_ADDR_3_VALUE			 (0xffffL<<16)
4194

4195
#define BCE_RV2P_INSTR_HIGH				0x00002830
4196
#define BCE_RV2P_INSTR_HIGH_HIGH			 (0x1fL<<0)
4197

4198
#define BCE_RV2P_INSTR_LOW				0x00002834
4199
#define BCE_RV2P_PROC1_ADDR_CMD			0x00002838
4200
#define BCE_RV2P_PROC1_ADDR_CMD_ADD			 (0x3ffL<<0)
4201
#define BCE_RV2P_PROC1_ADDR_CMD_RDWR			 (1L<<31)
4202

4203
#define BCE_RV2P_PROC2_ADDR_CMD			0x0000283c
4204
#define BCE_RV2P_PROC2_ADDR_CMD_ADD			 (0x3ffL<<0)
4205
#define BCE_RV2P_PROC2_ADDR_CMD_RDWR			 (1L<<31)
4206

4207
#define BCE_RV2P_PROC1_GRC_DEBUG			0x00002840
4208
#define BCE_RV2P_PROC2_GRC_DEBUG			0x00002844
4209
#define BCE_RV2P_GRC_PROC_DEBUG			0x00002848
4210
#define BCE_RV2P_DEBUG_VECT_PEEK			0x0000284c
4211
#define BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)
4212
#define BCE_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
4213
#define BCE_RV2P_DEBUG_VECT_PEEK_1_SEL			 (0xfL<<12)
4214
#define BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)
4215
#define BCE_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
4216
#define BCE_RV2P_DEBUG_VECT_PEEK_2_SEL			 (0xfL<<28)
4217

4218
#define BCE_RV2P_PFTQ_DATA				0x00002b40
4219
#define BCE_RV2P_PFTQ_CMD				0x00002b78
4220
#define BCE_RV2P_PFTQ_CMD_OFFSET			 (0x3ffL<<0)
4221
#define BCE_RV2P_PFTQ_CMD_WR_TOP			 (1L<<10)
4222
#define BCE_RV2P_PFTQ_CMD_WR_TOP_0			 (0L<<10)
4223
#define BCE_RV2P_PFTQ_CMD_WR_TOP_1			 (1L<<10)
4224
#define BCE_RV2P_PFTQ_CMD_SFT_RESET			 (1L<<25)
4225
#define BCE_RV2P_PFTQ_CMD_RD_DATA			 (1L<<26)
4226
#define BCE_RV2P_PFTQ_CMD_ADD_INTERVEN			 (1L<<27)
4227
#define BCE_RV2P_PFTQ_CMD_ADD_DATA			 (1L<<28)
4228
#define BCE_RV2P_PFTQ_CMD_INTERVENE_CLR		 (1L<<29)
4229
#define BCE_RV2P_PFTQ_CMD_POP				 (1L<<30)
4230
#define BCE_RV2P_PFTQ_CMD_BUSY				 (1L<<31)
4231

4232
#define BCE_RV2P_PFTQ_CTL				0x00002b7c
4233
#define BCE_RV2P_PFTQ_CTL_INTERVENE			 (1L<<0)
4234
#define BCE_RV2P_PFTQ_CTL_OVERFLOW			 (1L<<1)
4235
#define BCE_RV2P_PFTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4236
#define BCE_RV2P_PFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4237
#define BCE_RV2P_PFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4238

4239
#define BCE_RV2P_TFTQ_DATA				0x00002b80
4240
#define BCE_RV2P_TFTQ_CMD				0x00002bb8
4241
#define BCE_RV2P_TFTQ_CMD_OFFSET			 (0x3ffL<<0)
4242
#define BCE_RV2P_TFTQ_CMD_WR_TOP			 (1L<<10)
4243
#define BCE_RV2P_TFTQ_CMD_WR_TOP_0			 (0L<<10)
4244
#define BCE_RV2P_TFTQ_CMD_WR_TOP_1			 (1L<<10)
4245
#define BCE_RV2P_TFTQ_CMD_SFT_RESET			 (1L<<25)
4246
#define BCE_RV2P_TFTQ_CMD_RD_DATA			 (1L<<26)
4247
#define BCE_RV2P_TFTQ_CMD_ADD_INTERVEN			 (1L<<27)
4248
#define BCE_RV2P_TFTQ_CMD_ADD_DATA			 (1L<<28)
4249
#define BCE_RV2P_TFTQ_CMD_INTERVENE_CLR		 (1L<<29)
4250
#define BCE_RV2P_TFTQ_CMD_POP				 (1L<<30)
4251
#define BCE_RV2P_TFTQ_CMD_BUSY				 (1L<<31)
4252

4253
#define BCE_RV2P_TFTQ_CTL				0x00002bbc
4254
#define BCE_RV2P_TFTQ_CTL_INTERVENE			 (1L<<0)
4255
#define BCE_RV2P_TFTQ_CTL_OVERFLOW			 (1L<<1)
4256
#define BCE_RV2P_TFTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4257
#define BCE_RV2P_TFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4258
#define BCE_RV2P_TFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4259

4260
#define BCE_RV2P_MFTQ_DATA				0x00002bc0
4261
#define BCE_RV2P_MFTQ_CMD				0x00002bf8
4262
#define BCE_RV2P_MFTQ_CMD_OFFSET			 (0x3ffL<<0)
4263
#define BCE_RV2P_MFTQ_CMD_WR_TOP			 (1L<<10)
4264
#define BCE_RV2P_MFTQ_CMD_WR_TOP_0			 (0L<<10)
4265
#define BCE_RV2P_MFTQ_CMD_WR_TOP_1			 (1L<<10)
4266
#define BCE_RV2P_MFTQ_CMD_SFT_RESET			 (1L<<25)
4267
#define BCE_RV2P_MFTQ_CMD_RD_DATA			 (1L<<26)
4268
#define BCE_RV2P_MFTQ_CMD_ADD_INTERVEN			 (1L<<27)
4269
#define BCE_RV2P_MFTQ_CMD_ADD_DATA			 (1L<<28)
4270
#define BCE_RV2P_MFTQ_CMD_INTERVENE_CLR		 (1L<<29)
4271
#define BCE_RV2P_MFTQ_CMD_POP				 (1L<<30)
4272
#define BCE_RV2P_MFTQ_CMD_BUSY				 (1L<<31)
4273

4274
#define BCE_RV2P_MFTQ_CTL				0x00002bfc
4275
#define BCE_RV2P_MFTQ_CTL_INTERVENE			 (1L<<0)
4276
#define BCE_RV2P_MFTQ_CTL_OVERFLOW			 (1L<<1)
4277
#define BCE_RV2P_MFTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4278
#define BCE_RV2P_MFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4279
#define BCE_RV2P_MFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4280

4281
/*
4282
 *  mq_reg definition
4283
 *  offset: 0x3c00
4284
 */
4285
#define BCE_MQ_COMMAND								0x00003c00
4286
#define BCE_MQ_COMMAND_ENABLED						(1L<<0)
4287
#define BCE_MQ_COMMAND_INIT							(1L<<1)
4288
#define BCE_MQ_COMMAND_OVERFLOW						(1L<<4)
4289
#define BCE_MQ_COMMAND_WR_ERROR						(1L<<5)
4290
#define BCE_MQ_COMMAND_RD_ERROR						(1L<<6)
4291
#define BCE_MQ_COMMAND_IDB_CFG_ERROR				(1L<<7)
4292
#define BCE_MQ_COMMAND_IDB_OVERFLOW					(1L<<10)
4293
#define BCE_MQ_COMMAND_NO_BIN_ERROR					(1L<<11)
4294
#define BCE_MQ_COMMAND_NO_MAP_ERROR					(1L<<12)
4295

4296
#define BCE_MQ_STATUS								0x00003c04
4297
#define BCE_MQ_STATUS_CTX_ACCESS_STAT				(1L<<16)
4298
#define BCE_MQ_STATUS_CTX_ACCESS64_STAT				(1L<<17)
4299
#define BCE_MQ_STATUS_PCI_STALL_STAT				(1L<<18)
4300
#define BCE_MQ_STATUS_IDB_OFLOW_STAT				(1L<<19)
4301

4302
#define BCE_MQ_CONFIG								0x00003c08
4303
#define BCE_MQ_CONFIG_TX_HIGH_PRI					(1L<<0)
4304
#define BCE_MQ_CONFIG_HALT_DIS						(1L<<1)
4305
#define BCE_MQ_CONFIG_BIN_MQ_MODE					(1L<<2)
4306
#define BCE_MQ_CONFIG_DIS_IDB_DROP					(1L<<3)
4307
#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE				(0x7L<<4)
4308
#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256			(0L<<4)
4309
#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_512			(1L<<4)
4310
#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K			(2L<<4)
4311
#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K			(3L<<4)
4312
#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K			(4L<<4)
4313
#define BCE_MQ_CONFIG_MAX_DEPTH						(0x7fL<<8)
4314
#define BCE_MQ_CONFIG_CUR_DEPTH						(0x7fL<<20)
4315

4316
#define BCE_MQ_ENQUEUE1								0x00003c0c
4317
#define BCE_MQ_ENQUEUE1_OFFSET						(0x3fL<<2)
4318
#define BCE_MQ_ENQUEUE1_CID							(0x3fffL<<8)
4319
#define BCE_MQ_ENQUEUE1_BYTE_MASK					(0xfL<<24)
4320
#define BCE_MQ_ENQUEUE1_KNL_MODE					(1L<<28)
4321

4322
#define BCE_MQ_ENQUEUE2								0x00003c10
4323
#define BCE_MQ_BAD_WR_ADDR							0x00003c14
4324
#define BCE_MQ_BAD_RD_ADDR							0x00003c18
4325
#define BCE_MQ_KNL_BYP_WIND_START					0x00003c1c
4326
#define BCE_MQ_KNL_BYP_WIND_START_VALUE				(0xfffffL<<12)
4327

4328
#define BCE_MQ_KNL_WIND_END							0x00003c20
4329
#define BCE_MQ_KNL_WIND_END_VALUE					(0xffffffL<<8)
4330

4331
#define BCE_MQ_KNL_WRITE_MASK1						0x00003c24
4332
#define BCE_MQ_KNL_TX_MASK1							0x00003c28
4333
#define BCE_MQ_KNL_CMD_MASK1						0x00003c2c
4334
#define BCE_MQ_KNL_COND_ENQUEUE_MASK1				0x00003c30
4335
#define BCE_MQ_KNL_RX_V2P_MASK1						0x00003c34
4336
#define BCE_MQ_KNL_WRITE_MASK2						0x00003c38
4337
#define BCE_MQ_KNL_TX_MASK2							0x00003c3c
4338
#define BCE_MQ_KNL_CMD_MASK2						0x00003c40
4339
#define BCE_MQ_KNL_COND_ENQUEUE_MASK2				0x00003c44
4340
#define BCE_MQ_KNL_RX_V2P_MASK2						0x00003c48
4341
#define BCE_MQ_KNL_BYP_WRITE_MASK1					0x00003c4c
4342
#define BCE_MQ_KNL_BYP_TX_MASK1						0x00003c50
4343
#define BCE_MQ_KNL_BYP_CMD_MASK1					0x00003c54
4344
#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK1			0x00003c58
4345
#define BCE_MQ_KNL_BYP_RX_V2P_MASK1					0x00003c5c
4346
#define BCE_MQ_KNL_BYP_WRITE_MASK2					0x00003c60
4347
#define BCE_MQ_KNL_BYP_TX_MASK2						0x00003c64
4348
#define BCE_MQ_KNL_BYP_CMD_MASK2					0x00003c68
4349
#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK2			0x00003c6c
4350
#define BCE_MQ_KNL_BYP_RX_V2P_MASK2					0x00003c70
4351
#define BCE_MQ_MEM_WR_ADDR							0x00003c74
4352
#define BCE_MQ_MEM_WR_ADDR_VALUE					(0x3fL<<0)
4353

4354
#define BCE_MQ_MEM_WR_DATA0							0x00003c78
4355
#define BCE_MQ_MEM_WR_DATA0_VALUE					(0xffffffffL<<0)
4356

4357
#define BCE_MQ_MEM_WR_DATA1							0x00003c7c
4358
#define BCE_MQ_MEM_WR_DATA1_VALUE					(0xffffffffL<<0)
4359

4360
#define BCE_MQ_MEM_WR_DATA2							0x00003c80
4361
#define BCE_MQ_MEM_WR_DATA2_VALUE					(0x3fffffffL<<0)
4362
#define BCE_MQ_MEM_WR_DATA2_VALUE_XI				(0x7fffffffL<<0)
4363

4364
#define BCE_MQ_MEM_RD_ADDR							0x00003c84
4365
#define BCE_MQ_MEM_RD_ADDR_VALUE					(0x3fL<<0)
4366

4367
#define BCE_MQ_MEM_RD_DATA0							0x00003c88
4368
#define BCE_MQ_MEM_RD_DATA0_VALUE					(0xffffffffL<<0)
4369

4370
#define BCE_MQ_MEM_RD_DATA1							0x00003c8c
4371
#define BCE_MQ_MEM_RD_DATA1_VALUE					(0xffffffffL<<0)
4372

4373
#define BCE_MQ_MEM_RD_DATA2							0x00003c90
4374
#define BCE_MQ_MEM_RD_DATA2_VALUE					(0x3fffffffL<<0)
4375
#define BCE_MQ_MEM_RD_DATA2_VALUE_XI				(0x7fffffffL<<0)
4376

4377
#define BCE_MQ_CONFIG2								0x00003d00
4378
#define BCE_MQ_CONFIG2_CONT_SZ						(0x7L<<4)
4379
#define BCE_MQ_CONFIG2_FIRST_L4L5					(0x1fL<<8)
4380

4381
#define BCE_MQ_MAP_L2_3								0x00003d2c
4382
#define BCE_MQ_MAP_L2_3_MQ_OFFSET					(0xffL<<0)
4383
#define BCE_MQ_MAP_L2_3_SZ							(0x3L<<8)
4384
#define BCE_MQ_MAP_L2_3_CTX_OFFSET					(0x2ffL<<10)
4385
#define BCE_MQ_MAP_L2_3_BIN_OFFSET					(0x7L<<23)
4386
#define BCE_MQ_MAP_L2_3_ARM							(0x3L<<26)
4387
#define BCE_MQ_MAP_L2_3_ENA							(0x1L<<31)
4388
#define BCE_MQ_MAP_L2_3_DEFAULT						0x82004646
4389

4390
#define BCE_MQ_MAP_L2_5								0x00003d34
4391
#define BCE_MQ_MAP_L2_5_MQ_OFFSET					(0xffL<<0)
4392
#define BCE_MQ_MAP_L2_5_SZ							(0x3L<<8)
4393
#define BCE_MQ_MAP_L2_5_CTX_OFFSET					(0x2ffL<<10)
4394
#define BCE_MQ_MAP_L2_5_BIN_OFFSET					(0x7L<<23)
4395
#define BCE_MQ_MAP_L2_5_ARM							(0x3L<<26)
4396
#define BCE_MQ_MAP_L2_5_ENA							(0x1L<<31)
4397
#define BCE_MQ_MAP_L2_5_DEFAULT						0x83000b08
4398

4399
/*
4400
 *  csch_reg definition
4401
 *  offset: 0x4000
4402
 */
4403
#define BCE_CSCH_COMMAND				0x00004000
4404
#define BCE_CSCH_CH_FTQ_CMD				0x000043f8
4405
#define BCE_CSCH_CH_FTQ_CTL				0x000043fc
4406
#define BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
4407
#define BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
4408

4409
/*
4410
 *  tbdr_reg definition
4411
 *  offset: 0x5000
4412
 */
4413
#define BCE_TBDR_COMMAND				0x00005000
4414
#define BCE_TBDR_COMMAND_ENABLE				(1L<<0)
4415
#define BCE_TBDR_COMMAND_SOFT_RST			(1L<<1)
4416
#define BCE_TBDR_COMMAND_MSTR_ABORT			(1L<<4)
4417

4418
#define BCE_TBDR_STATUS					0x00005004
4419
#define BCE_TBDR_STATUS_DMA_WAIT			(1L<<0)
4420
#define BCE_TBDR_STATUS_FTQ_WAIT			(1L<<1)
4421
#define BCE_TBDR_STATUS_FIFO_OVERFLOW			(1L<<2)
4422
#define BCE_TBDR_STATUS_FIFO_UNDERFLOW			(1L<<3)
4423
#define BCE_TBDR_STATUS_SEARCHMISS_ERROR		(1L<<4)
4424
#define BCE_TBDR_STATUS_FTQ_ENTRY_CNT			(1L<<5)
4425
#define BCE_TBDR_STATUS_BURST_CNT			(1L<<6)
4426

4427
#define BCE_TBDR_CONFIG					0x00005008
4428
#define BCE_TBDR_CONFIG_MAX_BDS				(0xffL<<0)
4429
#define BCE_TBDR_CONFIG_SWAP_MODE			(1L<<8)
4430
#define BCE_TBDR_CONFIG_PRIORITY			(1L<<9)
4431
#define BCE_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS		(1L<<10)
4432
#define BCE_TBDR_CONFIG_PAGE_SIZE			(0xfL<<24)
4433
#define BCE_TBDR_CONFIG_PAGE_SIZE_256			(0L<<24)
4434
#define BCE_TBDR_CONFIG_PAGE_SIZE_512			(1L<<24)
4435
#define BCE_TBDR_CONFIG_PAGE_SIZE_1K			(2L<<24)
4436
#define BCE_TBDR_CONFIG_PAGE_SIZE_2K			(3L<<24)
4437
#define BCE_TBDR_CONFIG_PAGE_SIZE_4K			(4L<<24)
4438
#define BCE_TBDR_CONFIG_PAGE_SIZE_8K			(5L<<24)
4439
#define BCE_TBDR_CONFIG_PAGE_SIZE_16K			(6L<<24)
4440
#define BCE_TBDR_CONFIG_PAGE_SIZE_32K			(7L<<24)
4441
#define BCE_TBDR_CONFIG_PAGE_SIZE_64K			(8L<<24)
4442
#define BCE_TBDR_CONFIG_PAGE_SIZE_128K			(9L<<24)
4443
#define BCE_TBDR_CONFIG_PAGE_SIZE_256K			(10L<<24)
4444
#define BCE_TBDR_CONFIG_PAGE_SIZE_512K			(11L<<24)
4445
#define BCE_TBDR_CONFIG_PAGE_SIZE_1M			(12L<<24)
4446

4447
#define BCE_TBDR_DEBUG_VECT_PEEK			0x0000500c
4448
#define BCE_TBDR_DEBUG_VECT_PEEK_1_VALUE		(0x7ffL<<0)
4449
#define BCE_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN		(1L<<11)
4450
#define BCE_TBDR_DEBUG_VECT_PEEK_1_SEL			(0xfL<<12)
4451
#define BCE_TBDR_DEBUG_VECT_PEEK_2_VALUE		(0x7ffL<<16)
4452
#define BCE_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN		(1L<<27)
4453
#define BCE_TBDR_DEBUG_VECT_PEEK_2_SEL			(0xfL<<28)
4454

4455
#define BCE_TBDR_FTQ_DATA				0x000053c0
4456
#define BCE_TBDR_FTQ_CMD				0x000053f8
4457
#define BCE_TBDR_FTQ_CMD_OFFSET				(0x3ffL<<0)
4458
#define BCE_TBDR_FTQ_CMD_WR_TOP				(1L<<10)
4459
#define BCE_TBDR_FTQ_CMD_WR_TOP_0			(0L<<10)
4460
#define BCE_TBDR_FTQ_CMD_WR_TOP_1			(1L<<10)
4461
#define BCE_TBDR_FTQ_CMD_SFT_RESET			(1L<<25)
4462
#define BCE_TBDR_FTQ_CMD_RD_DATA			(1L<<26)
4463
#define BCE_TBDR_FTQ_CMD_ADD_INTERVEN			(1L<<27)
4464
#define BCE_TBDR_FTQ_CMD_ADD_DATA			(1L<<28)
4465
#define BCE_TBDR_FTQ_CMD_INTERVENE_CLR			(1L<<29)
4466
#define BCE_TBDR_FTQ_CMD_POP				(1L<<30)
4467
#define BCE_TBDR_FTQ_CMD_BUSY				(1L<<31)
4468

4469
#define BCE_TBDR_FTQ_CTL				0x000053fc
4470
#define BCE_TBDR_FTQ_CTL_INTERVENE			(1L<<0)
4471
#define BCE_TBDR_FTQ_CTL_OVERFLOW			(1L<<1)
4472
#define BCE_TBDR_FTQ_CTL_FORCE_INTERVENE		(1L<<2)
4473
#define BCE_TBDR_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
4474
#define BCE_TBDR_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
4475

4476
/*
4477
 *  tdma_reg definition
4478
 *  offset: 0x5c00
4479
 */
4480
#define BCE_TDMA_COMMAND				0x00005c00
4481
#define BCE_TDMA_COMMAND_ENABLED			 (1L<<0)
4482
#define BCE_TDMA_COMMAND_MASTER_ABORT			 (1L<<4)
4483
#define BCE_TDMA_COMMAND_BAD_L2_LENGTH_ABORT		 (1L<<7)
4484

4485
#define BCE_TDMA_STATUS					0x00005c04
4486
#define BCE_TDMA_STATUS_DMA_WAIT			 (1L<<0)
4487
#define BCE_TDMA_STATUS_PAYLOAD_WAIT			 (1L<<1)
4488
#define BCE_TDMA_STATUS_PATCH_FTQ_WAIT			 (1L<<2)
4489
#define BCE_TDMA_STATUS_LOCK_WAIT			 (1L<<3)
4490
#define BCE_TDMA_STATUS_FTQ_ENTRY_CNT			 (1L<<16)
4491
#define BCE_TDMA_STATUS_BURST_CNT			 (1L<<17)
4492

4493
#define BCE_TDMA_CONFIG					0x00005c08
4494
#define BCE_TDMA_CONFIG_ONE_DMA				 (1L<<0)
4495
#define BCE_TDMA_CONFIG_ONE_RECORD			 (1L<<1)
4496
#define BCE_TDMA_CONFIG_LIMIT_SZ			 (0xfL<<4)
4497
#define BCE_TDMA_CONFIG_LIMIT_SZ_64			 (0L<<4)
4498
#define BCE_TDMA_CONFIG_LIMIT_SZ_128			 (0x4L<<4)
4499
#define BCE_TDMA_CONFIG_LIMIT_SZ_256			 (0x6L<<4)
4500
#define BCE_TDMA_CONFIG_LIMIT_SZ_512			 (0x8L<<4)
4501
#define BCE_TDMA_CONFIG_LINE_SZ				 (0xfL<<8)
4502
#define BCE_TDMA_CONFIG_LINE_SZ_64			 (0L<<8)
4503
#define BCE_TDMA_CONFIG_LINE_SZ_128			 (4L<<8)
4504
#define BCE_TDMA_CONFIG_LINE_SZ_256			 (6L<<8)
4505
#define BCE_TDMA_CONFIG_LINE_SZ_512			 (8L<<8)
4506
#define BCE_TDMA_CONFIG_ALIGN_ENA			 (1L<<15)
4507
#define BCE_TDMA_CONFIG_CHK_L2_BD			 (1L<<16)
4508
#define BCE_TDMA_CONFIG_FIFO_CMP			 (0xfL<<20)
4509

4510
#define BCE_TDMA_PAYLOAD_PROD				0x00005c0c
4511
#define BCE_TDMA_PAYLOAD_PROD_VALUE			 (0x1fffL<<3)
4512

4513
#define BCE_TDMA_DBG_WATCHDOG				0x00005c10
4514
#define BCE_TDMA_DBG_TRIGGER				0x00005c14
4515
#define BCE_TDMA_DMAD_FSM				0x00005c80
4516
#define BCE_TDMA_DMAD_FSM_BD_INVLD			 (1L<<0)
4517
#define BCE_TDMA_DMAD_FSM_PUSH				 (0xfL<<4)
4518
#define BCE_TDMA_DMAD_FSM_ARB_TBDC			 (0x3L<<8)
4519
#define BCE_TDMA_DMAD_FSM_ARB_CTX			 (1L<<12)
4520
#define BCE_TDMA_DMAD_FSM_DR_INTF			 (1L<<16)
4521
#define BCE_TDMA_DMAD_FSM_DMAD				 (0x7L<<20)
4522
#define BCE_TDMA_DMAD_FSM_BD				 (0xfL<<24)
4523

4524
#define BCE_TDMA_DMAD_STATUS				0x00005c84
4525
#define BCE_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY		 (0x3L<<0)
4526
#define BCE_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY		 (0x3L<<4)
4527
#define BCE_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY		 (0x3L<<8)
4528
#define BCE_TDMA_DMAD_STATUS_IFTQ_ENUM			 (0xfL<<12)
4529

4530
#define BCE_TDMA_DR_INTF_FSM				0x00005c88
4531
#define BCE_TDMA_DR_INTF_FSM_L2_COMP			 (0x3L<<0)
4532
#define BCE_TDMA_DR_INTF_FSM_TPATQ			 (0x7L<<4)
4533
#define BCE_TDMA_DR_INTF_FSM_TPBUF			 (0x3L<<8)
4534
#define BCE_TDMA_DR_INTF_FSM_DR_BUF			 (0x7L<<12)
4535
#define BCE_TDMA_DR_INTF_FSM_DMAD			 (0x7L<<16)
4536

4537
#define BCE_TDMA_DR_INTF_STATUS				0x00005c8c
4538
#define BCE_TDMA_DR_INTF_STATUS_HOLE_PHASE		 (0x7L<<0)
4539
#define BCE_TDMA_DR_INTF_STATUS_DATA_AVAIL		 (0x3L<<4)
4540
#define BCE_TDMA_DR_INTF_STATUS_SHIFT_ADDR		 (0x7L<<8)
4541
#define BCE_TDMA_DR_INTF_STATUS_NXT_PNTR		 (0xfL<<12)
4542
#define BCE_TDMA_DR_INTF_STATUS_BYTE_COUNT		 (0x7L<<16)
4543

4544
#define BCE_TDMA_FTQ_DATA				0x00005fc0
4545
#define BCE_TDMA_FTQ_CMD				0x00005ff8
4546
#define BCE_TDMA_FTQ_CMD_OFFSET				 (0x3ffL<<0)
4547
#define BCE_TDMA_FTQ_CMD_WR_TOP				 (1L<<10)
4548
#define BCE_TDMA_FTQ_CMD_WR_TOP_0			 (0L<<10)
4549
#define BCE_TDMA_FTQ_CMD_WR_TOP_1			 (1L<<10)
4550
#define BCE_TDMA_FTQ_CMD_SFT_RESET			 (1L<<25)
4551
#define BCE_TDMA_FTQ_CMD_RD_DATA			 (1L<<26)
4552
#define BCE_TDMA_FTQ_CMD_ADD_INTERVEN			 (1L<<27)
4553
#define BCE_TDMA_FTQ_CMD_ADD_DATA			 (1L<<28)
4554
#define BCE_TDMA_FTQ_CMD_INTERVENE_CLR			 (1L<<29)
4555
#define BCE_TDMA_FTQ_CMD_POP				 (1L<<30)
4556
#define BCE_TDMA_FTQ_CMD_BUSY				 (1L<<31)
4557

4558
#define BCE_TDMA_FTQ_CTL				0x00005ffc
4559
#define BCE_TDMA_FTQ_CTL_INTERVENE			 (1L<<0)
4560
#define BCE_TDMA_FTQ_CTL_OVERFLOW			 (1L<<1)
4561
#define BCE_TDMA_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4562
#define BCE_TDMA_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4563
#define BCE_TDMA_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4564

4565
/*
4566
 *  nvm_reg definition
4567
 *  offset: 0x6400
4568
 */
4569
#define BCE_NVM_COMMAND					0x00006400
4570
#define BCE_NVM_COMMAND_RST				 (1L<<0)
4571
#define BCE_NVM_COMMAND_DONE				 (1L<<3)
4572
#define BCE_NVM_COMMAND_DOIT				 (1L<<4)
4573
#define BCE_NVM_COMMAND_WR				 (1L<<5)
4574
#define BCE_NVM_COMMAND_ERASE				 (1L<<6)
4575
#define BCE_NVM_COMMAND_FIRST				 (1L<<7)
4576
#define BCE_NVM_COMMAND_LAST				 (1L<<8)
4577
#define BCE_NVM_COMMAND_WREN				 (1L<<16)
4578
#define BCE_NVM_COMMAND_WRDI				 (1L<<17)
4579
#define BCE_NVM_COMMAND_EWSR				 (1L<<18)
4580
#define BCE_NVM_COMMAND_WRSR				 (1L<<19)
4581

4582
#define BCE_NVM_STATUS					0x00006404
4583
#define BCE_NVM_STATUS_PI_FSM_STATE			 (0xfL<<0)
4584
#define BCE_NVM_STATUS_EE_FSM_STATE			 (0xfL<<4)
4585
#define BCE_NVM_STATUS_EQ_FSM_STATE			 (0xfL<<8)
4586

4587
#define BCE_NVM_WRITE					0x00006408
4588
#define BCE_NVM_WRITE_NVM_WRITE_VALUE			 (0xffffffffL<<0)
4589
#define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG		 (0L<<0)
4590
#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK		 (1L<<0)
4591
#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA		 (2L<<0)
4592
#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK		 (4L<<0)
4593
#define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B		 (8L<<0)
4594
#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO		 (16L<<0)
4595
#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI		 (32L<<0)
4596

4597
#define BCE_NVM_ADDR					0x0000640c
4598
#define BCE_NVM_ADDR_NVM_ADDR_VALUE			 (0xffffffL<<0)
4599
#define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG		 (0L<<0)
4600
#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK		 (1L<<0)
4601
#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA		 (2L<<0)
4602
#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK		 (4L<<0)
4603
#define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B		 (8L<<0)
4604
#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO			 (16L<<0)
4605
#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI			 (32L<<0)
4606

4607
#define BCE_NVM_READ					0x00006410
4608
#define BCE_NVM_READ_NVM_READ_VALUE			 (0xffffffffL<<0)
4609
#define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG		 (0L<<0)
4610
#define BCE_NVM_READ_NVM_READ_VALUE_EECLK		 (1L<<0)
4611
#define BCE_NVM_READ_NVM_READ_VALUE_EEDATA		 (2L<<0)
4612
#define BCE_NVM_READ_NVM_READ_VALUE_SCLK		 (4L<<0)
4613
#define BCE_NVM_READ_NVM_READ_VALUE_CS_B		 (8L<<0)
4614
#define BCE_NVM_READ_NVM_READ_VALUE_SO			 (16L<<0)
4615
#define BCE_NVM_READ_NVM_READ_VALUE_SI			 (32L<<0)
4616

4617
#define BCE_NVM_CFG1					0x00006414
4618
#define BCE_NVM_CFG1_FLASH_MODE				 (1L<<0)
4619
#define BCE_NVM_CFG1_BUFFER_MODE			 (1L<<1)
4620
#define BCE_NVM_CFG1_PASS_MODE				 (1L<<2)
4621
#define BCE_NVM_CFG1_BITBANG_MODE			 (1L<<3)
4622
#define BCE_NVM_CFG1_STATUS_BIT				 (0x7L<<4)
4623
#define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY		 (0L<<4)
4624
#define BCE_NVM_CFG1_STATUS_BIT_BUFFER_RDY		 (7L<<4)
4625
#define BCE_NVM_CFG1_SPI_CLK_DIV			 (0xfL<<7)
4626
#define BCE_NVM_CFG1_SEE_CLK_DIV			 (0x7ffL<<11)
4627
#define BCE_NVM_CFG1_PROTECT_MODE			 (1L<<24)
4628
#define BCE_NVM_CFG1_FLASH_SIZE				 (1L<<25)
4629
#define BCE_NVM_CFG1_COMPAT_BYPASSS			 (1L<<31)
4630

4631
#define BCE_NVM_CFG2					0x00006418
4632
#define BCE_NVM_CFG2_ERASE_CMD				 (0xffL<<0)
4633
#define BCE_NVM_CFG2_DUMMY				 (0xffL<<8)
4634
#define BCE_NVM_CFG2_STATUS_CMD				 (0xffL<<16)
4635

4636
#define BCE_NVM_CFG3					0x0000641c
4637
#define BCE_NVM_CFG3_BUFFER_RD_CMD			 (0xffL<<0)
4638
#define BCE_NVM_CFG3_WRITE_CMD				 (0xffL<<8)
4639
#define BCE_NVM_CFG3_BUFFER_WRITE_CMD			 (0xffL<<16)
4640
#define BCE_NVM_CFG3_READ_CMD				 (0xffL<<24)
4641

4642
#define BCE_NVM_SW_ARB					0x00006420
4643
#define BCE_NVM_SW_ARB_ARB_REQ_SET0			 (1L<<0)
4644
#define BCE_NVM_SW_ARB_ARB_REQ_SET1			 (1L<<1)
4645
#define BCE_NVM_SW_ARB_ARB_REQ_SET2			 (1L<<2)
4646
#define BCE_NVM_SW_ARB_ARB_REQ_SET3			 (1L<<3)
4647
#define BCE_NVM_SW_ARB_ARB_REQ_CLR0			 (1L<<4)
4648
#define BCE_NVM_SW_ARB_ARB_REQ_CLR1			 (1L<<5)
4649
#define BCE_NVM_SW_ARB_ARB_REQ_CLR2			 (1L<<6)
4650
#define BCE_NVM_SW_ARB_ARB_REQ_CLR3			 (1L<<7)
4651
#define BCE_NVM_SW_ARB_ARB_ARB0				 (1L<<8)
4652
#define BCE_NVM_SW_ARB_ARB_ARB1				 (1L<<9)
4653
#define BCE_NVM_SW_ARB_ARB_ARB2				 (1L<<10)
4654
#define BCE_NVM_SW_ARB_ARB_ARB3				 (1L<<11)
4655
#define BCE_NVM_SW_ARB_REQ0				 (1L<<12)
4656
#define BCE_NVM_SW_ARB_REQ1				 (1L<<13)
4657
#define BCE_NVM_SW_ARB_REQ2				 (1L<<14)
4658
#define BCE_NVM_SW_ARB_REQ3				 (1L<<15)
4659

4660
#define BCE_NVM_ACCESS_ENABLE				0x00006424
4661
#define BCE_NVM_ACCESS_ENABLE_EN			 (1L<<0)
4662
#define BCE_NVM_ACCESS_ENABLE_WR_EN			 (1L<<1)
4663

4664
#define BCE_NVM_WRITE1					0x00006428
4665
#define BCE_NVM_WRITE1_WREN_CMD				 (0xffL<<0)
4666
#define BCE_NVM_WRITE1_WRDI_CMD				 (0xffL<<8)
4667
#define BCE_NVM_WRITE1_SR_DATA				 (0xffL<<16)
4668

4669
/*
4670
 *  hc_reg definition
4671
 *  offset: 0x6800
4672
 */
4673
#define BCE_HC_COMMAND					0x00006800
4674
#define BCE_HC_COMMAND_ENABLE				 (1L<<0)
4675
#define BCE_HC_COMMAND_SKIP_ABORT			 (1L<<4)
4676
#define BCE_HC_COMMAND_COAL_NOW			 	 (1L<<16)
4677
#define BCE_HC_COMMAND_COAL_NOW_WO_INT			 (1L<<17)
4678
#define BCE_HC_COMMAND_STATS_NOW			 (1L<<18)
4679
#define BCE_HC_COMMAND_FORCE_INT			 (0x3L<<19)
4680
#define BCE_HC_COMMAND_FORCE_INT_NULL			 (0L<<19)
4681
#define BCE_HC_COMMAND_FORCE_INT_HIGH			 (1L<<19)
4682
#define BCE_HC_COMMAND_FORCE_INT_LOW			 (2L<<19)
4683
#define BCE_HC_COMMAND_FORCE_INT_FREE			 (3L<<19)
4684
#define BCE_HC_COMMAND_CLR_STAT_NOW			 (1L<<21)
4685
#define BCE_HC_COMMAND_MAIN_PWR_INT			 (1L<<22)
4686
#define BCE_HC_COMMAND_COAL_ON_NEXT_EVENT		 (1L<<27)
4687

4688
#define BCE_HC_STATUS					0x00006804
4689
#define BCE_HC_STATUS_MASTER_ABORT			 (1L<<0)
4690
#define BCE_HC_STATUS_PARITY_ERROR_STATE		 (1L<<1)
4691
#define BCE_HC_STATUS_PCI_CLK_CNT_STAT			 (1L<<16)
4692
#define BCE_HC_STATUS_CORE_CLK_CNT_STAT			 (1L<<17)
4693
#define BCE_HC_STATUS_NUM_STATUS_BLOCKS_STAT		 (1L<<18)
4694
#define BCE_HC_STATUS_NUM_INT_GEN_STAT			 (1L<<19)
4695
#define BCE_HC_STATUS_NUM_INT_MBOX_WR_STAT		 (1L<<20)
4696
#define BCE_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT	 (1L<<23)
4697
#define BCE_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT	 (1L<<24)
4698
#define BCE_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT	 (1L<<25)
4699

4700
#define BCE_HC_CONFIG					0x00006808
4701
#define BCE_HC_CONFIG_COLLECT_STATS			 (1L<<0)
4702
#define BCE_HC_CONFIG_RX_TMR_MODE			 (1L<<1)
4703
#define BCE_HC_CONFIG_TX_TMR_MODE			 (1L<<2)
4704
#define BCE_HC_CONFIG_COM_TMR_MODE			 (1L<<3)
4705
#define BCE_HC_CONFIG_CMD_TMR_MODE			 (1L<<4)
4706
#define BCE_HC_CONFIG_STATISTIC_PRIORITY		 (1L<<5)
4707
#define BCE_HC_CONFIG_STATUS_PRIORITY			 (1L<<6)
4708
#define BCE_HC_CONFIG_STAT_MEM_ADDR			 (0xffL<<8)
4709
#define BCE_HC_CONFIG_PER_MODE				 (1L<<16)
4710
#define BCE_HC_CONFIG_ONE_SHOT				 (1L<<17)
4711
#define BCE_HC_CONFIG_USE_INT_PARAM			 (1L<<18)
4712
#define BCE_HC_CONFIG_SET_MASK_AT_RD			 (1L<<19)
4713
#define BCE_HC_CONFIG_PER_COLLECT_LIMIT			 (0xfL<<20)
4714
#define BCE_HC_CONFIG_SB_ADDR_INC			 (0x7L<<24)
4715
#define BCE_HC_CONFIG_SB_ADDR_INC_64B			 (0L<<24)
4716
#define BCE_HC_CONFIG_SB_ADDR_INC_128B			 (1L<<24)
4717
#define BCE_HC_CONFIG_SB_ADDR_INC_256B			 (2L<<24)
4718
#define BCE_HC_CONFIG_SB_ADDR_INC_512B			 (3L<<24)
4719
#define BCE_HC_CONFIG_SB_ADDR_INC_1024B			 (4L<<24)
4720
#define BCE_HC_CONFIG_SB_ADDR_INC_2048B			 (5L<<24)
4721
#define BCE_HC_CONFIG_SB_ADDR_INC_4096B			 (6L<<24)
4722
#define BCE_HC_CONFIG_SB_ADDR_INC_8192B			 (7L<<24)
4723
#define BCE_HC_CONFIG_GEN_STAT_AVG_INTR			 (1L<<29)
4724
#define BCE_HC_CONFIG_UNMASK_ALL			 (1L<<30)
4725
#define BCE_HC_CONFIG_TX_SEL				 (1L<<31)
4726

4727
#define BCE_HC_ATTN_BITS_ENABLE				0x0000680c
4728
#define BCE_HC_STATUS_ADDR_L				0x00006810
4729
#define BCE_HC_STATUS_ADDR_H				0x00006814
4730
#define BCE_HC_STATISTICS_ADDR_L			0x00006818
4731
#define BCE_HC_STATISTICS_ADDR_H			0x0000681c
4732
#define BCE_HC_TX_QUICK_CONS_TRIP			0x00006820
4733
#define BCE_HC_TX_QUICK_CONS_TRIP_VALUE			 (0xffL<<0)
4734
#define BCE_HC_TX_QUICK_CONS_TRIP_INT			 (0xffL<<16)
4735

4736
#define BCE_HC_COMP_PROD_TRIP				0x00006824
4737
#define BCE_HC_COMP_PROD_TRIP_VALUE			 (0xffL<<0)
4738
#define BCE_HC_COMP_PROD_TRIP_INT			 (0xffL<<16)
4739

4740
#define BCE_HC_RX_QUICK_CONS_TRIP			0x00006828
4741
#define BCE_HC_RX_QUICK_CONS_TRIP_VALUE			 (0xffL<<0)
4742
#define BCE_HC_RX_QUICK_CONS_TRIP_INT			 (0xffL<<16)
4743

4744
#define BCE_HC_RX_TICKS					0x0000682c
4745
#define BCE_HC_RX_TICKS_VALUE				 (0x3ffL<<0)
4746
#define BCE_HC_RX_TICKS_INT				 (0x3ffL<<16)
4747

4748
#define BCE_HC_TX_TICKS					0x00006830
4749
#define BCE_HC_TX_TICKS_VALUE				 (0x3ffL<<0)
4750
#define BCE_HC_TX_TICKS_INT				 (0x3ffL<<16)
4751

4752
#define BCE_HC_COM_TICKS				0x00006834
4753
#define BCE_HC_COM_TICKS_VALUE				 (0x3ffL<<0)
4754
#define BCE_HC_COM_TICKS_INT				 (0x3ffL<<16)
4755

4756
#define BCE_HC_CMD_TICKS				0x00006838
4757
#define BCE_HC_CMD_TICKS_VALUE				 (0x3ffL<<0)
4758
#define BCE_HC_CMD_TICKS_INT				 (0x3ffL<<16)
4759

4760
#define BCE_HC_PERIODIC_TICKS				0x0000683c
4761
#define BCE_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS		 (0xffffL<<0)
4762
#define BCE_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
4763

4764
#define BCE_HC_STAT_COLLECT_TICKS			0x00006840
4765
#define BCE_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS	 (0xffL<<4)
4766

4767
#define BCE_HC_STATS_TICKS				0x00006844
4768
#define BCE_HC_STATS_TICKS_HC_STAT_TICKS		 (0xffffL<<8)
4769

4770
#define BCE_HC_STATS_INTERRUPT_STATUS			0x00006848
4771
#define BCE_HC_STATS_INTERRUPT_STATUS_SB_STATUS		 (0x1ffL<<0)
4772
#define BCE_HC_STATS_INTERRUPT_STATUS_INT_STATUS	 (0x1ffL<<16)
4773

4774
#define BCE_HC_STAT_MEM_DATA				0x0000684c
4775
#define BCE_HC_STAT_GEN_SEL_0				0x00006850
4776
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0			 (0x7fL<<0)
4777
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0	 (0L<<0)
4778
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1	 (1L<<0)
4779
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2	 (2L<<0)
4780
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3	 (3L<<0)
4781
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4	 (4L<<0)
4782
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5	 (5L<<0)
4783
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6	 (6L<<0)
4784
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7	 (7L<<0)
4785
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8	 (8L<<0)
4786
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9	 (9L<<0)
4787
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10	 (10L<<0)
4788
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11	 (11L<<0)
4789
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0	 (12L<<0)
4790
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1	 (13L<<0)
4791
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2	 (14L<<0)
4792
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3	 (15L<<0)
4793
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4	 (16L<<0)
4794
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5	 (17L<<0)
4795
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6	 (18L<<0)
4796
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7	 (19L<<0)
4797
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0	 (20L<<0)
4798
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1	 (21L<<0)
4799
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2	 (22L<<0)
4800
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3	 (23L<<0)
4801
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4	 (24L<<0)
4802
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5	 (25L<<0)
4803
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6	 (26L<<0)
4804
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7	 (27L<<0)
4805
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8	 (28L<<0)
4806
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9	 (29L<<0)
4807
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10	 (30L<<0)
4808
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11	 (31L<<0)
4809
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0	 (32L<<0)
4810
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1	 (33L<<0)
4811
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2	 (34L<<0)
4812
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3	 (35L<<0)
4813
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0	 (36L<<0)
4814
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1	 (37L<<0)
4815
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2	 (38L<<0)
4816
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3	 (39L<<0)
4817
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4	 (40L<<0)
4818
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5	 (41L<<0)
4819
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6	 (42L<<0)
4820
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7	 (43L<<0)
4821
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0	 (44L<<0)
4822
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1	 (45L<<0)
4823
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2	 (46L<<0)
4824
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3	 (47L<<0)
4825
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4	 (48L<<0)
4826
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5	 (49L<<0)
4827
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6	 (50L<<0)
4828
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7	 (51L<<0)
4829
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT	 (52L<<0)
4830
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT	 (53L<<0)
4831
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS	 (54L<<0)
4832
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN	 (55L<<0)
4833
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR	 (56L<<0)
4834
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK	 (59L<<0)
4835
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK	 (60L<<0)
4836
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK	 (61L<<0)
4837
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT	 (62L<<0)
4838
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT	 (63L<<0)
4839
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT	 (64L<<0)
4840
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT	 (65L<<0)
4841
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT	 (66L<<0)
4842
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT	 (67L<<0)
4843
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT	 (68L<<0)
4844
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
4845
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
4846
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
4847
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT	 (72L<<0)
4848
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT	 (73L<<0)
4849
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT	 (74L<<0)
4850
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT	 (75L<<0)
4851
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT	 (76L<<0)
4852
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT	 (77L<<0)
4853
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT	 (78L<<0)
4854
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT	 (79L<<0)
4855
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT	 (80L<<0)
4856
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT	 (81L<<0)
4857
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT	 (82L<<0)
4858
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT	 (83L<<0)
4859
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT	 (84L<<0)
4860
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT	 (85L<<0)
4861
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT	 (86L<<0)
4862
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT	 (87L<<0)
4863
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT	 (88L<<0)
4864
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT	 (89L<<0)
4865
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT	 (90L<<0)
4866
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT	 (91L<<0)
4867
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT	 (92L<<0)
4868
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT	 (93L<<0)
4869
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT	 (94L<<0)
4870
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64	 (95L<<0)
4871
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64	 (96L<<0)
4872
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS	 (97L<<0)
4873
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS	 (98L<<0)
4874
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT	 (99L<<0)
4875
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT	 (100L<<0)
4876
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT	 (101L<<0)
4877
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT	 (102L<<0)
4878
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT	 (103L<<0)
4879
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT	 (104L<<0)
4880
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT	 (105L<<0)
4881
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT	 (106L<<0)
4882
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT	 (107L<<0)
4883
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT	 (108L<<0)
4884
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT	 (109L<<0)
4885
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT	 (110L<<0)
4886
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT	 (111L<<0)
4887
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT	 (112L<<0)
4888
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT	 (113L<<0)
4889
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT	 (114L<<0)
4890
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0	 (115L<<0)
4891
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1	 (116L<<0)
4892
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2	 (117L<<0)
4893
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3	 (118L<<0)
4894
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4	 (119L<<0)
4895
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5	 (120L<<0)
4896
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS	 (121L<<0)
4897
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS	 (122L<<0)
4898
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT	 (127L<<0)
4899
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1		 (0x7fL<<8)
4900
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2		 (0x7fL<<16)
4901
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3		 (0x7fL<<24)
4902
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI		 (0xffL<<0)
4903
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI	 (52L<<0)
4904
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI	 (57L<<0)
4905
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI	 (58L<<0)
4906
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI	 (85L<<0)
4907
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI	 (86L<<0)
4908
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI	 (87L<<0)
4909
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI	 (88L<<0)
4910
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI	 (89L<<0)
4911
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI	 (90L<<0)
4912
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI	 (91L<<0)
4913
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI	 (92L<<0)
4914
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI	 (93L<<0)
4915
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI	 (94L<<0)
4916
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI	 (123L<<0)
4917
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI	 (124L<<0)
4918
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI	 (125L<<0)
4919
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI	 (126L<<0)
4920
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI	 (128L<<0)
4921
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI	 (129L<<0)
4922
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI	 (130L<<0)
4923
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI	 (131L<<0)
4924
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI	 (132L<<0)
4925
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI	 (133L<<0)
4926
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI	 (134L<<0)
4927
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI	 (135L<<0)
4928
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI	 (136L<<0)
4929
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI	 (137L<<0)
4930
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI	 (138L<<0)
4931
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI	 (139L<<0)
4932
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI	 (140L<<0)
4933
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI	 (141L<<0)
4934
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI	 (142L<<0)
4935
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI	 (143L<<0)
4936
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI	 (144L<<0)
4937
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI	 (145L<<0)
4938
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI	 (146L<<0)
4939
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI	 (147L<<0)
4940
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI	 (148L<<0)
4941
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI	 (149L<<0)
4942
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI	 (150L<<0)
4943
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI	 (151L<<0)
4944
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI	 (152L<<0)
4945
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI	 (153L<<0)
4946
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI	 (154L<<0)
4947
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI	 (155L<<0)
4948
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI	 (156L<<0)
4949
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI	 (157L<<0)
4950
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI	 (158L<<0)
4951
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI	 (159L<<0)
4952
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI	 (160L<<0)
4953
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI	 (161L<<0)
4954
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI	 (162L<<0)
4955
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI	 (163L<<0)
4956
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI	 (164L<<0)
4957
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI	 (165L<<0)
4958
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI	 (166L<<0)
4959
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI	 (167L<<0)
4960
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI	 (168L<<0)
4961
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI	 (169L<<0)
4962
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI	 (170L<<0)
4963
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI	 (171L<<0)
4964
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI	 (172L<<0)
4965
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI	 (173L<<0)
4966
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI	 (174L<<0)
4967
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI	 (175L<<0)
4968
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI	 (176L<<0)
4969
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI	 (177L<<0)
4970
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI	 (178L<<0)
4971
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI		 (0xffL<<8)
4972
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI		 (0xffL<<16)
4973
#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI		 (0xffL<<24)
4974

4975
#define BCE_HC_STAT_GEN_SEL_1				0x00006854
4976
#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4		 (0x7fL<<0)
4977
#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5		 (0x7fL<<8)
4978
#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6		 (0x7fL<<16)
4979
#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7		 (0x7fL<<24)
4980
#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI		 (0xffL<<0)
4981
#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI		 (0xffL<<8)
4982
#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI		 (0xffL<<16)
4983
#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI		 (0xffL<<24)
4984

4985
#define BCE_HC_STAT_GEN_SEL_2				0x00006858
4986
#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8		 (0x7fL<<0)
4987
#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9		 (0x7fL<<8)
4988
#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10		 (0x7fL<<16)
4989
#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11		 (0x7fL<<24)
4990
#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI		 (0xffL<<0)
4991
#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI		 (0xffL<<8)
4992
#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI		 (0xffL<<16)
4993
#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI		 (0xffL<<24)
4994

4995
#define BCE_HC_STAT_GEN_SEL_3				0x0000685c
4996
#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12		 (0x7fL<<0)
4997
#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13		 (0x7fL<<8)
4998
#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14		 (0x7fL<<16)
4999
#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15		 (0x7fL<<24)
5000
#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI		 (0xffL<<0)
5001
#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI		 (0xffL<<8)
5002
#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI		 (0xffL<<16)
5003
#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI		 (0xffL<<24)
5004

5005
#define BCE_HC_STAT_GEN_STAT0				0x00006888
5006
#define BCE_HC_STAT_GEN_STAT1				0x0000688c
5007
#define BCE_HC_STAT_GEN_STAT2				0x00006890
5008
#define BCE_HC_STAT_GEN_STAT3				0x00006894
5009
#define BCE_HC_STAT_GEN_STAT4				0x00006898
5010
#define BCE_HC_STAT_GEN_STAT5				0x0000689c
5011
#define BCE_HC_STAT_GEN_STAT6				0x000068a0
5012
#define BCE_HC_STAT_GEN_STAT7				0x000068a4
5013
#define BCE_HC_STAT_GEN_STAT8				0x000068a8
5014
#define BCE_HC_STAT_GEN_STAT9				0x000068ac
5015
#define BCE_HC_STAT_GEN_STAT10				0x000068b0
5016
#define BCE_HC_STAT_GEN_STAT11				0x000068b4
5017
#define BCE_HC_STAT_GEN_STAT12				0x000068b8
5018
#define BCE_HC_STAT_GEN_STAT13				0x000068bc
5019
#define BCE_HC_STAT_GEN_STAT14				0x000068c0
5020
#define BCE_HC_STAT_GEN_STAT15				0x000068c4
5021
#define BCE_HC_STAT_GEN_STAT_AC0			0x000068c8
5022
#define BCE_HC_STAT_GEN_STAT_AC1			0x000068cc
5023
#define BCE_HC_STAT_GEN_STAT_AC2			0x000068d0
5024
#define BCE_HC_STAT_GEN_STAT_AC3			0x000068d4
5025
#define BCE_HC_STAT_GEN_STAT_AC4			0x000068d8
5026
#define BCE_HC_STAT_GEN_STAT_AC5			0x000068dc
5027
#define BCE_HC_STAT_GEN_STAT_AC6			0x000068e0
5028
#define BCE_HC_STAT_GEN_STAT_AC7			0x000068e4
5029
#define BCE_HC_STAT_GEN_STAT_AC8			0x000068e8
5030
#define BCE_HC_STAT_GEN_STAT_AC9			0x000068ec
5031
#define BCE_HC_STAT_GEN_STAT_AC10			0x000068f0
5032
#define BCE_HC_STAT_GEN_STAT_AC11			0x000068f4
5033
#define BCE_HC_STAT_GEN_STAT_AC12			0x000068f8
5034
#define BCE_HC_STAT_GEN_STAT_AC13			0x000068fc
5035
#define BCE_HC_STAT_GEN_STAT_AC14			0x00006900
5036
#define BCE_HC_STAT_GEN_STAT_AC15			0x00006904
5037
#define BCE_HC_STAT_GEN_STAT_AC			0x000068c8
5038
#define BCE_HC_VIS					0x00006908
5039
#define BCE_HC_VIS_STAT_BUILD_STATE			 (0xfL<<0)
5040
#define BCE_HC_VIS_STAT_BUILD_STATE_IDLE		 (0L<<0)
5041
#define BCE_HC_VIS_STAT_BUILD_STATE_START		 (1L<<0)
5042
#define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST		 (2L<<0)
5043
#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64		 (3L<<0)
5044
#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32		 (4L<<0)
5045
#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE	 (5L<<0)
5046
#define BCE_HC_VIS_STAT_BUILD_STATE_DMA		 (6L<<0)
5047
#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL	 (7L<<0)
5048
#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_LOW		 (8L<<0)
5049
#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_HIGH		 (9L<<0)
5050
#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_DATA		 (10L<<0)
5051
#define BCE_HC_VIS_DMA_STAT_STATE			 (0xfL<<8)
5052
#define BCE_HC_VIS_DMA_STAT_STATE_IDLE			 (0L<<8)
5053
#define BCE_HC_VIS_DMA_STAT_STATE_STATUS_PARAM		 (1L<<8)
5054
#define BCE_HC_VIS_DMA_STAT_STATE_STATUS_DMA		 (2L<<8)
5055
#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP		 (3L<<8)
5056
#define BCE_HC_VIS_DMA_STAT_STATE_COMP			 (4L<<8)
5057
#define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM	 (5L<<8)
5058
#define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA	 (6L<<8)
5059
#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1		 (7L<<8)
5060
#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2		 (8L<<8)
5061
#define BCE_HC_VIS_DMA_STAT_STATE_WAIT			 (9L<<8)
5062
#define BCE_HC_VIS_DMA_STAT_STATE_ABORT		 (15L<<8)
5063
#define BCE_HC_VIS_DMA_MSI_STATE			 (0x7L<<12)
5064
#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE		 (0x3L<<15)
5065
#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE		 (0L<<15)
5066
#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT	 (1L<<15)
5067
#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_START	 (2L<<15)
5068

5069
#define BCE_HC_VIS_1					0x0000690c
5070
#define BCE_HC_VIS_1_HW_INTACK_STATE			 (1L<<4)
5071
#define BCE_HC_VIS_1_HW_INTACK_STATE_IDLE		 (0L<<4)
5072
#define BCE_HC_VIS_1_HW_INTACK_STATE_COUNT		 (1L<<4)
5073
#define BCE_HC_VIS_1_SW_INTACK_STATE			 (1L<<5)
5074
#define BCE_HC_VIS_1_SW_INTACK_STATE_IDLE		 (0L<<5)
5075
#define BCE_HC_VIS_1_SW_INTACK_STATE_COUNT		 (1L<<5)
5076
#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE		 (1L<<6)
5077
#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE	 (0L<<6)
5078
#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT	 (1L<<6)
5079
#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE		 (1L<<7)
5080
#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE		 (0L<<7)
5081
#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT		 (1L<<7)
5082
#define BCE_HC_VIS_1_RAM_RD_ARB_STATE			 (0xfL<<17)
5083
#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_IDLE		 (0L<<17)
5084
#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_DMA		 (1L<<17)
5085
#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE		 (2L<<17)
5086
#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN		 (3L<<17)
5087
#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_WAIT		 (4L<<17)
5088
#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE	 (5L<<17)
5089
#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN	 (6L<<17)
5090
#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT		 (7L<<17)
5091
#define BCE_HC_VIS_1_RAM_WR_ARB_STATE			 (0x3L<<21)
5092
#define BCE_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL		 (0L<<21)
5093
#define BCE_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR		 (1L<<21)
5094
#define BCE_HC_VIS_1_INT_GEN_STATE			 (1L<<23)
5095
#define BCE_HC_VIS_1_INT_GEN_STATE_DLE			 (0L<<23)
5096
#define BCE_HC_VIS_1_INT_GEN_STATE_NTERRUPT		 (1L<<23)
5097
#define BCE_HC_VIS_1_STAT_CHAN_ID			 (0x7L<<24)
5098
#define BCE_HC_VIS_1_INT_B				 (1L<<27)
5099

5100
#define BCE_HC_DEBUG_VECT_PEEK				0x00006910
5101
#define BCE_HC_DEBUG_VECT_PEEK_1_VALUE			 (0x7ffL<<0)
5102
#define BCE_HC_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
5103
#define BCE_HC_DEBUG_VECT_PEEK_1_SEL			 (0xfL<<12)
5104
#define BCE_HC_DEBUG_VECT_PEEK_2_VALUE			 (0x7ffL<<16)
5105
#define BCE_HC_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
5106
#define BCE_HC_DEBUG_VECT_PEEK_2_SEL			 (0xfL<<28)
5107

5108
#define BCE_HC_COALESCE_NOW				0x00006914
5109
#define BCE_HC_COALESCE_NOW_COAL_NOW			 (0x1ffL<<1)
5110
#define BCE_HC_COALESCE_NOW_COAL_NOW_WO_INT		 (0x1ffL<<11)
5111
#define BCE_HC_COALESCE_NOW_COAL_ON_NXT_EVENT		 (0x1ffL<<21)
5112

5113
#define BCE_HC_MSIX_BIT_VECTOR				0x00006918
5114
#define BCE_HC_MSIX_BIT_VECTOR_VAL			 (0x1ffL<<0)
5115

5116
#define BCE_HC_SB_CONFIG_1				0x00006a00
5117
#define BCE_HC_SB_CONFIG_1_RX_TMR_MODE			 (1L<<1)
5118
#define BCE_HC_SB_CONFIG_1_TX_TMR_MODE			 (1L<<2)
5119
#define BCE_HC_SB_CONFIG_1_COM_TMR_MODE		 (1L<<3)
5120
#define BCE_HC_SB_CONFIG_1_CMD_TMR_MODE		 (1L<<4)
5121
#define BCE_HC_SB_CONFIG_1_PER_MODE			 (1L<<16)
5122
#define BCE_HC_SB_CONFIG_1_ONE_SHOT			 (1L<<17)
5123
#define BCE_HC_SB_CONFIG_1_USE_INT_PARAM		 (1L<<18)
5124
#define BCE_HC_SB_CONFIG_1_PER_COLLECT_LIMIT		 (0xfL<<20)
5125

5126
#define BCE_HC_TX_QUICK_CONS_TRIP_1			0x00006a04
5127
#define BCE_HC_TX_QUICK_CONS_TRIP_1_VALUE		 (0xffL<<0)
5128
#define BCE_HC_TX_QUICK_CONS_TRIP_1_INT		 (0xffL<<16)
5129

5130
#define BCE_HC_COMP_PROD_TRIP_1			0x00006a08
5131
#define BCE_HC_COMP_PROD_TRIP_1_VALUE			 (0xffL<<0)
5132
#define BCE_HC_COMP_PROD_TRIP_1_INT			 (0xffL<<16)
5133

5134
#define BCE_HC_RX_QUICK_CONS_TRIP_1			0x00006a0c
5135
#define BCE_HC_RX_QUICK_CONS_TRIP_1_VALUE		 (0xffL<<0)
5136
#define BCE_HC_RX_QUICK_CONS_TRIP_1_INT		 (0xffL<<16)
5137

5138
#define BCE_HC_RX_TICKS_1				0x00006a10
5139
#define BCE_HC_RX_TICKS_1_VALUE			 (0x3ffL<<0)
5140
#define BCE_HC_RX_TICKS_1_INT				 (0x3ffL<<16)
5141

5142
#define BCE_HC_TX_TICKS_1				0x00006a14
5143
#define BCE_HC_TX_TICKS_1_VALUE			 (0x3ffL<<0)
5144
#define BCE_HC_TX_TICKS_1_INT				 (0x3ffL<<16)
5145

5146
#define BCE_HC_COM_TICKS_1				0x00006a18
5147
#define BCE_HC_COM_TICKS_1_VALUE			 (0x3ffL<<0)
5148
#define BCE_HC_COM_TICKS_1_INT				 (0x3ffL<<16)
5149

5150
#define BCE_HC_CMD_TICKS_1				0x00006a1c
5151
#define BCE_HC_CMD_TICKS_1_VALUE			 (0x3ffL<<0)
5152
#define BCE_HC_CMD_TICKS_1_INT				 (0x3ffL<<16)
5153

5154
#define BCE_HC_PERIODIC_TICKS_1			0x00006a20
5155
#define BCE_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS	 (0xffffL<<0)
5156
#define BCE_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5157

5158
#define BCE_HC_SB_CONFIG_2				0x00006a24
5159
#define BCE_HC_SB_CONFIG_2_RX_TMR_MODE			 (1L<<1)
5160
#define BCE_HC_SB_CONFIG_2_TX_TMR_MODE			 (1L<<2)
5161
#define BCE_HC_SB_CONFIG_2_COM_TMR_MODE		 (1L<<3)
5162
#define BCE_HC_SB_CONFIG_2_CMD_TMR_MODE		 (1L<<4)
5163
#define BCE_HC_SB_CONFIG_2_PER_MODE			 (1L<<16)
5164
#define BCE_HC_SB_CONFIG_2_ONE_SHOT			 (1L<<17)
5165
#define BCE_HC_SB_CONFIG_2_USE_INT_PARAM		 (1L<<18)
5166
#define BCE_HC_SB_CONFIG_2_PER_COLLECT_LIMIT		 (0xfL<<20)
5167

5168
#define BCE_HC_TX_QUICK_CONS_TRIP_2			0x00006a28
5169
#define BCE_HC_TX_QUICK_CONS_TRIP_2_VALUE		 (0xffL<<0)
5170
#define BCE_HC_TX_QUICK_CONS_TRIP_2_INT		 (0xffL<<16)
5171

5172
#define BCE_HC_COMP_PROD_TRIP_2			0x00006a2c
5173
#define BCE_HC_COMP_PROD_TRIP_2_VALUE			 (0xffL<<0)
5174
#define BCE_HC_COMP_PROD_TRIP_2_INT			 (0xffL<<16)
5175

5176
#define BCE_HC_RX_QUICK_CONS_TRIP_2			0x00006a30
5177
#define BCE_HC_RX_QUICK_CONS_TRIP_2_VALUE		 (0xffL<<0)
5178
#define BCE_HC_RX_QUICK_CONS_TRIP_2_INT		 (0xffL<<16)
5179

5180
#define BCE_HC_RX_TICKS_2				0x00006a34
5181
#define BCE_HC_RX_TICKS_2_VALUE			 (0x3ffL<<0)
5182
#define BCE_HC_RX_TICKS_2_INT				 (0x3ffL<<16)
5183

5184
#define BCE_HC_TX_TICKS_2				0x00006a38
5185
#define BCE_HC_TX_TICKS_2_VALUE			 (0x3ffL<<0)
5186
#define BCE_HC_TX_TICKS_2_INT				 (0x3ffL<<16)
5187

5188
#define BCE_HC_COM_TICKS_2				0x00006a3c
5189
#define BCE_HC_COM_TICKS_2_VALUE			 (0x3ffL<<0)
5190
#define BCE_HC_COM_TICKS_2_INT				 (0x3ffL<<16)
5191

5192
#define BCE_HC_CMD_TICKS_2				0x00006a40
5193
#define BCE_HC_CMD_TICKS_2_VALUE			 (0x3ffL<<0)
5194
#define BCE_HC_CMD_TICKS_2_INT				 (0x3ffL<<16)
5195

5196
#define BCE_HC_PERIODIC_TICKS_2			0x00006a44
5197
#define BCE_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS	 (0xffffL<<0)
5198
#define BCE_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5199

5200
#define BCE_HC_SB_CONFIG_3				0x00006a48
5201
#define BCE_HC_SB_CONFIG_3_RX_TMR_MODE			 (1L<<1)
5202
#define BCE_HC_SB_CONFIG_3_TX_TMR_MODE			 (1L<<2)
5203
#define BCE_HC_SB_CONFIG_3_COM_TMR_MODE		 (1L<<3)
5204
#define BCE_HC_SB_CONFIG_3_CMD_TMR_MODE		 (1L<<4)
5205
#define BCE_HC_SB_CONFIG_3_PER_MODE			 (1L<<16)
5206
#define BCE_HC_SB_CONFIG_3_ONE_SHOT			 (1L<<17)
5207
#define BCE_HC_SB_CONFIG_3_USE_INT_PARAM		 (1L<<18)
5208
#define BCE_HC_SB_CONFIG_3_PER_COLLECT_LIMIT		 (0xfL<<20)
5209

5210
#define BCE_HC_TX_QUICK_CONS_TRIP_3			0x00006a4c
5211
#define BCE_HC_TX_QUICK_CONS_TRIP_3_VALUE		 (0xffL<<0)
5212
#define BCE_HC_TX_QUICK_CONS_TRIP_3_INT		 (0xffL<<16)
5213

5214
#define BCE_HC_COMP_PROD_TRIP_3			0x00006a50
5215
#define BCE_HC_COMP_PROD_TRIP_3_VALUE			 (0xffL<<0)
5216
#define BCE_HC_COMP_PROD_TRIP_3_INT			 (0xffL<<16)
5217

5218
#define BCE_HC_RX_QUICK_CONS_TRIP_3			0x00006a54
5219
#define BCE_HC_RX_QUICK_CONS_TRIP_3_VALUE		 (0xffL<<0)
5220
#define BCE_HC_RX_QUICK_CONS_TRIP_3_INT		 (0xffL<<16)
5221

5222
#define BCE_HC_RX_TICKS_3				0x00006a58
5223
#define BCE_HC_RX_TICKS_3_VALUE			 (0x3ffL<<0)
5224
#define BCE_HC_RX_TICKS_3_INT				 (0x3ffL<<16)
5225

5226
#define BCE_HC_TX_TICKS_3				0x00006a5c
5227
#define BCE_HC_TX_TICKS_3_VALUE			 (0x3ffL<<0)
5228
#define BCE_HC_TX_TICKS_3_INT				 (0x3ffL<<16)
5229

5230
#define BCE_HC_COM_TICKS_3				0x00006a60
5231
#define BCE_HC_COM_TICKS_3_VALUE			 (0x3ffL<<0)
5232
#define BCE_HC_COM_TICKS_3_INT				 (0x3ffL<<16)
5233

5234
#define BCE_HC_CMD_TICKS_3				0x00006a64
5235
#define BCE_HC_CMD_TICKS_3_VALUE			 (0x3ffL<<0)
5236
#define BCE_HC_CMD_TICKS_3_INT				 (0x3ffL<<16)
5237

5238
#define BCE_HC_PERIODIC_TICKS_3			0x00006a68
5239
#define BCE_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS	 (0xffffL<<0)
5240
#define BCE_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5241

5242
#define BCE_HC_SB_CONFIG_4				0x00006a6c
5243
#define BCE_HC_SB_CONFIG_4_RX_TMR_MODE			 (1L<<1)
5244
#define BCE_HC_SB_CONFIG_4_TX_TMR_MODE			 (1L<<2)
5245
#define BCE_HC_SB_CONFIG_4_COM_TMR_MODE		 (1L<<3)
5246
#define BCE_HC_SB_CONFIG_4_CMD_TMR_MODE		 (1L<<4)
5247
#define BCE_HC_SB_CONFIG_4_PER_MODE			 (1L<<16)
5248
#define BCE_HC_SB_CONFIG_4_ONE_SHOT			 (1L<<17)
5249
#define BCE_HC_SB_CONFIG_4_USE_INT_PARAM		 (1L<<18)
5250
#define BCE_HC_SB_CONFIG_4_PER_COLLECT_LIMIT		 (0xfL<<20)
5251

5252
#define BCE_HC_TX_QUICK_CONS_TRIP_4			0x00006a70
5253
#define BCE_HC_TX_QUICK_CONS_TRIP_4_VALUE		 (0xffL<<0)
5254
#define BCE_HC_TX_QUICK_CONS_TRIP_4_INT		 (0xffL<<16)
5255

5256
#define BCE_HC_COMP_PROD_TRIP_4			0x00006a74
5257
#define BCE_HC_COMP_PROD_TRIP_4_VALUE			 (0xffL<<0)
5258
#define BCE_HC_COMP_PROD_TRIP_4_INT			 (0xffL<<16)
5259

5260
#define BCE_HC_RX_QUICK_CONS_TRIP_4			0x00006a78
5261
#define BCE_HC_RX_QUICK_CONS_TRIP_4_VALUE		 (0xffL<<0)
5262
#define BCE_HC_RX_QUICK_CONS_TRIP_4_INT		 (0xffL<<16)
5263

5264
#define BCE_HC_RX_TICKS_4				0x00006a7c
5265
#define BCE_HC_RX_TICKS_4_VALUE			 (0x3ffL<<0)
5266
#define BCE_HC_RX_TICKS_4_INT				 (0x3ffL<<16)
5267

5268
#define BCE_HC_TX_TICKS_4				0x00006a80
5269
#define BCE_HC_TX_TICKS_4_VALUE			 (0x3ffL<<0)
5270
#define BCE_HC_TX_TICKS_4_INT				 (0x3ffL<<16)
5271

5272
#define BCE_HC_COM_TICKS_4				0x00006a84
5273
#define BCE_HC_COM_TICKS_4_VALUE			 (0x3ffL<<0)
5274
#define BCE_HC_COM_TICKS_4_INT				 (0x3ffL<<16)
5275

5276
#define BCE_HC_CMD_TICKS_4				0x00006a88
5277
#define BCE_HC_CMD_TICKS_4_VALUE			 (0x3ffL<<0)
5278
#define BCE_HC_CMD_TICKS_4_INT				 (0x3ffL<<16)
5279

5280
#define BCE_HC_PERIODIC_TICKS_4			0x00006a8c
5281
#define BCE_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS	 (0xffffL<<0)
5282
#define BCE_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5283

5284
#define BCE_HC_SB_CONFIG_5				0x00006a90
5285
#define BCE_HC_SB_CONFIG_5_RX_TMR_MODE			 (1L<<1)
5286
#define BCE_HC_SB_CONFIG_5_TX_TMR_MODE			 (1L<<2)
5287
#define BCE_HC_SB_CONFIG_5_COM_TMR_MODE		 (1L<<3)
5288
#define BCE_HC_SB_CONFIG_5_CMD_TMR_MODE		 (1L<<4)
5289
#define BCE_HC_SB_CONFIG_5_PER_MODE			 (1L<<16)
5290
#define BCE_HC_SB_CONFIG_5_ONE_SHOT			 (1L<<17)
5291
#define BCE_HC_SB_CONFIG_5_USE_INT_PARAM		 (1L<<18)
5292
#define BCE_HC_SB_CONFIG_5_PER_COLLECT_LIMIT		 (0xfL<<20)
5293

5294
#define BCE_HC_TX_QUICK_CONS_TRIP_5			0x00006a94
5295
#define BCE_HC_TX_QUICK_CONS_TRIP_5_VALUE		 (0xffL<<0)
5296
#define BCE_HC_TX_QUICK_CONS_TRIP_5_INT		 (0xffL<<16)
5297

5298
#define BCE_HC_COMP_PROD_TRIP_5			0x00006a98
5299
#define BCE_HC_COMP_PROD_TRIP_5_VALUE			 (0xffL<<0)
5300
#define BCE_HC_COMP_PROD_TRIP_5_INT			 (0xffL<<16)
5301

5302
#define BCE_HC_RX_QUICK_CONS_TRIP_5			0x00006a9c
5303
#define BCE_HC_RX_QUICK_CONS_TRIP_5_VALUE		 (0xffL<<0)
5304
#define BCE_HC_RX_QUICK_CONS_TRIP_5_INT		 (0xffL<<16)
5305

5306
#define BCE_HC_RX_TICKS_5				0x00006aa0
5307
#define BCE_HC_RX_TICKS_5_VALUE			 (0x3ffL<<0)
5308
#define BCE_HC_RX_TICKS_5_INT				 (0x3ffL<<16)
5309

5310
#define BCE_HC_TX_TICKS_5				0x00006aa4
5311
#define BCE_HC_TX_TICKS_5_VALUE			 (0x3ffL<<0)
5312
#define BCE_HC_TX_TICKS_5_INT				 (0x3ffL<<16)
5313

5314
#define BCE_HC_COM_TICKS_5				0x00006aa8
5315
#define BCE_HC_COM_TICKS_5_VALUE			 (0x3ffL<<0)
5316
#define BCE_HC_COM_TICKS_5_INT				 (0x3ffL<<16)
5317

5318
#define BCE_HC_CMD_TICKS_5				0x00006aac
5319
#define BCE_HC_CMD_TICKS_5_VALUE			 (0x3ffL<<0)
5320
#define BCE_HC_CMD_TICKS_5_INT				 (0x3ffL<<16)
5321

5322
#define BCE_HC_PERIODIC_TICKS_5			0x00006ab0
5323
#define BCE_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS	 (0xffffL<<0)
5324
#define BCE_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5325

5326
#define BCE_HC_SB_CONFIG_6				0x00006ab4
5327
#define BCE_HC_SB_CONFIG_6_RX_TMR_MODE			 (1L<<1)
5328
#define BCE_HC_SB_CONFIG_6_TX_TMR_MODE			 (1L<<2)
5329
#define BCE_HC_SB_CONFIG_6_COM_TMR_MODE		 (1L<<3)
5330
#define BCE_HC_SB_CONFIG_6_CMD_TMR_MODE		 (1L<<4)
5331
#define BCE_HC_SB_CONFIG_6_PER_MODE			 (1L<<16)
5332
#define BCE_HC_SB_CONFIG_6_ONE_SHOT			 (1L<<17)
5333
#define BCE_HC_SB_CONFIG_6_USE_INT_PARAM		 (1L<<18)
5334
#define BCE_HC_SB_CONFIG_6_PER_COLLECT_LIMIT		 (0xfL<<20)
5335

5336
#define BCE_HC_TX_QUICK_CONS_TRIP_6			0x00006ab8
5337
#define BCE_HC_TX_QUICK_CONS_TRIP_6_VALUE		 (0xffL<<0)
5338
#define BCE_HC_TX_QUICK_CONS_TRIP_6_INT		 (0xffL<<16)
5339

5340
#define BCE_HC_COMP_PROD_TRIP_6			0x00006abc
5341
#define BCE_HC_COMP_PROD_TRIP_6_VALUE			 (0xffL<<0)
5342
#define BCE_HC_COMP_PROD_TRIP_6_INT			 (0xffL<<16)
5343

5344
#define BCE_HC_RX_QUICK_CONS_TRIP_6			0x00006ac0
5345
#define BCE_HC_RX_QUICK_CONS_TRIP_6_VALUE		 (0xffL<<0)
5346
#define BCE_HC_RX_QUICK_CONS_TRIP_6_INT		 (0xffL<<16)
5347

5348
#define BCE_HC_RX_TICKS_6				0x00006ac4
5349
#define BCE_HC_RX_TICKS_6_VALUE			 (0x3ffL<<0)
5350
#define BCE_HC_RX_TICKS_6_INT				 (0x3ffL<<16)
5351

5352
#define BCE_HC_TX_TICKS_6				0x00006ac8
5353
#define BCE_HC_TX_TICKS_6_VALUE			 (0x3ffL<<0)
5354
#define BCE_HC_TX_TICKS_6_INT				 (0x3ffL<<16)
5355

5356
#define BCE_HC_COM_TICKS_6				0x00006acc
5357
#define BCE_HC_COM_TICKS_6_VALUE			 (0x3ffL<<0)
5358
#define BCE_HC_COM_TICKS_6_INT				 (0x3ffL<<16)
5359

5360
#define BCE_HC_CMD_TICKS_6				0x00006ad0
5361
#define BCE_HC_CMD_TICKS_6_VALUE			 (0x3ffL<<0)
5362
#define BCE_HC_CMD_TICKS_6_INT				 (0x3ffL<<16)
5363

5364
#define BCE_HC_PERIODIC_TICKS_6			0x00006ad4
5365
#define BCE_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS	 (0xffffL<<0)
5366
#define BCE_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5367

5368
#define BCE_HC_SB_CONFIG_7				0x00006ad8
5369
#define BCE_HC_SB_CONFIG_7_RX_TMR_MODE			 (1L<<1)
5370
#define BCE_HC_SB_CONFIG_7_TX_TMR_MODE			 (1L<<2)
5371
#define BCE_HC_SB_CONFIG_7_COM_TMR_MODE		 (1L<<3)
5372
#define BCE_HC_SB_CONFIG_7_CMD_TMR_MODE		 (1L<<4)
5373
#define BCE_HC_SB_CONFIG_7_PER_MODE			 (1L<<16)
5374
#define BCE_HC_SB_CONFIG_7_ONE_SHOT			 (1L<<17)
5375
#define BCE_HC_SB_CONFIG_7_USE_INT_PARAM		 (1L<<18)
5376
#define BCE_HC_SB_CONFIG_7_PER_COLLECT_LIMIT		 (0xfL<<20)
5377

5378
#define BCE_HC_TX_QUICK_CONS_TRIP_7			0x00006adc
5379
#define BCE_HC_TX_QUICK_CONS_TRIP_7_VALUE		 (0xffL<<0)
5380
#define BCE_HC_TX_QUICK_CONS_TRIP_7_INT		 (0xffL<<16)
5381

5382
#define BCE_HC_COMP_PROD_TRIP_7			0x00006ae0
5383
#define BCE_HC_COMP_PROD_TRIP_7_VALUE			 (0xffL<<0)
5384
#define BCE_HC_COMP_PROD_TRIP_7_INT			 (0xffL<<16)
5385

5386
#define BCE_HC_RX_QUICK_CONS_TRIP_7			0x00006ae4
5387
#define BCE_HC_RX_QUICK_CONS_TRIP_7_VALUE		 (0xffL<<0)
5388
#define BCE_HC_RX_QUICK_CONS_TRIP_7_INT		 (0xffL<<16)
5389

5390
#define BCE_HC_RX_TICKS_7				0x00006ae8
5391
#define BCE_HC_RX_TICKS_7_VALUE			 (0x3ffL<<0)
5392
#define BCE_HC_RX_TICKS_7_INT				 (0x3ffL<<16)
5393

5394
#define BCE_HC_TX_TICKS_7				0x00006aec
5395
#define BCE_HC_TX_TICKS_7_VALUE			 (0x3ffL<<0)
5396
#define BCE_HC_TX_TICKS_7_INT				 (0x3ffL<<16)
5397

5398
#define BCE_HC_COM_TICKS_7				0x00006af0
5399
#define BCE_HC_COM_TICKS_7_VALUE			 (0x3ffL<<0)
5400
#define BCE_HC_COM_TICKS_7_INT				 (0x3ffL<<16)
5401

5402
#define BCE_HC_CMD_TICKS_7				0x00006af4
5403
#define BCE_HC_CMD_TICKS_7_VALUE			 (0x3ffL<<0)
5404
#define BCE_HC_CMD_TICKS_7_INT				 (0x3ffL<<16)
5405

5406
#define BCE_HC_PERIODIC_TICKS_7			0x00006af8
5407
#define BCE_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS	 (0xffffL<<0)
5408
#define BCE_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5409

5410
#define BCE_HC_SB_CONFIG_8				0x00006afc
5411
#define BCE_HC_SB_CONFIG_8_RX_TMR_MODE			 (1L<<1)
5412
#define BCE_HC_SB_CONFIG_8_TX_TMR_MODE			 (1L<<2)
5413
#define BCE_HC_SB_CONFIG_8_COM_TMR_MODE		 (1L<<3)
5414
#define BCE_HC_SB_CONFIG_8_CMD_TMR_MODE		 (1L<<4)
5415
#define BCE_HC_SB_CONFIG_8_PER_MODE			 (1L<<16)
5416
#define BCE_HC_SB_CONFIG_8_ONE_SHOT			 (1L<<17)
5417
#define BCE_HC_SB_CONFIG_8_USE_INT_PARAM		 (1L<<18)
5418
#define BCE_HC_SB_CONFIG_8_PER_COLLECT_LIMIT		 (0xfL<<20)
5419

5420
#define BCE_HC_TX_QUICK_CONS_TRIP_8			0x00006b00
5421
#define BCE_HC_TX_QUICK_CONS_TRIP_8_VALUE		 (0xffL<<0)
5422
#define BCE_HC_TX_QUICK_CONS_TRIP_8_INT		 (0xffL<<16)
5423

5424
#define BCE_HC_COMP_PROD_TRIP_8			0x00006b04
5425
#define BCE_HC_COMP_PROD_TRIP_8_VALUE			 (0xffL<<0)
5426
#define BCE_HC_COMP_PROD_TRIP_8_INT			 (0xffL<<16)
5427

5428
#define BCE_HC_RX_QUICK_CONS_TRIP_8			0x00006b08
5429
#define BCE_HC_RX_QUICK_CONS_TRIP_8_VALUE		 (0xffL<<0)
5430
#define BCE_HC_RX_QUICK_CONS_TRIP_8_INT		 (0xffL<<16)
5431

5432
#define BCE_HC_RX_TICKS_8				0x00006b0c
5433
#define BCE_HC_RX_TICKS_8_VALUE			 (0x3ffL<<0)
5434
#define BCE_HC_RX_TICKS_8_INT				 (0x3ffL<<16)
5435

5436
#define BCE_HC_TX_TICKS_8				0x00006b10
5437
#define BCE_HC_TX_TICKS_8_VALUE			 (0x3ffL<<0)
5438
#define BCE_HC_TX_TICKS_8_INT				 (0x3ffL<<16)
5439

5440
#define BCE_HC_COM_TICKS_8				0x00006b14
5441
#define BCE_HC_COM_TICKS_8_VALUE			 (0x3ffL<<0)
5442
#define BCE_HC_COM_TICKS_8_INT				 (0x3ffL<<16)
5443

5444
#define BCE_HC_CMD_TICKS_8				0x00006b18
5445
#define BCE_HC_CMD_TICKS_8_VALUE			 (0x3ffL<<0)
5446
#define BCE_HC_CMD_TICKS_8_INT				 (0x3ffL<<16)
5447

5448
#define BCE_HC_PERIODIC_TICKS_8			0x00006b1c
5449
#define BCE_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS	 (0xffffL<<0)
5450
#define BCE_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5451

5452
/*
5453
 *  txp_reg definition
5454
 *  offset: 0x40000
5455
 */
5456
#define BCE_TXP_CPU_MODE				0x00045000
5457
#define BCE_TXP_CPU_MODE_LOCAL_RST			 (1L<<0)
5458
#define BCE_TXP_CPU_MODE_STEP_ENA			 (1L<<1)
5459
#define BCE_TXP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
5460
#define BCE_TXP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
5461
#define BCE_TXP_CPU_MODE_MSG_BIT1			 (1L<<6)
5462
#define BCE_TXP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
5463
#define BCE_TXP_CPU_MODE_SOFT_HALT			 (1L<<10)
5464
#define BCE_TXP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
5465
#define BCE_TXP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
5466
#define BCE_TXP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
5467
#define BCE_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
5468

5469
#define BCE_TXP_CPU_STATE				0x00045004
5470
#define BCE_TXP_CPU_STATE_BREAKPOINT			 (1L<<0)
5471
#define BCE_TXP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
5472
#define BCE_TXP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
5473
#define BCE_TXP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
5474
#define BCE_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
5475
#define BCE_TXP_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
5476
#define BCE_TXP_CPU_STATE_ALIGN_HALTED			 (1L<<7)
5477
#define BCE_TXP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
5478
#define BCE_TXP_CPU_STATE_SOFT_HALTED			 (1L<<10)
5479
#define BCE_TXP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
5480
#define BCE_TXP_CPU_STATE_INTERRRUPT			 (1L<<12)
5481
#define BCE_TXP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
5482
#define BCE_TXP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
5483
#define BCE_TXP_CPU_STATE_BLOCKED_READ			 (1L<<31)
5484

5485
#define BCE_TXP_CPU_EVENT_MASK				0x00045008
5486
#define BCE_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
5487
#define BCE_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
5488
#define BCE_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
5489
#define BCE_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
5490
#define BCE_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
5491
#define BCE_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
5492
#define BCE_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
5493
#define BCE_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
5494
#define BCE_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
5495
#define BCE_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
5496
#define BCE_TXP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
5497

5498
#define BCE_TXP_CPU_PROGRAM_COUNTER			0x0004501c
5499
#define BCE_TXP_CPU_INSTRUCTION			0x00045020
5500
#define BCE_TXP_CPU_DATA_ACCESS			0x00045024
5501
#define BCE_TXP_CPU_INTERRUPT_ENABLE			0x00045028
5502
#define BCE_TXP_CPU_INTERRUPT_VECTOR			0x0004502c
5503
#define BCE_TXP_CPU_INTERRUPT_SAVED_PC			0x00045030
5504
#define BCE_TXP_CPU_HW_BREAKPOINT			0x00045034
5505
#define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
5506
#define BCE_TXP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
5507

5508
#define BCE_TXP_CPU_REG_FILE				0x00045200
5509
#define BCE_TXP_FTQ_DATA				0x000453c0
5510
#define BCE_TXP_FTQ_CMD				0x000453f8
5511
#define BCE_TXP_FTQ_CMD_OFFSET				 (0x3ffL<<0)
5512
#define BCE_TXP_FTQ_CMD_WR_TOP				 (1L<<10)
5513
#define BCE_TXP_FTQ_CMD_WR_TOP_0			 (0L<<10)
5514
#define BCE_TXP_FTQ_CMD_WR_TOP_1			 (1L<<10)
5515
#define BCE_TXP_FTQ_CMD_SFT_RESET			 (1L<<25)
5516
#define BCE_TXP_FTQ_CMD_RD_DATA			 (1L<<26)
5517
#define BCE_TXP_FTQ_CMD_ADD_INTERVEN			 (1L<<27)
5518
#define BCE_TXP_FTQ_CMD_ADD_DATA			 (1L<<28)
5519
#define BCE_TXP_FTQ_CMD_INTERVENE_CLR			 (1L<<29)
5520
#define BCE_TXP_FTQ_CMD_POP				 (1L<<30)
5521
#define BCE_TXP_FTQ_CMD_BUSY				 (1L<<31)
5522

5523
#define BCE_TXP_FTQ_CTL				0x000453fc
5524
#define BCE_TXP_FTQ_CTL_INTERVENE			 (1L<<0)
5525
#define BCE_TXP_FTQ_CTL_OVERFLOW			 (1L<<1)
5526
#define BCE_TXP_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
5527
#define BCE_TXP_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
5528
#define BCE_TXP_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
5529

5530
#define BCE_TXP_SCRATCH				0x00060000
5531

5532
/*
5533
 *  tpat_reg definition
5534
 *  offset: 0x80000
5535
 */
5536
#define BCE_TPAT_CPU_MODE				0x00085000
5537
#define BCE_TPAT_CPU_MODE_LOCAL_RST			 (1L<<0)
5538
#define BCE_TPAT_CPU_MODE_STEP_ENA			 (1L<<1)
5539
#define BCE_TPAT_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
5540
#define BCE_TPAT_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
5541
#define BCE_TPAT_CPU_MODE_MSG_BIT1			 (1L<<6)
5542
#define BCE_TPAT_CPU_MODE_INTERRUPT_ENA		 (1L<<7)
5543
#define BCE_TPAT_CPU_MODE_SOFT_HALT			 (1L<<10)
5544
#define BCE_TPAT_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
5545
#define BCE_TPAT_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
5546
#define BCE_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
5547
#define BCE_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
5548

5549
#define BCE_TPAT_CPU_STATE				0x00085004
5550
#define BCE_TPAT_CPU_STATE_BREAKPOINT			 (1L<<0)
5551
#define BCE_TPAT_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
5552
#define BCE_TPAT_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
5553
#define BCE_TPAT_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
5554
#define BCE_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED	 (1L<<5)
5555
#define BCE_TPAT_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
5556
#define BCE_TPAT_CPU_STATE_ALIGN_HALTED		 (1L<<7)
5557
#define BCE_TPAT_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
5558
#define BCE_TPAT_CPU_STATE_SOFT_HALTED			 (1L<<10)
5559
#define BCE_TPAT_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
5560
#define BCE_TPAT_CPU_STATE_INTERRRUPT			 (1L<<12)
5561
#define BCE_TPAT_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
5562
#define BCE_TPAT_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
5563
#define BCE_TPAT_CPU_STATE_BLOCKED_READ		 (1L<<31)
5564

5565
#define BCE_TPAT_CPU_EVENT_MASK			0x00085008
5566
#define BCE_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK	 (1L<<0)
5567
#define BCE_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
5568
#define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
5569
#define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
5570
#define BCE_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
5571
#define BCE_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
5572
#define BCE_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
5573
#define BCE_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
5574
#define BCE_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
5575
#define BCE_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
5576
#define BCE_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
5577

5578
#define BCE_TPAT_CPU_PROGRAM_COUNTER			0x0008501c
5579
#define BCE_TPAT_CPU_INSTRUCTION			0x00085020
5580
#define BCE_TPAT_CPU_DATA_ACCESS			0x00085024
5581
#define BCE_TPAT_CPU_INTERRUPT_ENABLE			0x00085028
5582
#define BCE_TPAT_CPU_INTERRUPT_VECTOR			0x0008502c
5583
#define BCE_TPAT_CPU_INTERRUPT_SAVED_PC		0x00085030
5584
#define BCE_TPAT_CPU_HW_BREAKPOINT			0x00085034
5585
#define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
5586
#define BCE_TPAT_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
5587
#define BCE_TPAT_CPU_REG_FILE				0x00085200
5588
#define BCE_TPAT_FTQ_DATA				0x000853c0
5589
#define BCE_TPAT_FTQ_CMD				0x000853f8
5590
#define BCE_TPAT_FTQ_CMD_OFFSET			 (0x3ffL<<0)
5591
#define BCE_TPAT_FTQ_CMD_WR_TOP			 (1L<<10)
5592
#define BCE_TPAT_FTQ_CMD_WR_TOP_0			 (0L<<10)
5593
#define BCE_TPAT_FTQ_CMD_WR_TOP_1			 (1L<<10)
5594
#define BCE_TPAT_FTQ_CMD_SFT_RESET			 (1L<<25)
5595
#define BCE_TPAT_FTQ_CMD_RD_DATA			 (1L<<26)
5596
#define BCE_TPAT_FTQ_CMD_ADD_INTERVEN			 (1L<<27)
5597
#define BCE_TPAT_FTQ_CMD_ADD_DATA			 (1L<<28)
5598
#define BCE_TPAT_FTQ_CMD_INTERVENE_CLR			 (1L<<29)
5599
#define BCE_TPAT_FTQ_CMD_POP				 (1L<<30)
5600
#define BCE_TPAT_FTQ_CMD_BUSY				 (1L<<31)
5601

5602
#define BCE_TPAT_FTQ_CTL				0x000853fc
5603
#define BCE_TPAT_FTQ_CTL_INTERVENE			 (1L<<0)
5604
#define BCE_TPAT_FTQ_CTL_OVERFLOW			 (1L<<1)
5605
#define BCE_TPAT_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
5606
#define BCE_TPAT_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
5607
#define BCE_TPAT_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
5608

5609
#define BCE_TPAT_SCRATCH				0x000a0000
5610

5611
/*
5612
 *  rxp_reg definition
5613
 *  offset: 0xc0000
5614
 */
5615
#define BCE_RXP_CPU_MODE				0x000c5000
5616
#define BCE_RXP_CPU_MODE_LOCAL_RST			 (1L<<0)
5617
#define BCE_RXP_CPU_MODE_STEP_ENA			 (1L<<1)
5618
#define BCE_RXP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
5619
#define BCE_RXP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
5620
#define BCE_RXP_CPU_MODE_MSG_BIT1			 (1L<<6)
5621
#define BCE_RXP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
5622
#define BCE_RXP_CPU_MODE_SOFT_HALT			 (1L<<10)
5623
#define BCE_RXP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
5624
#define BCE_RXP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
5625
#define BCE_RXP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
5626
#define BCE_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
5627

5628
#define BCE_RXP_CPU_STATE				0x000c5004
5629
#define BCE_RXP_CPU_STATE_BREAKPOINT			 (1L<<0)
5630
#define BCE_RXP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
5631
#define BCE_RXP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
5632
#define BCE_RXP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
5633
#define BCE_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
5634
#define BCE_RXP_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
5635
#define BCE_RXP_CPU_STATE_ALIGN_HALTED			 (1L<<7)
5636
#define BCE_RXP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
5637
#define BCE_RXP_CPU_STATE_SOFT_HALTED			 (1L<<10)
5638
#define BCE_RXP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
5639
#define BCE_RXP_CPU_STATE_INTERRRUPT			 (1L<<12)
5640
#define BCE_RXP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
5641
#define BCE_RXP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
5642
#define BCE_RXP_CPU_STATE_BLOCKED_READ			 (1L<<31)
5643

5644
#define BCE_RXP_CPU_EVENT_MASK				0x000c5008
5645
#define BCE_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
5646
#define BCE_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
5647
#define BCE_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
5648
#define BCE_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
5649
#define BCE_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
5650
#define BCE_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
5651
#define BCE_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
5652
#define BCE_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
5653
#define BCE_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
5654
#define BCE_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
5655
#define BCE_RXP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
5656

5657
#define BCE_RXP_CPU_PROGRAM_COUNTER			0x000c501c
5658
#define BCE_RXP_CPU_INSTRUCTION			0x000c5020
5659
#define BCE_RXP_CPU_DATA_ACCESS			0x000c5024
5660
#define BCE_RXP_CPU_INTERRUPT_ENABLE			0x000c5028
5661
#define BCE_RXP_CPU_INTERRUPT_VECTOR			0x000c502c
5662
#define BCE_RXP_CPU_INTERRUPT_SAVED_PC			0x000c5030
5663
#define BCE_RXP_CPU_HW_BREAKPOINT			0x000c5034
5664
#define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
5665
#define BCE_RXP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
5666

5667
#define BCE_RXP_CPU_REG_FILE				0x000c5200
5668
#define BCE_RXP_CFTQ_DATA				0x000c5380
5669
#define BCE_RXP_CFTQ_CMD				0x000c53b8
5670
#define BCE_RXP_CFTQ_CMD_OFFSET			 (0x3ffL<<0)
5671
#define BCE_RXP_CFTQ_CMD_WR_TOP			 (1L<<10)
5672
#define BCE_RXP_CFTQ_CMD_WR_TOP_0			 (0L<<10)
5673
#define BCE_RXP_CFTQ_CMD_WR_TOP_1			 (1L<<10)
5674
#define BCE_RXP_CFTQ_CMD_SFT_RESET			 (1L<<25)
5675
#define BCE_RXP_CFTQ_CMD_RD_DATA			 (1L<<26)
5676
#define BCE_RXP_CFTQ_CMD_ADD_INTERVEN			 (1L<<27)
5677
#define BCE_RXP_CFTQ_CMD_ADD_DATA			 (1L<<28)
5678
#define BCE_RXP_CFTQ_CMD_INTERVENE_CLR			 (1L<<29)
5679
#define BCE_RXP_CFTQ_CMD_POP				 (1L<<30)
5680
#define BCE_RXP_CFTQ_CMD_BUSY				 (1L<<31)
5681

5682
#define BCE_RXP_CFTQ_CTL				0x000c53bc
5683
#define BCE_RXP_CFTQ_CTL_INTERVENE			 (1L<<0)
5684
#define BCE_RXP_CFTQ_CTL_OVERFLOW			 (1L<<1)
5685
#define BCE_RXP_CFTQ_CTL_FORCE_INTERVENE		 (1L<<2)
5686
#define BCE_RXP_CFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
5687
#define BCE_RXP_CFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
5688

5689
#define BCE_RXP_FTQ_DATA				0x000c53c0
5690
#define BCE_RXP_FTQ_CMD				0x000c53f8
5691
#define BCE_RXP_FTQ_CMD_OFFSET				 (0x3ffL<<0)
5692
#define BCE_RXP_FTQ_CMD_WR_TOP				 (1L<<10)
5693
#define BCE_RXP_FTQ_CMD_WR_TOP_0			 (0L<<10)
5694
#define BCE_RXP_FTQ_CMD_WR_TOP_1			 (1L<<10)
5695
#define BCE_RXP_FTQ_CMD_SFT_RESET			 (1L<<25)
5696
#define BCE_RXP_FTQ_CMD_RD_DATA			 (1L<<26)
5697
#define BCE_RXP_FTQ_CMD_ADD_INTERVEN			 (1L<<27)
5698
#define BCE_RXP_FTQ_CMD_ADD_DATA			 (1L<<28)
5699
#define BCE_RXP_FTQ_CMD_INTERVENE_CLR			 (1L<<29)
5700
#define BCE_RXP_FTQ_CMD_POP				 (1L<<30)
5701
#define BCE_RXP_FTQ_CMD_BUSY				 (1L<<31)
5702

5703
#define BCE_RXP_FTQ_CTL				0x000c53fc
5704
#define BCE_RXP_FTQ_CTL_INTERVENE			 (1L<<0)
5705
#define BCE_RXP_FTQ_CTL_OVERFLOW			 (1L<<1)
5706
#define BCE_RXP_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
5707
#define BCE_RXP_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
5708
#define BCE_RXP_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
5709

5710
#define BCE_RXP_SCRATCH				0x000e0000
5711

5712
/*
5713
 *  com_reg definition
5714
 *  offset: 0x100000
5715
 */
5716
#define BCE_COM_CPU_MODE				0x00105000
5717
#define BCE_COM_CPU_MODE_LOCAL_RST			 (1L<<0)
5718
#define BCE_COM_CPU_MODE_STEP_ENA			 (1L<<1)
5719
#define BCE_COM_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
5720
#define BCE_COM_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
5721
#define BCE_COM_CPU_MODE_MSG_BIT1			 (1L<<6)
5722
#define BCE_COM_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
5723
#define BCE_COM_CPU_MODE_SOFT_HALT			 (1L<<10)
5724
#define BCE_COM_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
5725
#define BCE_COM_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
5726
#define BCE_COM_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
5727
#define BCE_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
5728

5729
#define BCE_COM_CPU_STATE				0x00105004
5730
#define BCE_COM_CPU_STATE_BREAKPOINT			 (1L<<0)
5731
#define BCE_COM_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
5732
#define BCE_COM_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
5733
#define BCE_COM_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
5734
#define BCE_COM_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
5735
#define BCE_COM_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
5736
#define BCE_COM_CPU_STATE_ALIGN_HALTED			 (1L<<7)
5737
#define BCE_COM_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
5738
#define BCE_COM_CPU_STATE_SOFT_HALTED			 (1L<<10)
5739
#define BCE_COM_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
5740
#define BCE_COM_CPU_STATE_INTERRRUPT			 (1L<<12)
5741
#define BCE_COM_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
5742
#define BCE_COM_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
5743
#define BCE_COM_CPU_STATE_BLOCKED_READ			 (1L<<31)
5744

5745
#define BCE_COM_CPU_EVENT_MASK				0x00105008
5746
#define BCE_COM_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
5747
#define BCE_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
5748
#define BCE_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
5749
#define BCE_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
5750
#define BCE_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
5751
#define BCE_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
5752
#define BCE_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
5753
#define BCE_COM_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
5754
#define BCE_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
5755
#define BCE_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
5756
#define BCE_COM_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
5757

5758
#define BCE_COM_CPU_PROGRAM_COUNTER			0x0010501c
5759
#define BCE_COM_CPU_INSTRUCTION			0x00105020
5760
#define BCE_COM_CPU_DATA_ACCESS			0x00105024
5761
#define BCE_COM_CPU_INTERRUPT_ENABLE			0x00105028
5762
#define BCE_COM_CPU_INTERRUPT_VECTOR			0x0010502c
5763
#define BCE_COM_CPU_INTERRUPT_SAVED_PC			0x00105030
5764
#define BCE_COM_CPU_HW_BREAKPOINT			0x00105034
5765
#define BCE_COM_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
5766
#define BCE_COM_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
5767

5768
#define BCE_COM_CPU_REG_FILE				0x00105200
5769
#define BCE_COM_COMXQ_FTQ_DATA				0x00105340
5770
#define BCE_COM_COMXQ_FTQ_CMD				0x00105378
5771
#define BCE_COM_COMXQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
5772
#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP			 (1L<<10)
5773
#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
5774
#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
5775
#define BCE_COM_COMXQ_FTQ_CMD_SFT_RESET		 (1L<<25)
5776
#define BCE_COM_COMXQ_FTQ_CMD_RD_DATA			 (1L<<26)
5777
#define BCE_COM_COMXQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
5778
#define BCE_COM_COMXQ_FTQ_CMD_ADD_DATA			 (1L<<28)
5779
#define BCE_COM_COMXQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
5780
#define BCE_COM_COMXQ_FTQ_CMD_POP			 (1L<<30)
5781
#define BCE_COM_COMXQ_FTQ_CMD_BUSY			 (1L<<31)
5782

5783
#define BCE_COM_COMXQ_FTQ_CTL				0x0010537c
5784
#define BCE_COM_COMXQ_FTQ_CTL_INTERVENE		 (1L<<0)
5785
#define BCE_COM_COMXQ_FTQ_CTL_OVERFLOW			 (1L<<1)
5786
#define BCE_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
5787
#define BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
5788
#define BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
5789

5790
#define BCE_COM_COMTQ_FTQ_DATA				0x00105380
5791
#define BCE_COM_COMTQ_FTQ_CMD				0x001053b8
5792
#define BCE_COM_COMTQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
5793
#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP			 (1L<<10)
5794
#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
5795
#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
5796
#define BCE_COM_COMTQ_FTQ_CMD_SFT_RESET		 (1L<<25)
5797
#define BCE_COM_COMTQ_FTQ_CMD_RD_DATA			 (1L<<26)
5798
#define BCE_COM_COMTQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
5799
#define BCE_COM_COMTQ_FTQ_CMD_ADD_DATA			 (1L<<28)
5800
#define BCE_COM_COMTQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
5801
#define BCE_COM_COMTQ_FTQ_CMD_POP			 (1L<<30)
5802
#define BCE_COM_COMTQ_FTQ_CMD_BUSY			 (1L<<31)
5803

5804
#define BCE_COM_COMTQ_FTQ_CTL				0x001053bc
5805
#define BCE_COM_COMTQ_FTQ_CTL_INTERVENE		 (1L<<0)
5806
#define BCE_COM_COMTQ_FTQ_CTL_OVERFLOW			 (1L<<1)
5807
#define BCE_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
5808
#define BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
5809
#define BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
5810

5811
#define BCE_COM_COMQ_FTQ_DATA				0x001053c0
5812
#define BCE_COM_COMQ_FTQ_CMD				0x001053f8
5813
#define BCE_COM_COMQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
5814
#define BCE_COM_COMQ_FTQ_CMD_WR_TOP			 (1L<<10)
5815
#define BCE_COM_COMQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
5816
#define BCE_COM_COMQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
5817
#define BCE_COM_COMQ_FTQ_CMD_SFT_RESET			 (1L<<25)
5818
#define BCE_COM_COMQ_FTQ_CMD_RD_DATA			 (1L<<26)
5819
#define BCE_COM_COMQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
5820
#define BCE_COM_COMQ_FTQ_CMD_ADD_DATA			 (1L<<28)
5821
#define BCE_COM_COMQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
5822
#define BCE_COM_COMQ_FTQ_CMD_POP			 (1L<<30)
5823
#define BCE_COM_COMQ_FTQ_CMD_BUSY			 (1L<<31)
5824

5825
#define BCE_COM_COMQ_FTQ_CTL				0x001053fc
5826
#define BCE_COM_COMQ_FTQ_CTL_INTERVENE			 (1L<<0)
5827
#define BCE_COM_COMQ_FTQ_CTL_OVERFLOW			 (1L<<1)
5828
#define BCE_COM_COMQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
5829
#define BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
5830
#define BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
5831

5832
#define BCE_COM_SCRATCH				0x00120000
5833

5834
/*
5835
 *  cp_reg definition
5836
 *  offset: 0x180000
5837
 */
5838
#define BCE_CP_CPU_MODE				0x00185000
5839
#define BCE_CP_CPU_MODE_LOCAL_RST			 (1L<<0)
5840
#define BCE_CP_CPU_MODE_STEP_ENA			 (1L<<1)
5841
#define BCE_CP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
5842
#define BCE_CP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
5843
#define BCE_CP_CPU_MODE_MSG_BIT1			 (1L<<6)
5844
#define BCE_CP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
5845
#define BCE_CP_CPU_MODE_SOFT_HALT			 (1L<<10)
5846
#define BCE_CP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
5847
#define BCE_CP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
5848
#define BCE_CP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
5849
#define BCE_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
5850

5851
#define BCE_CP_CPU_STATE				0x00185004
5852
#define BCE_CP_CPU_STATE_BREAKPOINT			 (1L<<0)
5853
#define BCE_CP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
5854
#define BCE_CP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
5855
#define BCE_CP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
5856
#define BCE_CP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
5857
#define BCE_CP_CPU_STATE_BAD_pc_HALTED			 (1L<<6)
5858
#define BCE_CP_CPU_STATE_ALIGN_HALTED			 (1L<<7)
5859
#define BCE_CP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
5860
#define BCE_CP_CPU_STATE_SOFT_HALTED			 (1L<<10)
5861
#define BCE_CP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
5862
#define BCE_CP_CPU_STATE_INTERRRUPT			 (1L<<12)
5863
#define BCE_CP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
5864
#define BCE_CP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
5865
#define BCE_CP_CPU_STATE_BLOCKED_READ			 (1L<<31)
5866

5867
#define BCE_CP_CPU_EVENT_MASK				0x00185008
5868
#define BCE_CP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
5869
#define BCE_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
5870
#define BCE_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
5871
#define BCE_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
5872
#define BCE_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
5873
#define BCE_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
5874
#define BCE_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
5875
#define BCE_CP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
5876
#define BCE_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK		 (1L<<10)
5877
#define BCE_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
5878
#define BCE_CP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
5879

5880
#define BCE_CP_CPU_PROGRAM_COUNTER			0x0018501c
5881
#define BCE_CP_CPU_INSTRUCTION				0x00185020
5882
#define BCE_CP_CPU_DATA_ACCESS				0x00185024
5883
#define BCE_CP_CPU_INTERRUPT_ENABLE			0x00185028
5884
#define BCE_CP_CPU_INTERRUPT_VECTOR			0x0018502c
5885
#define BCE_CP_CPU_INTERRUPT_SAVED_PC			0x00185030
5886
#define BCE_CP_CPU_HW_BREAKPOINT			0x00185034
5887
#define BCE_CP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
5888
#define BCE_CP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
5889

5890
#define BCE_CP_CPU_REG_FILE				0x00185200
5891
#define BCE_CP_CPQ_FTQ_DATA				0x001853c0
5892
#define BCE_CP_CPQ_FTQ_CMD				0x001853f8
5893
#define BCE_CP_CPQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
5894
#define BCE_CP_CPQ_FTQ_CMD_WR_TOP			 (1L<<10)
5895
#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
5896
#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
5897
#define BCE_CP_CPQ_FTQ_CMD_SFT_RESET			 (1L<<25)
5898
#define BCE_CP_CPQ_FTQ_CMD_RD_DATA			 (1L<<26)
5899
#define BCE_CP_CPQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
5900
#define BCE_CP_CPQ_FTQ_CMD_ADD_DATA			 (1L<<28)
5901
#define BCE_CP_CPQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
5902
#define BCE_CP_CPQ_FTQ_CMD_POP				 (1L<<30)
5903
#define BCE_CP_CPQ_FTQ_CMD_BUSY			 (1L<<31)
5904

5905
#define BCE_CP_CPQ_FTQ_CTL				0x001853fc
5906
#define BCE_CP_CPQ_FTQ_CTL_INTERVENE			 (1L<<0)
5907
#define BCE_CP_CPQ_FTQ_CTL_OVERFLOW			 (1L<<1)
5908
#define BCE_CP_CPQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
5909
#define BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
5910
#define BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
5911

5912
#define BCE_CP_SCRATCH					0x001a0000
5913

5914
/*
5915
 *  tas_reg definition
5916
 *  offset: 0x1c0000
5917
 */
5918
#define BCE_TAS_FTQ_CMD						0x001c03f8
5919
#define BCE_TAS_FTQ_CTL						0x001c03fc
5920
#define BCE_TAS_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
5921
#define BCE_TAS_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
5922

5923
/*
5924
 *  mcp_reg definition
5925
 *  offset: 0x140000
5926
 */
5927
#define BCE_MCP_CPU_MODE				0x00145000
5928
#define BCE_MCP_CPU_MODE_LOCAL_RST			 (1L<<0)
5929
#define BCE_MCP_CPU_MODE_STEP_ENA			 (1L<<1)
5930
#define BCE_MCP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
5931
#define BCE_MCP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
5932
#define BCE_MCP_CPU_MODE_MSG_BIT1			 (1L<<6)
5933
#define BCE_MCP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
5934
#define BCE_MCP_CPU_MODE_SOFT_HALT			 (1L<<10)
5935
#define BCE_MCP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
5936
#define BCE_MCP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
5937
#define BCE_MCP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
5938
#define BCE_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
5939

5940
#define BCE_MCP_CPU_STATE				0x00145004
5941
#define BCE_MCP_CPU_STATE_BREAKPOINT			 (1L<<0)
5942
#define BCE_MCP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
5943
#define BCE_MCP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
5944
#define BCE_MCP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
5945
#define BCE_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
5946
#define BCE_MCP_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
5947
#define BCE_MCP_CPU_STATE_ALIGN_HALTED			 (1L<<7)
5948
#define BCE_MCP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
5949
#define BCE_MCP_CPU_STATE_SOFT_HALTED			 (1L<<10)
5950
#define BCE_MCP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
5951
#define BCE_MCP_CPU_STATE_INTERRRUPT			 (1L<<12)
5952
#define BCE_MCP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
5953
#define BCE_MCP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
5954
#define BCE_MCP_CPU_STATE_BLOCKED_READ			 (1L<<31)
5955

5956
#define BCE_MCP_CPU_EVENT_MASK				0x00145008
5957
#define BCE_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
5958
#define BCE_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
5959
#define BCE_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
5960
#define BCE_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
5961
#define BCE_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
5962
#define BCE_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
5963
#define BCE_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
5964
#define BCE_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
5965
#define BCE_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
5966
#define BCE_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
5967
#define BCE_MCP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
5968

5969
#define BCE_MCP_CPU_PROGRAM_COUNTER			0x0014501c
5970
#define BCE_MCP_CPU_INSTRUCTION			0x00145020
5971
#define BCE_MCP_CPU_DATA_ACCESS			0x00145024
5972
#define BCE_MCP_CPU_INTERRUPT_ENABLE			0x00145028
5973
#define BCE_MCP_CPU_INTERRUPT_VECTOR			0x0014502c
5974
#define BCE_MCP_CPU_INTERRUPT_SAVED_PC			0x00145030
5975
#define BCE_MCP_CPU_HW_BREAKPOINT			0x00145034
5976
#define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
5977
#define BCE_MCP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
5978

5979
#define BCE_MCP_CPU_REG_FILE				0x00145200
5980
#define BCE_MCP_MCPQ_FTQ_DATA				0x001453c0
5981
#define BCE_MCP_MCPQ_FTQ_CMD				0x001453f8
5982
#define BCE_MCP_MCPQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
5983
#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP			 (1L<<10)
5984
#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
5985
#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
5986
#define BCE_MCP_MCPQ_FTQ_CMD_SFT_RESET			 (1L<<25)
5987
#define BCE_MCP_MCPQ_FTQ_CMD_RD_DATA			 (1L<<26)
5988
#define BCE_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
5989
#define BCE_MCP_MCPQ_FTQ_CMD_ADD_DATA			 (1L<<28)
5990
#define BCE_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
5991
#define BCE_MCP_MCPQ_FTQ_CMD_POP			 (1L<<30)
5992
#define BCE_MCP_MCPQ_FTQ_CMD_BUSY			 (1L<<31)
5993

5994
#define BCE_MCP_MCPQ_FTQ_CTL				0x001453fc
5995
#define BCE_MCP_MCPQ_FTQ_CTL_INTERVENE			 (1L<<0)
5996
#define BCE_MCP_MCPQ_FTQ_CTL_OVERFLOW			 (1L<<1)
5997
#define BCE_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
5998
#define BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
5999
#define BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
6000

6001
#define BCE_MCP_ROM								0x00150000
6002
#define BCE_MCP_SCRATCH							0x00160000
6003

6004
#define BCE_SHM_HDR_SIGNATURE					BCE_MCP_SCRATCH
6005
#define BCE_SHM_HDR_SIGNATURE_SIG_MASK			0xffff0000
6006
#define BCE_SHM_HDR_SIGNATURE_SIG				0x53530000
6007
#define BCE_SHM_HDR_SIGNATURE_VER_MASK			0x000000ff
6008
#define BCE_SHM_HDR_SIGNATURE_VER_ONE			0x00000001
6009

6010
#define BCE_SHM_HDR_ADDR_0				BCE_MCP_SCRATCH + 4
6011
#define BCE_SHM_HDR_ADDR_1				BCE_MCP_SCRATCH + 8
6012

6013
/****************************************************************************/
6014
/* End machine generated definitions.                                     */
6015
/****************************************************************************/
6016

6017
/****************************************************************************/
6018
/* Begin firmware definitions.                                              */
6019
/****************************************************************************/
6020
/* The following definitions refer to pre-defined locations in processor    */
6021
/* memory space which allows the driver to enable particular functionality  */
6022
/* within the firmware or read specific information about the running        */
6023
/* firmware.                                                                */
6024
/****************************************************************************/
6025

6026
/*
6027
 * Perfect match control register.
6028
 * 0 = Default.  All received unicst packets matching MAC address
6029
 *     BCE_EMAC_MAC_MATCH[0:1,8:9,10:11,12:13,14:15] are sent to receive queue
6030
 *     0, all other perfect match registers are reserved.
6031
 * 1 = All received unicast packets matching MAC address
6032
 *     BCE_EMAC_MAC_MATCH[0:1] are mapped to receive queue 0,
6033
 *     BCE_EMAC_MAC_MATCH[2:3] is mapped to receive queue 1, etc.
6034
 * 2 = All received unicast packets matching any BCE_EMAC_MAC_MATCH[] register
6035
 *     are sent to receive queue 0.
6036
 */
6037
#define BCE_RXP_PM_CTRL			0x0e00d0
6038

6039
/*
6040
 * This firmware statistic records the number of frames that
6041
 * were dropped because there were no buffers available in the
6042
 * receive chain.
6043
 */
6044
#define BCE_COM_NO_BUFFERS		0x120084
6045
/****************************************************************************/
6046
/* End firmware definitions.                                                */
6047
/****************************************************************************/
6048

6049
#define NUM_MC_HASH_REGISTERS   8
6050

6051
#define DMA_READ_CHANS	5
6052
#define DMA_WRITE_CHANS	3
6053

6054
/* Use the natural page size of the host CPU. */
6055
/* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */
6056
#define BCM_PAGE_BITS	PAGE_SHIFT
6057
#define BCM_PAGE_SIZE	PAGE_SIZE
6058
#define BCM_PAGE_MASK	(BCM_PAGE_SIZE - 1)
6059
#define BCM_PAGES(x)	((((x) + BCM_PAGE_SIZE - 1) & \
6060
    BCM_PAGE_MASK) >> BCM_PAGE_BITS)
6061

6062
/*
6063
 * Page count must remain a power of 2 for all
6064
 * of the math to work correctly.
6065
 */
6066
#define DEFAULT_TX_PAGES		2
6067
#define MAX_TX_PAGES			8
6068
#define TOTAL_TX_BD_PER_PAGE	(BCM_PAGE_SIZE / sizeof(struct tx_bd))
6069
#define USABLE_TX_BD_PER_PAGE	(TOTAL_TX_BD_PER_PAGE - 1)
6070
#define MAX_TX_BD_AVAIL		(MAX_TX_PAGES * TOTAL_TX_BD_PER_PAGE)
6071
#define TOTAL_TX_BD_ALLOC		(TOTAL_TX_BD_PER_PAGE * sc->tx_pages)
6072
#define USABLE_TX_BD_ALLOC		(USABLE_TX_BD_PER_PAGE * sc->tx_pages)
6073
#define MAX_TX_BD_ALLOC		(TOTAL_TX_BD_ALLOC - 1)
6074

6075
/* Advance to the next tx_bd, skipping any next page pointers. */
6076
#define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) ==	\
6077
    (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1
6078

6079
#define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD_ALLOC)
6080

6081
#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
6082
#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
6083

6084
/*
6085
 * Page count must remain a power of 2 for all
6086
 * of the math to work correctly.
6087
 */
6088
#define DEFAULT_RX_PAGES		2
6089
#define MAX_RX_PAGES			8
6090
#define TOTAL_RX_BD_PER_PAGE	(BCM_PAGE_SIZE / sizeof(struct rx_bd))
6091
#define USABLE_RX_BD_PER_PAGE	(TOTAL_RX_BD_PER_PAGE - 1)
6092
#define MAX_RX_BD_AVAIL		(MAX_RX_PAGES * TOTAL_RX_BD_PER_PAGE)
6093
#define TOTAL_RX_BD_ALLOC		(TOTAL_RX_BD_PER_PAGE * sc->rx_pages)
6094
#define USABLE_RX_BD_ALLOC		(USABLE_RX_BD_PER_PAGE * sc->rx_pages)
6095
#define MAX_RX_BD_ALLOC		(TOTAL_RX_BD_ALLOC - 1)
6096

6097
/* Advance to the next rx_bd, skipping any next page pointers. */
6098
#define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) ==	\
6099
    (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1
6100

6101
#define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD_ALLOC)
6102

6103
#define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
6104
#define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE)
6105

6106
/*
6107
 * To accommodate jumbo frames, the page chain should
6108
 * be 4 times larger than the receive chain.
6109
 */
6110
#define DEFAULT_PG_PAGES		(DEFAULT_RX_PAGES * 4)
6111
#define MAX_PG_PAGES			(MAX_RX_PAGES * 4)
6112
#define TOTAL_PG_BD_PER_PAGE	(BCM_PAGE_SIZE / sizeof(struct rx_bd))
6113
#define USABLE_PG_BD_PER_PAGE	(TOTAL_PG_BD_PER_PAGE - 1)
6114
#define MAX_PG_BD_AVAIL		(MAX_PG_PAGES * TOTAL_PG_BD_PER_PAGE)
6115
#define TOTAL_PG_BD_ALLOC		(TOTAL_PG_BD_PER_PAGE * sc->pg_pages)
6116
#define USABLE_PG_BD_ALLOC		(USABLE_PG_BD_PER_PAGE * sc->pg_pages)
6117
#define MAX_PG_BD_ALLOC		(TOTAL_PG_BD_ALLOC - 1)
6118

6119
/* Advance to the next pg_bd, skipping any next page pointers. */
6120
#define NEXT_PG_BD(x) (((x) & USABLE_PG_BD_PER_PAGE) ==	\
6121
    (USABLE_PG_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1
6122

6123
#define PG_CHAIN_IDX(x) ((x) & MAX_PG_BD_ALLOC)
6124

6125
#define PG_PAGE(x) (((x) & ~USABLE_PG_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
6126
#define PG_IDX(x) ((x) & USABLE_PG_BD_PER_PAGE)
6127

6128
#define CTX_INIT_RETRY_COUNT        10
6129

6130
/* Context size. */
6131
#define CTX_SHIFT		7
6132
#define CTX_SIZE		(1 << CTX_SHIFT)
6133
#define CTX_MASK		(CTX_SIZE - 1)
6134
#define GET_CID_ADDR(_cid)	((_cid) << CTX_SHIFT)
6135
#define GET_CID(_cid_addr)	((_cid_addr) >> CTX_SHIFT)
6136

6137
#define PHY_CTX_SHIFT		6
6138
#define PHY_CTX_SIZE		(1 << PHY_CTX_SHIFT)
6139
#define PHY_CTX_MASK		(PHY_CTX_SIZE - 1)
6140
#define GET_PCID_ADDR(_pcid)	((_pcid) << PHY_CTX_SHIFT)
6141
#define GET_PCID(_pcid_addr)	((_pcid_addr) >> PHY_CTX_SHIFT)
6142

6143
#define MB_KERNEL_CTX_SHIFT	8
6144
#define MB_KERNEL_CTX_SIZE	(1 << MB_KERNEL_CTX_SHIFT)
6145
#define MB_KERNEL_CTX_MASK	(MB_KERNEL_CTX_SIZE - 1)
6146
#define MB_GET_CID_ADDR(_cid)	(0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
6147

6148
#define MAX_CID_CNT		0x4000
6149
#define MAX_CID_ADDR		(GET_CID_ADDR(MAX_CID_CNT))
6150
#define INVALID_CID_ADDR	0xffffffff
6151

6152
#define TX_CID			16
6153
#define RX_CID			0
6154

6155
#define DEFAULT_TX_QUICK_CONS_TRIP_INT	20
6156
#define DEFAULT_TX_QUICK_CONS_TRIP		20
6157
#define DEFAULT_TX_TICKS_INT			80
6158
#define DEFAULT_TX_TICKS				80
6159
#define DEFAULT_RX_QUICK_CONS_TRIP_INT	6
6160
#define DEFAULT_RX_QUICK_CONS_TRIP		6
6161
#define DEFAULT_RX_TICKS_INT			18
6162
#define DEFAULT_RX_TICKS				18
6163

6164
/****************************************************************************/
6165
/* BCE Processor Firmwware Load Definitions                                 */
6166
/****************************************************************************/
6167

6168
struct cpu_reg {
6169
	u32 mode;
6170
	u32 mode_value_halt;
6171
	u32 mode_value_sstep;
6172

6173
	u32 state;
6174
	u32 state_value_clear;
6175

6176
	u32 gpr0;
6177
	u32 evmask;
6178
	u32 pc;
6179
	u32 inst;
6180
	u32 bp;
6181

6182
	u32 spad_base;
6183

6184
	u32 mips_view_base;
6185
};
6186

6187
struct fw_info {
6188
	u32 ver_major;
6189
	u32 ver_minor;
6190
	u32 ver_fix;
6191

6192
	u32 start_addr;
6193

6194
	/* Text section. */
6195
	u32 text_addr;
6196
	u32 text_len;
6197
	u32 text_index;
6198
	const u32 *text;
6199

6200
	/* Data section. */
6201
	u32 data_addr;
6202
	u32 data_len;
6203
	u32 data_index;
6204
	const u32 *data;
6205

6206
	/* SBSS section. */
6207
	u32 sbss_addr;
6208
	u32 sbss_len;
6209
	u32 sbss_index;
6210
	const u32 *sbss;
6211

6212
	/* BSS section. */
6213
	u32 bss_addr;
6214
	u32 bss_len;
6215
	u32 bss_index;
6216
	const u32 *bss;
6217

6218
	/* Read-only section. */
6219
	u32 rodata_addr;
6220
	u32 rodata_len;
6221
	u32 rodata_index;
6222
	const u32 *rodata;
6223
};
6224

6225
#define RV2P_PROC1		0
6226
#define RV2P_PROC2		1
6227

6228
#define BCE_MIREG(x)		((x & 0x1F) << 16)
6229
#define BCE_MIPHY(x)		((x & 0x1F) << 21)
6230
#define BCE_PHY_TIMEOUT		50
6231

6232
#define BCE_NVRAM_SIZE		0x200
6233
#define BCE_NVRAM_MAGIC		0x669955aa
6234
#define BCE_CRC32_RESIDUAL	0xdebb20e3
6235

6236
#define BCE_TX_TIMEOUT		5
6237

6238
#define BCE_MAX_SEGMENTS	35
6239
#define BCE_TSO_MAX_SIZE	(65535 + sizeof(struct ether_vlan_header))
6240
#define BCE_TSO_MAX_SEG_SIZE	4096
6241

6242
#define BCE_DMA_ALIGN		8
6243
#define BCE_DMA_BOUNDARY	0
6244
#define BCE_RX_BUF_ALIGN	16
6245

6246
#define BCE_MAX_CONTEXT		4
6247

6248
/* The BCM5708 has a problem with addresses greater that 40bits. */
6249
/* Handle the sizing issue in an architecture agnostic fashion.  */
6250
#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
6251
#define BCE_BUS_SPACE_MAXADDR		BUS_SPACE_MAXADDR
6252
#else
6253
#define BCE_BUS_SPACE_MAXADDR		0xFFFFFFFFFF
6254
#endif
6255

6256
/*
6257
 * XXX Checksum offload involving IP fragments seems to cause problems on
6258
 * transmit.  Disable it for now, hopefully there will be a more elegant
6259
 * solution later.
6260
 */
6261
#ifdef BCE_IP_CSUM
6262
#define BCE_IF_HWASSIST	(CSUM_IP | CSUM_TCP | CSUM_UDP)
6263
#else
6264
#define BCE_IF_HWASSIST	(CSUM_TCP | CSUM_UDP)
6265
#endif
6266

6267
#define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU |			\
6268
    IFCAP_VLAN_HWTAGGING | IFCAP_HWCSUM |			\
6269
    IFCAP_JUMBO_MTU | IFCAP_VLAN_HWCSUM)
6270

6271
#define BCE_MIN_MTU			60
6272
#define BCE_MIN_ETHER_MTU		64
6273

6274
#define BCE_MAX_STD_MTU			1500
6275
#define BCE_MAX_STD_ETHER_MTU		1518
6276
#define BCE_MAX_STD_ETHER_MTU_VLAN	1522
6277

6278
#define BCE_MAX_JUMBO_MTU		9000
6279
#define BCE_MAX_JUMBO_ETHER_MTU		9018
6280
#define BCE_MAX_JUMBO_ETHER_MTU_VLAN 	9022
6281

6282
// #define BCE_MAX_MTU		ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN	/* 9022 */
6283

6284
/****************************************************************************/
6285
/* BCE Device State Data Structure                                          */
6286
/****************************************************************************/
6287

6288
#define BCE_STATUS_BLK_SZ	sizeof(struct status_block)
6289
#define BCE_STATS_BLK_SZ	sizeof(struct statistics_block)
6290
#define BCE_TX_CHAIN_PAGE_SZ	BCM_PAGE_SIZE
6291
#define BCE_RX_CHAIN_PAGE_SZ	BCM_PAGE_SIZE
6292
#define BCE_PG_CHAIN_PAGE_SZ	BCM_PAGE_SIZE
6293

6294
struct bce_softc
6295
{
6296
	struct mtx		bce_mtx;
6297

6298
	/* Interface info */
6299
	if_t			bce_ifp;
6300

6301
	/* Parent device handle */
6302
	device_t		bce_dev;
6303

6304
	/* Interface number */
6305
	u_int8_t		bce_unit;
6306

6307
	/* Device resource handle */
6308
	struct resource		*bce_res_mem;
6309

6310
	/* TBI media info */
6311
	struct ifmedia		bce_ifmedia;
6312

6313
	/* Device bus tag */
6314
	bus_space_tag_t		bce_btag;
6315

6316
	/* Device bus handle */
6317
	bus_space_handle_t	bce_bhandle;
6318

6319
	/* Device virtual memory handle */
6320
	vm_offset_t		bce_vhandle;
6321

6322
	/* IRQ Resource Handle */
6323
	struct resource		*bce_res_irq;
6324

6325
	/* Interrupt handler. */
6326
	void			*bce_intrhand;
6327

6328
	/* ASIC Chip ID. */
6329
	u32			bce_chipid;
6330

6331
	/* General controller flags. */
6332
	u32			bce_flags;
6333
#define BCE_PCIX_FLAG				0x00000001
6334
#define BCE_PCI_32BIT_FLAG 			0x00000002
6335
#define BCE_RESERVED_FLAG			0x00000004
6336
#define BCE_NO_WOL_FLAG				0x00000008
6337
#define BCE_USING_DAC_FLAG			0x00000010
6338
#define BCE_USING_MSI_FLAG 			0x00000020
6339
#define BCE_MFW_ENABLE_FLAG			0x00000040
6340
#define BCE_ONE_SHOT_MSI_FLAG			0x00000080
6341
#define BCE_USING_MSIX_FLAG			0x00000100
6342
#define BCE_PCIE_FLAG				0x00000200
6343
#define BCE_USING_TX_FLOW_CONTROL		0x00000400
6344
#define BCE_USING_RX_FLOW_CONTROL		0x00000800
6345

6346
	/* Controller capability flags. */
6347
	u32			bce_cap_flags;
6348
#define BCE_MSI_CAPABLE_FLAG			0x00000001
6349
#define BCE_MSIX_CAPABLE_FLAG			0x00000002
6350
#define BCE_PCIE_CAPABLE_FLAG			0x00000004
6351
#define BCE_PCIX_CAPABLE_FLAG			0x00000008
6352

6353
	/* PHY specific flags. */
6354
	u32			bce_phy_flags;
6355
#define BCE_PHY_SERDES_FLAG			0x00000001
6356
#define BCE_PHY_CRC_FIX_FLAG			0x00000002
6357
#define BCE_PHY_PARALLEL_DETECT_FLAG		0x00000004
6358
#define BCE_PHY_2_5G_CAPABLE_FLAG		0x00000008
6359
#define BCE_PHY_INT_MODE_MASK_FLAG		0x00000300
6360
#define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG	0x00000100
6361
#define BCE_PHY_INT_MODE_LINK_READY_FLAG	0x00000200
6362
#define BCE_PHY_IEEE_CLAUSE_45_FLAG		0x00000400
6363
#define	BCE_PHY_REMOTE_CAP_FLAG			0x00000800
6364
#define	BCE_PHY_REMOTE_PORT_FIBER_FLAG		0x00001000
6365

6366
	/* Values that need to be shared with the PHY driver. */
6367
	u32			bce_shared_hw_cfg;
6368
	u32			bce_port_hw_cfg;
6369

6370
	bus_addr_t		max_bus_addr;
6371

6372
	/* PCI bus speed */
6373
	u16			bus_speed_mhz;
6374

6375
	/* PCIe link width */
6376
	u16			link_width;
6377

6378
	/* PCIe link speed */
6379
	u16			link_speed;
6380

6381
	/* Flash NVRAM settings */
6382
	const struct flash_spec	*bce_flash_info;
6383

6384
	/* Flash NVRAM size */
6385
	u32			bce_flash_size;
6386

6387
	/* Shared Memory base address */
6388
	u32			bce_shmem_base;
6389

6390
	/* Name string */
6391
	const char		*bce_name;
6392

6393
	/* Tracks the version of bootcode firmware. */
6394
	char			bce_bc_ver[32];
6395

6396
	/* Tracks the version of management firmware. */
6397
	char			bce_mfw_ver[32];
6398

6399
	/*
6400
	 * Tracks the state of the firmware.  0 = Running while any
6401
	 * other value indicates that the firmware is not responding.
6402
	 */
6403
	u16			bce_fw_timed_out;
6404

6405
	/*
6406
	 * An incrementing sequence used to coordinate messages passed
6407
	 * from the driver to the firmware.
6408
	 */
6409
	u16			bce_fw_wr_seq;
6410

6411
	/*
6412
	 * An incrementing sequence used to let the firmware know that
6413
	 * the driver is still operating.  Without the pulse, management
6414
	 * firmware such as IPMI or UMP will operate in OS absent state.
6415
	 */
6416
	u16			bce_fw_drv_pulse_wr_seq;
6417

6418
	/* Tracks whether firmware has lost the driver's pulse. */
6419
	u16			bce_drv_cardiac_arrest;
6420

6421
	/* Ethernet MAC address. */
6422
	u_char			eaddr[6];
6423

6424
	/*
6425
	 * These setting are used by the host coalescing (HC) block to
6426
	 * to control how often the status block, statistics block and
6427
	 * interrupts are generated.
6428
	 */
6429
	u16			bce_tx_quick_cons_trip_int;
6430
	u16			bce_tx_quick_cons_trip;
6431
	u16			bce_rx_quick_cons_trip_int;
6432
	u16			bce_rx_quick_cons_trip;
6433
	u16			bce_tx_ticks_int;
6434
	u16			bce_tx_ticks;
6435
	u16			bce_rx_ticks_int;
6436
	u16			bce_rx_ticks;
6437
	u32			bce_stats_ticks;
6438

6439
	/* The address of the integrated PHY on the MII bus. */
6440
	int			bce_phy_addr;
6441

6442
	/* The device handle for the MII bus child device. */
6443
	device_t		bce_miibus;
6444

6445
	/* Driver maintained RX chain pointers and byte counter. */
6446
	u16			rx_prod;
6447
	u16			rx_cons;
6448

6449
	/* Counts the bytes used in the RX chain. */
6450
	u32			rx_prod_bseq;
6451

6452
	/* Driver maintained TX chain pointers and byte counter. */
6453
	u16			tx_prod;
6454
	u16			tx_cons;
6455

6456
	/* Counts the bytes used in the TX chain. */
6457
	u32			tx_prod_bseq;
6458

6459
	/* Driver maintained PG chain pointers. */
6460
	u16			pg_prod;
6461
	u16			pg_cons;
6462

6463
	int			bce_link_up;
6464
	struct		callout bce_tick_callout;
6465
	struct		callout bce_pulse_callout;
6466

6467
	/* Ticks until chip reset */
6468
	int			watchdog_timer;
6469

6470
	/* Frame size and mbuf allocation size for RX frames. */
6471
	int			rx_bd_mbuf_alloc_size;
6472
	int			rx_bd_mbuf_data_len;
6473
	int			rx_bd_mbuf_align_pad;
6474

6475
	/* Receive mode settings (i.e promiscuous, multicast, etc.). */
6476
	u32			rx_mode;
6477

6478
	/* Bus tag for the bce controller. */
6479
	bus_dma_tag_t		parent_tag;
6480

6481
	/* H/W maintained TX buffer descriptor chain structure. */
6482
	int					tx_pages;
6483
	bus_dma_tag_t		tx_bd_chain_tag;
6484
	bus_dmamap_t		tx_bd_chain_map[MAX_TX_PAGES];
6485
	struct tx_bd		*tx_bd_chain[MAX_TX_PAGES];
6486
	bus_addr_t			tx_bd_chain_paddr[MAX_TX_PAGES];
6487

6488
	/* H/W maintained RX buffer descriptor chain structure. */
6489
	int					rx_pages;
6490
	bus_dma_tag_t		rx_bd_chain_tag;
6491
	bus_dmamap_t		rx_bd_chain_map[MAX_RX_PAGES];
6492
	struct rx_bd		*rx_bd_chain[MAX_RX_PAGES];
6493
	bus_addr_t			rx_bd_chain_paddr[MAX_RX_PAGES];
6494

6495
	/* H/W maintained page buffer descriptor chain structure. */
6496
	int					pg_pages;
6497
	bus_dma_tag_t		pg_bd_chain_tag;
6498
	bus_dmamap_t		pg_bd_chain_map[MAX_PG_PAGES];
6499
	struct rx_bd		*pg_bd_chain[MAX_PG_PAGES];
6500
	bus_addr_t			pg_bd_chain_paddr[MAX_PG_PAGES];
6501

6502
	/* H/W maintained status block. */
6503
	bus_dma_tag_t		status_tag;
6504
	bus_dmamap_t		status_map;
6505
	struct status_block	*status_block;
6506
	bus_addr_t			status_block_paddr;
6507

6508
	/* Driver maintained status block values. */
6509
	u16			last_status_idx;
6510
	u16			hw_rx_cons;
6511
	u16			hw_tx_cons;
6512

6513
	/* H/W maintained statistics block. */
6514
	bus_dma_tag_t		stats_tag;
6515
	bus_dmamap_t		stats_map;
6516
	struct statistics_block *stats_block;
6517
	bus_addr_t			stats_block_paddr;
6518

6519
	/* H/W maintained context block. */
6520
	int					ctx_pages;
6521
	bus_dma_tag_t		ctx_tag;
6522

6523
	/* BCM5709/16 use host memory for context. */
6524
	bus_dmamap_t		ctx_map[BCE_MAX_CONTEXT];
6525
	void				*ctx_block[BCE_MAX_CONTEXT];
6526
	bus_addr_t			ctx_paddr[BCE_MAX_CONTEXT];
6527

6528
	/* Bus tag for RX/TX mbufs. */
6529
	bus_dma_tag_t		rx_mbuf_tag;
6530
	bus_dma_tag_t		tx_mbuf_tag;
6531
	bus_dma_tag_t		pg_mbuf_tag;
6532

6533
	/* S/W maintained mbuf TX chain structure. */
6534
	bus_dmamap_t		tx_mbuf_map[MAX_TX_BD_AVAIL];
6535
	struct mbuf			*tx_mbuf_ptr[MAX_TX_BD_AVAIL];
6536

6537
	/* S/W maintained mbuf RX chain structure. */
6538
	bus_dmamap_t		rx_mbuf_map[MAX_RX_BD_AVAIL];
6539
	struct mbuf			*rx_mbuf_ptr[MAX_RX_BD_AVAIL];
6540

6541
	/* S/W maintained mbuf page chain structure. */
6542
	bus_dmamap_t		pg_mbuf_map[MAX_PG_BD_AVAIL];
6543
	struct mbuf			*pg_mbuf_ptr[MAX_PG_BD_AVAIL];
6544

6545
	/* Track the number of buffer descriptors in use. */
6546
	u16			free_rx_bd;
6547
	u16			max_rx_bd;
6548
	u16			used_tx_bd;
6549
	u16			max_tx_bd;
6550
	u16			free_pg_bd;
6551
	u16			max_pg_bd;
6552

6553
	/* Provides access to hardware statistics through sysctl. */
6554
	u64			stat_IfHCInOctets;
6555
	u64			stat_IfHCInBadOctets;
6556
	u64			stat_IfHCOutOctets;
6557
	u64			stat_IfHCOutBadOctets;
6558
	u64			stat_IfHCInUcastPkts;
6559
	u64			stat_IfHCInMulticastPkts;
6560
	u64			stat_IfHCInBroadcastPkts;
6561
	u64			stat_IfHCOutUcastPkts;
6562
	u64			stat_IfHCOutMulticastPkts;
6563
	u64			stat_IfHCOutBroadcastPkts;
6564

6565
	u32	stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
6566
	u32			stat_Dot3StatsCarrierSenseErrors;
6567
	u32			stat_Dot3StatsFCSErrors;
6568
	u32			stat_Dot3StatsAlignmentErrors;
6569
	u32			stat_Dot3StatsSingleCollisionFrames;
6570
	u32			stat_Dot3StatsMultipleCollisionFrames;
6571
	u32			stat_Dot3StatsDeferredTransmissions;
6572
	u32			stat_Dot3StatsExcessiveCollisions;
6573
	u32			stat_Dot3StatsLateCollisions;
6574
	u32			stat_EtherStatsCollisions;
6575
	u32			stat_EtherStatsFragments;
6576
	u32			stat_EtherStatsJabbers;
6577
	u32			stat_EtherStatsUndersizePkts;
6578
	u32			stat_EtherStatsOversizePkts;
6579
	u32			stat_EtherStatsPktsRx64Octets;
6580
	u32			stat_EtherStatsPktsRx65Octetsto127Octets;
6581
	u32			stat_EtherStatsPktsRx128Octetsto255Octets;
6582
	u32			stat_EtherStatsPktsRx256Octetsto511Octets;
6583
	u32			stat_EtherStatsPktsRx512Octetsto1023Octets;
6584
	u32			stat_EtherStatsPktsRx1024Octetsto1522Octets;
6585
	u32			stat_EtherStatsPktsRx1523Octetsto9022Octets;
6586
	u32			stat_EtherStatsPktsTx64Octets;
6587
	u32			stat_EtherStatsPktsTx65Octetsto127Octets;
6588
	u32			stat_EtherStatsPktsTx128Octetsto255Octets;
6589
	u32			stat_EtherStatsPktsTx256Octetsto511Octets;
6590
	u32			stat_EtherStatsPktsTx512Octetsto1023Octets;
6591
	u32			stat_EtherStatsPktsTx1024Octetsto1522Octets;
6592
	u32			stat_EtherStatsPktsTx1523Octetsto9022Octets;
6593
	u32			stat_XonPauseFramesReceived;
6594
	u32			stat_XoffPauseFramesReceived;
6595
	u32			stat_OutXonSent;
6596
	u32			stat_OutXoffSent;
6597
	u32			stat_FlowControlDone;
6598
	u32			stat_MacControlFramesReceived;
6599
	u32			stat_XoffStateEntered;
6600
	u32			stat_IfInFramesL2FilterDiscards;
6601
	u32			stat_IfInRuleCheckerDiscards;
6602
	u32			stat_IfInFTQDiscards;
6603
	u32			stat_IfInMBUFDiscards;
6604
	u32			stat_IfInRuleCheckerP4Hit;
6605
	u32			stat_CatchupInRuleCheckerDiscards;
6606
	u32			stat_CatchupInFTQDiscards;
6607
	u32			stat_CatchupInMBUFDiscards;
6608
	u32			stat_CatchupInRuleCheckerP4Hit;
6609

6610
	/* Provides access to certain firmware statistics. */
6611
	u32			com_no_buffers;
6612

6613
	/* Recoverable failure counters. */
6614
	u32			mbuf_alloc_failed_count;
6615
	u32			mbuf_frag_count;
6616
	u32			unexpected_attention_count;
6617
	u32			l2fhdr_error_count;
6618
	u32			dma_map_addr_tx_failed_count;
6619
	u32			dma_map_addr_rx_failed_count;
6620
	u32			watchdog_timeouts;
6621

6622
	/* Host coalescing block command register */
6623
	u32			hc_command;
6624

6625
	/* Bootcode state */
6626
	u32			bc_state;
6627

6628
#ifdef BCE_DEBUG
6629
	/* Simulated recoverable failure counters. */
6630
	u32			mbuf_alloc_failed_sim_count;
6631
	u32			unexpected_attention_sim_count;
6632
	u32			l2fhdr_error_sim_count;
6633
	u32			dma_map_addr_failed_sim_count;
6634

6635
	/* Track the number of enqueued mbufs. */
6636
	int			debug_tx_mbuf_alloc;
6637
	int			debug_rx_mbuf_alloc;
6638
	int			debug_pg_mbuf_alloc;
6639

6640
	/* Track how many and what type of interrupts are generated. */
6641
	u64			interrupts_generated;
6642
	u64			interrupts_handled;
6643
	u64			interrupts_rx;
6644
	u64			interrupts_tx;
6645
	u64			phy_interrupts;
6646

6647
	/* Lowest number of rx_bd's free. */
6648
	u16			rx_low_watermark;
6649

6650
	/* Number of times the RX chain was empty. */
6651
	u64			rx_empty_count;
6652

6653
	/* Lowest number of pages free. */
6654
	u16			pg_low_watermark;
6655

6656
	/* Number of times the page chain was empty. */
6657
	u64			pg_empty_count;
6658

6659
	/* Greatest number of tx_bd's used. */
6660
	u16			tx_hi_watermark;
6661

6662
	/* Number of times the TX chain was full. */
6663
	u64			tx_full_count;
6664

6665
	/* Number of TSO frames requested. */
6666
	u64			tso_frames_requested;
6667

6668
	/* Number of TSO frames completed. */
6669
	u64			tso_frames_completed;
6670

6671
	/* Number of TSO frames failed. */
6672
	u64			tso_frames_failed;
6673

6674
	/* Number of IP checksum offload frames.*/
6675
	u64			csum_offload_ip;
6676

6677
	/* Number of TCP/UDP checksum offload frames.*/
6678
	u64			csum_offload_tcp_udp;
6679

6680
	/* Number of VLAN tagged frames received. */
6681
	u64			vlan_tagged_frames_rcvd;
6682

6683
	/* Number of VLAN tagged frames stripped. */
6684
	u64			vlan_tagged_frames_stripped;
6685

6686
	/* Number of split header frames received. */
6687
	u64			split_header_frames_rcvd;
6688

6689
	/* Number of split header TCP frames received. */
6690
	u64			split_header_tcp_frames_rcvd;
6691

6692
	/* Buffer with NVRAM contents for the NIC. */
6693
	u8			*nvram_buf;
6694
#endif /* BCE_DEBUG */
6695
};
6696

6697
#endif /* __BCEREG_H_DEFINED */
6698

6699
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