#include <sys/cdefs.h>
#ifndef ECORE_HSI_H
#define ECORE_HSI_H
#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
struct license_key {
uint32_t reserved[6];
uint32_t max_iscsi_conn;
#define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
#define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
#define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
#define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16
uint32_t reserved_a;
uint32_t max_fcoe_conn;
#define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
#define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
#define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
#define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16
uint32_t reserved_b[4];
};
typedef struct license_key license_key_t;
#define PIN_CFG_NA 0x00000000
#define PIN_CFG_GPIO0_P0 0x00000001
#define PIN_CFG_GPIO1_P0 0x00000002
#define PIN_CFG_GPIO2_P0 0x00000003
#define PIN_CFG_GPIO3_P0 0x00000004
#define PIN_CFG_GPIO0_P1 0x00000005
#define PIN_CFG_GPIO1_P1 0x00000006
#define PIN_CFG_GPIO2_P1 0x00000007
#define PIN_CFG_GPIO3_P1 0x00000008
#define PIN_CFG_EPIO0 0x00000009
#define PIN_CFG_EPIO1 0x0000000a
#define PIN_CFG_EPIO2 0x0000000b
#define PIN_CFG_EPIO3 0x0000000c
#define PIN_CFG_EPIO4 0x0000000d
#define PIN_CFG_EPIO5 0x0000000e
#define PIN_CFG_EPIO6 0x0000000f
#define PIN_CFG_EPIO7 0x00000010
#define PIN_CFG_EPIO8 0x00000011
#define PIN_CFG_EPIO9 0x00000012
#define PIN_CFG_EPIO10 0x00000013
#define PIN_CFG_EPIO11 0x00000014
#define PIN_CFG_EPIO12 0x00000015
#define PIN_CFG_EPIO13 0x00000016
#define PIN_CFG_EPIO14 0x00000017
#define PIN_CFG_EPIO15 0x00000018
#define PIN_CFG_EPIO16 0x00000019
#define PIN_CFG_EPIO17 0x0000001a
#define PIN_CFG_EPIO18 0x0000001b
#define PIN_CFG_EPIO19 0x0000001c
#define PIN_CFG_EPIO20 0x0000001d
#define PIN_CFG_EPIO21 0x0000001e
#define PIN_CFG_EPIO22 0x0000001f
#define PIN_CFG_EPIO23 0x00000020
#define PIN_CFG_EPIO24 0x00000021
#define PIN_CFG_EPIO25 0x00000022
#define PIN_CFG_EPIO26 0x00000023
#define PIN_CFG_EPIO27 0x00000024
#define PIN_CFG_EPIO28 0x00000025
#define PIN_CFG_EPIO29 0x00000026
#define PIN_CFG_EPIO30 0x00000027
#define PIN_CFG_EPIO31 0x00000028
#define EPIO_CFG_NA 0x00000000
#define EPIO_CFG_EPIO0 0x00000001
#define EPIO_CFG_EPIO1 0x00000002
#define EPIO_CFG_EPIO2 0x00000003
#define EPIO_CFG_EPIO3 0x00000004
#define EPIO_CFG_EPIO4 0x00000005
#define EPIO_CFG_EPIO5 0x00000006
#define EPIO_CFG_EPIO6 0x00000007
#define EPIO_CFG_EPIO7 0x00000008
#define EPIO_CFG_EPIO8 0x00000009
#define EPIO_CFG_EPIO9 0x0000000a
#define EPIO_CFG_EPIO10 0x0000000b
#define EPIO_CFG_EPIO11 0x0000000c
#define EPIO_CFG_EPIO12 0x0000000d
#define EPIO_CFG_EPIO13 0x0000000e
#define EPIO_CFG_EPIO14 0x0000000f
#define EPIO_CFG_EPIO15 0x00000010
#define EPIO_CFG_EPIO16 0x00000011
#define EPIO_CFG_EPIO17 0x00000012
#define EPIO_CFG_EPIO18 0x00000013
#define EPIO_CFG_EPIO19 0x00000014
#define EPIO_CFG_EPIO20 0x00000015
#define EPIO_CFG_EPIO21 0x00000016
#define EPIO_CFG_EPIO22 0x00000017
#define EPIO_CFG_EPIO23 0x00000018
#define EPIO_CFG_EPIO24 0x00000019
#define EPIO_CFG_EPIO25 0x0000001a
#define EPIO_CFG_EPIO26 0x0000001b
#define EPIO_CFG_EPIO27 0x0000001c
#define EPIO_CFG_EPIO28 0x0000001d
#define EPIO_CFG_EPIO29 0x0000001e
#define EPIO_CFG_EPIO30 0x0000001f
#define EPIO_CFG_EPIO31 0x00000020
struct mac_addr {
uint32_t upper;
uint32_t lower;
};
struct shared_hw_cfg {
uint8_t part_num[16];
uint32_t config;
#define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
#define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
#define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
#define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
#define SHARED_HW_CFG_PORT_SWAP 0x00000004
#define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
#define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
#define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
#define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
#define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
#define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
#define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
#define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
#define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
#define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
#define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000
#define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12
#define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000
#define SHARED_HW_CFG_LED_MODE_SHIFT 16
#define SHARED_HW_CFG_LED_MAC1 0x00000000
#define SHARED_HW_CFG_LED_PHY1 0x00010000
#define SHARED_HW_CFG_LED_PHY2 0x00020000
#define SHARED_HW_CFG_LED_PHY3 0x00030000
#define SHARED_HW_CFG_LED_MAC2 0x00040000
#define SHARED_HW_CFG_LED_PHY4 0x00050000
#define SHARED_HW_CFG_LED_PHY5 0x00060000
#define SHARED_HW_CFG_LED_PHY6 0x00070000
#define SHARED_HW_CFG_LED_MAC3 0x00080000
#define SHARED_HW_CFG_LED_PHY7 0x00090000
#define SHARED_HW_CFG_LED_PHY9 0x000a0000
#define SHARED_HW_CFG_LED_PHY11 0x000b0000
#define SHARED_HW_CFG_LED_MAC4 0x000c0000
#define SHARED_HW_CFG_LED_PHY8 0x000d0000
#define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
#define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000
#define SHARED_HW_CFG_SRIOV_MASK 0x40000000
#define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
#define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
#define SHARED_HW_CFG_ATC_MASK 0x80000000
#define SHARED_HW_CFG_ATC_DISABLED 0x00000000
#define SHARED_HW_CFG_ATC_ENABLED 0x80000000
uint32_t config2;
#define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100
#define SHARED_HW_CFG_PCIE_GEN2_SHIFT 8
#define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
#define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
#define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
#define SHARED_HW_CFG_HIDE_PORT1 0x00002000
#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
#define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
#define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
#define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
#define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
#define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
#define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
#define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
#define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
#define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
#define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
#define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
uint32_t config_3;
#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F
#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0
#define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00
#define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8
#define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000
#define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100
uint32_t ump_nc_si_config;
#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
uint32_t board;
#define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
#define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
#define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
#define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
#define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000
#define SHARED_HW_CFG_BOARD_REV_SHIFT 16
#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000
#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000
#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
uint32_t wc_lane_config;
#define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
#define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
#define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
#define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
#define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8
#define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827
#define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
#define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
#define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
#define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
#define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
#define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
#define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
#define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
#define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
#define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
#define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
#define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
#define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
#define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
#define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
#define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
#define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
#define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
#define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01_SIG 0x06000000
};
struct port_hw_cfg {
uint32_t pci_id;
#define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF
#define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0
#define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000
#define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16
uint32_t pci_sub_id;
#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF
#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0
#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000
#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16
uint32_t power_dissipated;
#define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF
#define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
#define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00
#define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
#define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000
#define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
#define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000
#define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
uint32_t power_consumed;
#define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF
#define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
#define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00
#define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
#define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000
#define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
#define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000
#define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
uint32_t mac_upper;
uint32_t mac_lower;
#define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF
#define PORT_HW_CFG_UPPERMAC_SHIFT 0
uint32_t iscsi_mac_upper;
uint32_t iscsi_mac_lower;
uint32_t rdma_mac_upper;
uint32_t rdma_mac_lower;
uint32_t serdes_config;
#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000
#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
uint32_t reserved;
uint32_t vf_config;
#define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
#define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
uint32_t mf_pci_id;
#define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
#define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
uint32_t sfp_ctrl;
#define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
#define PORT_HW_CFG_TX_LASER_SHIFT 0
#define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
#define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
#define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
#define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
#define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
#define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
#define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
#define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
uint32_t e3_sfp_ctrl;
#define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
#define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
#define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
#define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
#define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
#define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
#define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
#define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
uint32_t e3_cmn_pin_cfg;
#define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
#define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
#define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
#define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
#define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
#define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
#define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
#define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
uint32_t e3_cmn_pin_cfg1;
#define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
#define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
uint32_t generic_features;
#define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001
#define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0
#define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000
#define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001
uint32_t sfi_tap_values;
#define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF
#define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0
#define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000
#define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16
#define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000
#define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20
#define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000
#define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT 24
#define PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000
#define PORT_HW_CFG_TX_DRV_POST2_SHIFT 28
uint32_t reserved0[5];
uint32_t aeu_int_mask;
uint32_t media_type;
#define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
#define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
#define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
#define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
#define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
#define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
uint16_t xgxs_config_rx[4];
uint16_t xgxs_config_tx[4];
uint32_t fcoe_fip_mac_upper;
#define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
#define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
uint32_t fcoe_fip_mac_lower;
uint32_t fcoe_wwn_port_name_upper;
uint32_t fcoe_wwn_port_name_lower;
uint32_t fcoe_wwn_node_name_upper;
uint32_t fcoe_wwn_node_name_lower;
uint32_t wwpn_for_npiv_config;
#define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001
#define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0
#define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000
#define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001
uint32_t wwpn_for_npiv_valid_addresses;
#define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF
#define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0
struct mac_addr wwpn_for_niv_macs[16];
uint32_t Reserved1[14];
uint32_t pf_allocation;
#define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF
#define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0
uint32_t xgbt_phy_cfg;
#define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
#define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
uint32_t default_cfg;
#define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
#define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
#define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
#define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
#define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
#define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
#define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
#define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
#define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
#define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
#define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
#define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
#define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
#define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
#define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
#define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
#define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
#define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
#define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
#define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
#define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
#define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
#define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
#define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
#define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
#define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
#define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
#define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
#define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
#define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
#define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
#define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
#define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
#define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
#define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
#define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
#define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
#define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
#define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
#define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
#define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
#define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
#define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
#define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
#define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
#define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
#define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
#define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000
#define PORT_HW_CFG_TAP_LEVELS_SHIFT 28
#define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000
#define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000
#define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000
#define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000
#define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000
#define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000
uint32_t speed_capability_mask2;
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
uint32_t multi_phy_config;
#define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
#define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
#define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
#define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
#define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
#define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
#define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
uint32_t external_phy_config2;
#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84858 0x00001200
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
uint16_t xgxs_config2_rx[4];
uint16_t xgxs_config2_tx[4];
uint32_t lane_config;
#define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
#define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
#define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
#define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
#define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
#define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
#define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
#define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
#define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
#define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000
#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
#define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
#define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
#define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
uint32_t external_phy_config;
#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF
#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858 0x00001200
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000
#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000
#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
uint32_t speed_capability_mask;
#define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF
#define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
#define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
#define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
#define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
#define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
#define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
uint32_t backup_mac_upper;
uint32_t backup_mac_lower;
};
struct shared_feat_cfg {
uint32_t config;
#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
0x00000002
#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
0x00000000
#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
0x00000002
#define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
#define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
#define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
#define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
#define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
#define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
#define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
#define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
#define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
#define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
#define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500
#define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600
#define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700
#define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000
#define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000
#define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000
#define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14
#define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000
#define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000
#define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000
#define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
#define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000
#define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
};
struct port_feat_cfg {
uint32_t config;
#define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F
#define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0
#define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000
#define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001
#define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002
#define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003
#define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004
#define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005
#define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006
#define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007
#define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008
#define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009
#define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a
#define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b
#define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c
#define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d
#define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e
#define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f
#define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0
#define PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4
#define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000
#define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010
#define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020
#define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030
#define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040
#define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050
#define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060
#define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070
#define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080
#define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090
#define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0
#define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0
#define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0
#define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0
#define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0
#define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0
#define PORT_FEAT_CFG_DCBX_MASK 0x00000100
#define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
#define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
#define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200
#define PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9
#define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000
#define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200
#define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00
#define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10
#define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000
#define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400
#define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800
#define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00
#define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
#define PORT_FEATURE_EN_SIZE_SHIFT 24
#define PORT_FEATURE_WOL_ENABLED 0x01000000
#define PORT_FEATURE_MBA_ENABLED 0x02000000
#define PORT_FEATURE_MFW_ENABLED 0x04000000
#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000
#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
0x00000000
#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
0x20000000
#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
uint32_t wol_config;
#define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
uint32_t mba_config;
#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
#define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
#define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
#define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
#define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
#define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
#define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
#define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000
#define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
#define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000
#define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
#define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
#define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000
#define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000
#define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000
#define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000
#define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000
#define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000
#define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000
#define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000
uint32_t Reserved0;
uint32_t mba_vlan_cfg;
#define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF
#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
#define PORT_FEATURE_MBA_VLAN_EN 0x00010000
#define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000
#define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000
#define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000
uint32_t Reserved1;
uint32_t smbus_config;
#define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
#define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
uint32_t vf_config;
#define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F
#define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
#define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
#define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
#define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
#define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
#define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
#define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
#define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
#define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
#define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
#define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
#define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
#define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
#define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
#define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
#define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
#define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
uint32_t link_config;
#define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
#define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
#define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
#define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
#define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
#define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
#define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
#define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500
#define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600
#define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700
#define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000
#define PORT_FEATURE_LINK_SPEED_SHIFT 16
#define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
#define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000
#define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000
#define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
#define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
#define PORT_FEATURE_LINK_SPEED_1G 0x00050000
#define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
#define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
#define PORT_FEATURE_LINK_SPEED_20G 0x00080000
#define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
#define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
#define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
#define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
#define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
#define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
uint32_t mfw_wol_link_cfg;
uint32_t link_config2;
uint32_t mfw_wol_link_cfg2;
uint32_t eee_power_mode;
#define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF
#define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0
#define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000
#define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001
#define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002
#define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
uint32_t Reserved2[16];
};
struct shm_dev_info {
uint32_t bc_rev;
struct shared_hw_cfg shared_hw_config;
struct port_hw_cfg port_hw_config[PORT_MAX];
struct shared_feat_cfg shared_feature_config;
struct port_feat_cfg port_feature_config[PORT_MAX];
};
struct extended_dev_info_shared_cfg {
uint32_t temperature_monitor1;
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000
uint32_t temperature_monitor2;
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0
#define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_MASK 0x00030000
#define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_SHIFT 16
#define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_BSC 0x00010000
#define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_MASK 0x03FC0000
#define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_SHIFT 18
uint32_t mfw_cfg;
#define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF
#define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0
#define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001
#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100
#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8
#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100
#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_MASK 0x00000200
#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_SHIFT 9
#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_ENABLED 0x00000200
#define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_MASK 0x00000400
#define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_SHIFT 10
#define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_ENABLED 0x00000400
#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000
#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16
#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000
uint32_t smbus_config;
#define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF
#define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0
uint32_t board_cfg;
#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F
#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0
#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008
#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009
#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a
#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b
#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c
#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d
#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e
#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f
#define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100
#define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8
#define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100
#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200
#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9
#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200
#define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400
#define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10
#define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400
#define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_MASK 0x00000800
#define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_SHIFT 11
#define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_ENABLED 0x00000800
#define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_MASK 0x00003000
#define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_SHIFT 12
#define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_PRESERVE 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_ACTUAL 0x00001000
#define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B0 0x00002000
#define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B1 0x00003000
uint32_t temperature_report;
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00
#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8
uint32_t wwn_prefix;
#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF
#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0
#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00
#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8
#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000
#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16
#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000
#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24
uint32_t dbg_cfg_flags;
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000
#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_MASK 0x00100000
#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_SHIFT 20
#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_ENABLED 0x00100000
uint32_t dbg_rx_sigdet_threshold;
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0
uint32_t iffe_features;
#define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001
#define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0
#define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001
#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E
#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1
#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010
#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4
#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010
#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020
#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5
#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020
#define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000
#define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15
#define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000
uint32_t current_iffe_mask;
#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E
#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1
#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010
#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4
#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010
#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020
#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5
#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020
uint32_t threshold_pin;
#define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF
#define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0
#define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00
#define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8
#define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000
#define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16
uint32_t mac_threshold_val;
#define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF
#define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0
#define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00
#define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8
#define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000
#define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16
uint32_t phy_threshold_val;
#define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF
#define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0
#define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00
#define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8
#define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000
#define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16
uint32_t host_pin;
#define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF
#define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0
#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00
#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8
#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000
#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16
#define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000
#define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24
uint32_t manufacture_ver;
uint32_t manufacture_data;
#define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_MASK 0x00040000
#define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_SHIFT18
#define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_2 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_4 0x00040000
uint32_t mcp_crash_dump;
#define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_MASK 0x7FFFFFFF
#define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_SHIFT 0
#define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_DISABLED 0x00000000
#define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_ENABLED 0x00000001
uint32_t mbi_version;
uint32_t mbi_date;
};
#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
#error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
#endif
#define FUNC_0 0
#define FUNC_1 1
#define FUNC_2 2
#define FUNC_3 3
#define FUNC_4 4
#define FUNC_5 5
#define FUNC_6 6
#define FUNC_7 7
#define E1_FUNC_MAX 2
#define E1H_FUNC_MAX 8
#define E2_FUNC_MAX 4
#define VN_0 0
#define VN_1 1
#define VN_2 2
#define VN_3 3
#define E1VN_MAX 1
#define E1HVN_MAX 4
#define E2_VF_MAX 64
#define DRV_PULSE_PERIOD_MS 250
#define FW_ACK_TIME_OUT_MS 5000
#define FW_ACK_POLL_TIME_MS 1
#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
#define MFW_TRACE_SIGNATURE 0x54524342
struct drv_port_mb {
uint32_t link_status;
#define LINK_STATUS_NONE (0<<0)
#define LINK_STATUS_LINK_FLAG_MASK 0x00000001
#define LINK_STATUS_LINK_UP 0x00000001
#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
#define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
#define LINK_STATUS_SERDES_LINK 0x00100000
#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
#define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
#define LINK_STATUS_PFC_ENABLED 0x20000000
#define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
#define LINK_STATUS_SFP_TX_FAULT 0x80000000
uint32_t port_stx;
uint32_t stat_nig_timer;
uint32_t ext_phy_fw_version;
};
struct drv_func_mb {
uint32_t drv_mb_header;
#define DRV_MSG_CODE_MASK 0xffff0000
#define DRV_MSG_CODE_LOAD_REQ 0x10000000
#define DRV_MSG_CODE_LOAD_DONE 0x11000000
#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
#define DRV_MSG_CODE_DCC_OK 0x30000000
#define DRV_MSG_CODE_DCC_FAILURE 0x31000000
#define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
#define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
#define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
#define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
#define DRV_MSG_CODE_OEM_OK 0x00010000
#define DRV_MSG_CODE_OEM_FAILURE 0x00020000
#define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000
#define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000
#define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
#define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
#define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
#define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
#define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000
#define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002
#define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
#define REQ_BC_VER_4_MT_SUPPORTED 0x00070201
#define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
#define REQ_BC_VER_4_FCOE_FEATURES 0x00070209
#define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
#define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
#define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401
#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
#define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000
#define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000
#define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000
#define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000
#define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000
#define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
#define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
#define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000
#define DRV_MSG_CODE_RMMOD 0xdb000000
#define REQ_BC_VER_4_RMMOD_CMD 0x0007080f
#define DRV_MSG_CODE_SET_MF_BW 0xe0000000
#define REQ_BC_VER_4_SET_MF_BW 0x00060202
#define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
#define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
#define DRV_MSG_CODE_INITIATE_FLR 0x02000000
#define REQ_BC_VER_4_INITIATE_FLR 0x00070213
#define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
#define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
#define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
#define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
#define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000
#define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000
#define DRV_MSG_CODE_UFP_CONFIG_ACK 0xe4000000
#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
#define DRV_MSG_CODE_CONFIG_CHANGE 0xC1000000
uint32_t drv_mb_param;
#define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
#define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
#define DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001
#define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002
#define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a
#define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000
#define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001
#define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002
#define DRV_MSG_CODE_VPD_IMAGE_REQ 0x00000003
#define DRV_MSG_CODE_CONFIG_CHANGE_MTU_SIZE 0x00000001
#define DRV_MSG_CODE_CONFIG_CHANGE_MAC_ADD 0x00000002
#define DRV_MSG_CODE_CONFIG_CHANGE_WOL_ENA 0x00000003
#define DRV_MSG_CODE_CONFIG_CHANGE_ISCI_BOOT 0x00000004
#define DRV_MSG_CODE_CONFIG_CHANGE_FCOE_BOOT 0x00000005
uint32_t fw_mb_header;
#define FW_MSG_CODE_MASK 0xffff0000
#define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
#define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
#define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
#define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
#define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
#define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
#define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
#define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
#define FW_MSG_CODE_DCC_DONE 0x30100000
#define FW_MSG_CODE_LLDP_DONE 0x40100000
#define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
#define FW_MSG_CODE_DIAG_REFUSE 0x50200000
#define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
#define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
#define FW_MSG_CODE_GET_KEY_DONE 0x80100000
#define FW_MSG_CODE_NO_KEY 0x80f00000
#define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
#define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
#define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
#define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
#define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
#define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
#define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000
#define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000
#define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000
#define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000
#define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000
#define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000
#define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
#define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
#define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000
#define FW_MSG_CODE_RMMOD_ACK 0xdb100000
#define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
#define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
#define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
#define FW_MSG_CODE_FLR_ACK 0x02000000
#define FW_MSG_CODE_FLR_NACK 0x02100000
#define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
#define FW_MSG_CODE_LIC_RESPONSE 0xff020000
#define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
#define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
#define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000
#define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000
#define FW_MSG_CODE_OEM_ACK 0x00010000
#define DRV_MSG_CODE_OEM_UPDATE_SVID_ACK 0x00020000
#define FW_MSG_CODE_CONFIG_CHANGE_DONE 0xC2000000
#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
uint32_t fw_mb_param;
#define FW_PARAM_INVALID_IMG 0xffffffff
uint32_t drv_pulse_mb;
#define DRV_PULSE_SEQ_MASK 0x00007fff
#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
uint32_t mcp_pulse_mb;
#define MCP_PULSE_SEQ_MASK 0x00007fff
#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
#define MCP_EVENT_MASK 0xffff0000
#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
uint32_t iscsi_boot_signature;
uint32_t iscsi_boot_block_offset;
uint32_t drv_status;
#define DRV_STATUS_PMF 0x00000001
#define DRV_STATUS_VF_DISABLED 0x00000002
#define DRV_STATUS_SET_MF_BW 0x00000004
#define DRV_STATUS_LINK_EVENT 0x00000008
#define DRV_STATUS_OEM_EVENT_MASK 0x00000070
#define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010
#define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020
#define DRV_STATUS_OEM_FC_NPIV_UPDATE 0x00000040
#define DRV_STATUS_OEM_UPDATE_SVID 0x00000080
#define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
#define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
#define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
#define DRV_STATUS_DCC_RESERVED1 0x00000800
#define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
#define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
#define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
#define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
#define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000
#define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000
#define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000
#define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000
#define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000
#define DRV_STATUS_DRV_INFO_REQ 0x04000000
#define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000
uint32_t virt_mac_upper;
#define VIRT_MAC_SIGN_MASK 0xffff0000
#define VIRT_MAC_SIGNATURE 0x564d0000
uint32_t virt_mac_lower;
};
#define MGMTFW_STATE_WORD_SIZE 110
struct mgmtfw_state {
uint32_t opaque[MGMTFW_STATE_WORD_SIZE];
};
struct shared_mf_cfg {
uint32_t clp_mb;
#define SHARED_MF_CLP_SET_DEFAULT 0x00000000
#define SHARED_MF_CLP_EXIT 0x00000001
#define SHARED_MF_CLP_EXIT_DONE 0x00010000
};
struct port_mf_cfg {
uint32_t dynamic_cfg;
#define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
#define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
#define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
uint32_t reserved[1];
};
struct func_mf_cfg {
uint32_t config;
#define FUNC_MF_CFG_FUNC_HIDE 0x00000001
#define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
#define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
#define FUNC_MF_CFG_PROTOCOL_DEFAULT \
FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
#define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
#define FUNC_MF_CFG_FUNC_DELETED 0x00000010
#define FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060
#define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000
#define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020
#define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040
#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
#define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
#define FUNC_MF_CFG_MIN_BW_SHIFT 16
#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
#define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
#define FUNC_MF_CFG_MAX_BW_SHIFT 24
#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
uint32_t mac_upper;
#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
#define FUNC_MF_CFG_UPPERMAC_SHIFT 0
#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
uint32_t mac_lower;
#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
uint32_t e1hov_tag;
#define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
#define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
#define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000
#define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16
uint32_t afex_config;
#define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff
#define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0
#define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00
#define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8
#define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100
#define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000
#define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16
uint32_t pf_allocation;
#define FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF
#define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0
};
enum mf_cfg_afex_vlan_mode {
FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
};
struct func_ext_cfg {
uint32_t func_cfg;
#define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F
#define MACP_FUNC_CFG_FLAGS_SHIFT 0
#define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
#define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
#define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
#define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
#define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080
uint32_t iscsi_mac_addr_upper;
uint32_t iscsi_mac_addr_lower;
uint32_t fcoe_mac_addr_upper;
uint32_t fcoe_mac_addr_lower;
uint32_t fcoe_wwn_port_name_upper;
uint32_t fcoe_wwn_port_name_lower;
uint32_t fcoe_wwn_node_name_upper;
uint32_t fcoe_wwn_node_name_lower;
uint32_t preserve_data;
#define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
#define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
#define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
#define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
};
struct mf_cfg {
struct shared_mf_cfg shared_mf_config;
struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX];
struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
struct func_ext_cfg func_ext_config[E1H_FUNC_MAX];
};
struct shmem_region {
uint32_t validity_map[PORT_MAX];
#define SHR_MEM_FORMAT_REV_MASK 0xff000000
#define SHR_MEM_FORMAT_REV_ID ('A'<<24)
#define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
#define SHR_MEM_VALIDITY_MB 0x00200000
#define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
#define SHR_MEM_VALIDITY_RESERVED 0x00000007
#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
#define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
#define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
#define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
#define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
#define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
#define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
struct shm_dev_info dev_info;
license_key_t drv_lic_key[PORT_MAX];
uint32_t fw_info_fio_offset;
struct mgmtfw_state mgmtfw_state;
struct drv_port_mb port_mb[PORT_MAX];
#ifdef BMAPI
struct drv_func_mb func_mb[1];
#else
struct drv_func_mb func_mb[];
#endif
};
struct fw_flr_ack {
uint32_t pf_ack;
uint32_t vf_ack;
uint32_t iov_dis_ack;
};
struct fw_flr_mb {
uint32_t aggint;
uint32_t opgen_addr;
struct fw_flr_ack ack;
};
struct eee_remote_vals {
uint32_t tx_tw;
uint32_t rx_tw;
};
#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
#define SHMEM_ARRAY_BITPOS(i, eb, fb) \
((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
(((i)%((fb)/(eb))) * (eb)))
#define SHMEM_ARRAY_GET(a, i, eb, fb) \
((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
SHMEM_ARRAY_MASK(eb))
#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
do { \
a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
SHMEM_ARRAY_BITPOS(i, eb, fb)); \
a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
SHMEM_ARRAY_BITPOS(i, eb, fb)); \
} while (0)
#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
#define DCBX_PRI_PG_BITWIDTH 4
#define DCBX_PRI_PG_FBITS 8
#define DCBX_PRI_PG_GET(a, i) \
SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
#define DCBX_PRI_PG_SET(a, i, val) \
SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
#define DCBX_MAX_NUM_PG_BW_ENTRIES 8
#define DCBX_BW_PG_BITWIDTH 8
#define DCBX_PG_BW_GET(a, i) \
SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
#define DCBX_PG_BW_SET(a, i, val) \
SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
#define DCBX_STRICT_PRI_PG 15
#define DCBX_MAX_APP_PROTOCOL 16
#define DCBX_MAX_APP_LOCAL 32
#define FCOE_APP_IDX 0
#define ISCSI_APP_IDX 1
#define PREDEFINED_APP_IDX_MAX 2
struct dcbx_ets_feature {
uint32_t enabled;
uint32_t pg_bw_tbl[2];
uint32_t pri_pg_tbl[1];
};
struct dcbx_pfc_feature {
#ifdef __BIG_ENDIAN
uint8_t pri_en_bitmap;
#define DCBX_PFC_PRI_0 0x01
#define DCBX_PFC_PRI_1 0x02
#define DCBX_PFC_PRI_2 0x04
#define DCBX_PFC_PRI_3 0x08
#define DCBX_PFC_PRI_4 0x10
#define DCBX_PFC_PRI_5 0x20
#define DCBX_PFC_PRI_6 0x40
#define DCBX_PFC_PRI_7 0x80
uint8_t pfc_caps;
uint8_t reserved;
uint8_t enabled;
#elif defined(__LITTLE_ENDIAN)
uint8_t enabled;
uint8_t reserved;
uint8_t pfc_caps;
uint8_t pri_en_bitmap;
#define DCBX_PFC_PRI_0 0x01
#define DCBX_PFC_PRI_1 0x02
#define DCBX_PFC_PRI_2 0x04
#define DCBX_PFC_PRI_3 0x08
#define DCBX_PFC_PRI_4 0x10
#define DCBX_PFC_PRI_5 0x20
#define DCBX_PFC_PRI_6 0x40
#define DCBX_PFC_PRI_7 0x80
#endif
};
struct dcbx_app_priority_entry {
#ifdef __BIG_ENDIAN
uint16_t app_id;
uint8_t pri_bitmap;
uint8_t appBitfield;
#define DCBX_APP_ENTRY_VALID 0x01
#define DCBX_APP_ENTRY_SF_MASK 0x30
#define DCBX_APP_ENTRY_SF_SHIFT 4
#define DCBX_APP_SF_ETH_TYPE 0x10
#define DCBX_APP_SF_PORT 0x20
#define DCBX_APP_PRI_0 0x01
#define DCBX_APP_PRI_1 0x02
#define DCBX_APP_PRI_2 0x04
#define DCBX_APP_PRI_3 0x08
#define DCBX_APP_PRI_4 0x10
#define DCBX_APP_PRI_5 0x20
#define DCBX_APP_PRI_6 0x40
#define DCBX_APP_PRI_7 0x80
#elif defined(__LITTLE_ENDIAN)
uint8_t appBitfield;
#define DCBX_APP_ENTRY_VALID 0x01
#define DCBX_APP_ENTRY_SF_MASK 0x30
#define DCBX_APP_ENTRY_SF_SHIFT 4
#define DCBX_APP_SF_ETH_TYPE 0x10
#define DCBX_APP_SF_PORT 0x20
uint8_t pri_bitmap;
uint16_t app_id;
#endif
};
struct dcbx_app_priority_feature {
#ifdef __BIG_ENDIAN
uint8_t reserved;
uint8_t default_pri;
uint8_t tc_supported;
uint8_t enabled;
#elif defined(__LITTLE_ENDIAN)
uint8_t enabled;
uint8_t tc_supported;
uint8_t default_pri;
uint8_t reserved;
#endif
struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
};
struct dcbx_features {
struct dcbx_ets_feature ets;
struct dcbx_pfc_feature pfc;
struct dcbx_app_priority_feature app;
};
struct lldp_params {
#ifdef __BIG_ENDIAN
uint8_t msg_fast_tx_interval;
uint8_t msg_tx_hold;
uint8_t msg_tx_interval;
uint8_t admin_status;
#define LLDP_TX_ONLY 0x01
#define LLDP_RX_ONLY 0x02
#define LLDP_TX_RX 0x03
#define LLDP_DISABLED 0x04
uint8_t reserved1;
uint8_t tx_fast;
uint8_t tx_crd_max;
uint8_t tx_crd;
#elif defined(__LITTLE_ENDIAN)
uint8_t admin_status;
#define LLDP_TX_ONLY 0x01
#define LLDP_RX_ONLY 0x02
#define LLDP_TX_RX 0x03
#define LLDP_DISABLED 0x04
uint8_t msg_tx_interval;
uint8_t msg_tx_hold;
uint8_t msg_fast_tx_interval;
uint8_t tx_crd;
uint8_t tx_crd_max;
uint8_t tx_fast;
uint8_t reserved1;
#endif
#define REM_CHASSIS_ID_STAT_LEN 4
#define REM_PORT_ID_STAT_LEN 4
uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
uint32_t peer_port_id[REM_PORT_ID_STAT_LEN];
};
struct lldp_dcbx_stat {
#define LOCAL_CHASSIS_ID_STAT_LEN 2
#define LOCAL_PORT_ID_STAT_LEN 2
uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN];
uint32_t num_tx_dcbx_pkts;
uint32_t num_rx_dcbx_pkts;
};
struct lldp_admin_mib {
uint32_t ver_cfg_flags;
#define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
#define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
#define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
#define DCBX_ETS_RECO_TX_ENABLED 0x00000008
#define DCBX_ETS_RECO_VALID 0x00000010
#define DCBX_ETS_WILLING 0x00000020
#define DCBX_PFC_WILLING 0x00000040
#define DCBX_APP_WILLING 0x00000080
#define DCBX_VERSION_CEE 0x00000100
#define DCBX_VERSION_IEEE 0x00000200
#define DCBX_DCBX_ENABLED 0x00000400
#define DCBX_CEE_VERSION_MASK 0x0000f000
#define DCBX_CEE_VERSION_SHIFT 12
#define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
#define DCBX_CEE_MAX_VERSION_SHIFT 16
struct dcbx_features features;
};
struct lldp_remote_mib {
uint32_t prefix_seq_num;
uint32_t flags;
#define DCBX_ETS_TLV_RX 0x00000001
#define DCBX_PFC_TLV_RX 0x00000002
#define DCBX_APP_TLV_RX 0x00000004
#define DCBX_ETS_RX_ERROR 0x00000010
#define DCBX_PFC_RX_ERROR 0x00000020
#define DCBX_APP_RX_ERROR 0x00000040
#define DCBX_ETS_REM_WILLING 0x00000100
#define DCBX_PFC_REM_WILLING 0x00000200
#define DCBX_APP_REM_WILLING 0x00000400
#define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
#define DCBX_REMOTE_MIB_VALID 0x00002000
struct dcbx_features features;
uint32_t suffix_seq_num;
};
struct lldp_local_mib {
uint32_t prefix_seq_num;
uint32_t error;
#define DCBX_LOCAL_ETS_ERROR 0x00000001
#define DCBX_LOCAL_PFC_ERROR 0x00000002
#define DCBX_LOCAL_APP_ERROR 0x00000004
#define DCBX_LOCAL_PFC_MISMATCH 0x00000010
#define DCBX_LOCAL_APP_MISMATCH 0x00000020
#define DCBX_REMOTE_MIB_ERROR 0x00000040
#define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
#define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
#define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
struct dcbx_features features;
uint32_t suffix_seq_num;
};
struct lldp_local_mib_ext {
uint32_t prefix_seq_num;
struct dcbx_app_priority_entry app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL];
uint32_t suffix_seq_num;
};
#define SHMEM_LINK_CONFIG_SIZE 2
struct shmem_lfa {
uint32_t req_duplex;
#define REQ_DUPLEX_PHY0_MASK 0x0000ffff
#define REQ_DUPLEX_PHY0_SHIFT 0
#define REQ_DUPLEX_PHY1_MASK 0xffff0000
#define REQ_DUPLEX_PHY1_SHIFT 16
uint32_t req_flow_ctrl;
#define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff
#define REQ_FLOW_CTRL_PHY0_SHIFT 0
#define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000
#define REQ_FLOW_CTRL_PHY1_SHIFT 16
uint32_t req_line_speed;
#define REQ_LINE_SPD_PHY0_MASK 0x0000ffff
#define REQ_LINE_SPD_PHY0_SHIFT 0
#define REQ_LINE_SPD_PHY1_MASK 0xffff0000
#define REQ_LINE_SPD_PHY1_SHIFT 16
uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
uint32_t additional_config;
#define REQ_FC_AUTO_ADV_MASK 0x0000ffff
#define REQ_FC_AUTO_ADV0_SHIFT 0
#define NO_LFA_DUE_TO_DCC_MASK 0x00010000
uint32_t lfa_sts;
#define LFA_LINK_FLAP_REASON_OFFSET 0
#define LFA_LINK_FLAP_REASON_MASK 0x000000ff
#define LFA_LINK_DOWN 0x1
#define LFA_LOOPBACK_ENABLED 0x2
#define LFA_DUPLEX_MISMATCH 0x3
#define LFA_MFW_IS_TOO_OLD 0x4
#define LFA_LINK_SPEED_MISMATCH 0x5
#define LFA_FLOW_CTRL_MISMATCH 0x6
#define LFA_SPEED_CAP_MISMATCH 0x7
#define LFA_DCC_LFA_DISABLED 0x8
#define LFA_EEE_MISMATCH 0x9
#define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
#define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
#define LINK_FLAP_COUNT_OFFSET 16
#define LINK_FLAP_COUNT_MASK 0x00ff0000
#define LFA_FLAGS_MASK 0xff000000
#define SHMEM_LFA_DONT_CLEAR_STAT (1<<24)
};
struct os_drv_ver{
#define DRV_VER_NOT_LOADED 0
#define DRV_PERS_ETHERNET 0
#define DRV_PERS_ISCSI 1
#define DRV_PERS_FCOE 2
#define MAX_DRV_PERS 3
uint32_t versions[MAX_DRV_PERS];
};
#define OEM_I2C_UUID_STR_ADDR 0x9f
#define OEM_I2C_CARD_SKU_STR_ADDR 0x3c
#define OEM_I2C_CARD_FN_STR_ADDR 0x48
#define OEM_I2C_CARD_NAME_STR_ADDR 0x10e
#define OEM_I2C_UUID_STR_LEN 16
#define OEM_I2C_CARD_SKU_STR_LEN 12
#define OEM_I2C_CARD_FN_STR_LEN 12
#define OEM_I2C_CARD_NAME_STR_LEN 128
#define OEM_I2C_CARD_VERSION_STR_LEN 36
struct oem_i2c_data_t {
uint32_t size;
uint8_t uuid[OEM_I2C_UUID_STR_LEN];
uint8_t card_sku[OEM_I2C_CARD_SKU_STR_LEN];
uint8_t card_name[OEM_I2C_CARD_NAME_STR_LEN];
uint8_t card_ver[OEM_I2C_CARD_VERSION_STR_LEN];
uint8_t card_fn[OEM_I2C_CARD_FN_STR_LEN];
};
enum curr_cfg_method_e {
CURR_CFG_MET_NONE = 0,
CURR_CFG_MET_OS = 1,
CURR_CFG_MET_VENDOR_SPEC = 2,
CURR_CFG_MET_HP_OTHER = 3,
CURR_CFG_MET_VC_CLP = 4,
CURR_CFG_MET_HP_CNU = 5,
CURR_CFG_MET_HP_DCI = 6,
};
#define FC_NPIV_WWPN_SIZE 8
#define FC_NPIV_WWNN_SIZE 8
struct bdn_npiv_settings {
uint8_t npiv_wwpn[FC_NPIV_WWPN_SIZE];
uint8_t npiv_wwnn[FC_NPIV_WWNN_SIZE];
};
struct bdn_fc_npiv_cfg {
uint32_t hdr;
uint32_t num_of_npiv;
};
#define MAX_NUMBER_NPIV 64
struct bdn_fc_npiv_tbl {
struct bdn_fc_npiv_cfg fc_npiv_cfg;
struct bdn_npiv_settings settings[MAX_NUMBER_NPIV];
};
struct mdump_driver_info {
uint32_t epoc;
uint32_t drv_ver;
uint32_t fw_ver;
uint32_t valid_dump;
#define FIRST_DUMP_VALID (1 << 0)
#define SECOND_DUMP_VALID (1 << 1)
uint32_t flags;
#define ENABLE_ALL_TRIGGERS (0x7fffffff)
#define TRIGGER_MDUMP_ONCE (1 << 31)
};
struct shmem2_region {
uint32_t size;
uint32_t dcc_support;
#define SHMEM_DCC_SUPPORT_NONE 0x00000000
#define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
#define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
#define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
#define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
#define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
uint32_t ext_phy_fw_version2[PORT_MAX];
uint32_t mf_cfg_addr;
#define SHMEM_MF_CFG_ADDR_NONE 0x00000000
struct fw_flr_mb flr_mb;
uint32_t dcbx_lldp_params_offset;
#define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
uint32_t dcbx_neg_res_offset;
#define SHMEM_DCBX_NEG_RES_NONE 0x00000000
uint32_t dcbx_remote_mib_offset;
#define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
uint32_t other_shmem_base_addr;
uint32_t other_shmem2_base_addr;
uint32_t mcp_vf_disabled[E2_VF_MAX / 32];
uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32];
uint32_t dcbx_lldp_dcbx_stat_offset;
#define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
uint32_t edebug_driver_if[2];
#define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
#define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
#define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
uint32_t nvm_retain_bitmap_addr;
uint32_t afex_driver_support;
#define SHMEM_AFEX_VERSION_MASK 0x100f
#define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001
#define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000
uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX];
uint32_t afex_param1_to_driver[E2_FUNC_MAX];
uint32_t afex_param2_to_driver[E2_FUNC_MAX];
uint32_t swim_base_addr;
uint32_t swim_funcs;
uint32_t swim_main_cb;
uint32_t afex_profiles_enabled[2];
uint32_t drv_flags;
#define DRV_FLAGS_DCB_CONFIGURED 0x0
#define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1
#define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2
#define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \
(1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
(1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
#define DRV_FLAGS_P0_OFFSET 0
#define DRV_FLAGS_P1_OFFSET 16
#define DRV_FLAGS_GET_PORT_OFFSET(_port) ((0 == _port) ? \
DRV_FLAGS_P0_OFFSET : \
DRV_FLAGS_P1_OFFSET)
#define DRV_FLAGS_GET_PORT_MASK(_port) (DRV_FLAGS_PORT_MASK << \
DRV_FLAGS_GET_PORT_OFFSET(_port))
#define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port) (1 << ( \
(_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port)))
uint32_t extended_dev_info_shared_addr;
uint32_t ncsi_oem_data_addr;
uint32_t sensor_data_addr;
uint32_t buffer_block_addr;
uint32_t sensor_data_req_update_interval;
uint32_t temperature_in_half_celsius;
uint32_t glob_struct_in_host;
uint32_t dcbx_neg_res_ext_offset;
#define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
uint32_t drv_capabilities_flag[E2_FUNC_MAX];
#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
#define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
#define DRV_FLAGS_MTU_MASK 0xffff0000
#define DRV_FLAGS_MTU_SHIFT 16
uint32_t extended_dev_info_shared_cfg_size;
uint32_t dcbx_en[PORT_MAX];
uint32_t multi_thread_data_offset;
uint32_t drv_info_host_addr_lo;
uint32_t drv_info_host_addr_hi;
uint32_t drv_info_control;
#define DRV_INFO_CONTROL_VER_MASK 0x000000ff
#define DRV_INFO_CONTROL_VER_SHIFT 0
#define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
#define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
uint32_t ibft_host_addr;
struct eee_remote_vals eee_remote_vals[PORT_MAX];
uint32_t pf_allocation[E2_FUNC_MAX];
#define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff
#define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0
uint32_t eee_status[PORT_MAX];
#define SHMEM_EEE_TIMER_MASK 0x0000ffff
#define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
#define SHMEM_EEE_SUPPORTED_SHIFT 16
#define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
#define SHMEM_EEE_100M_ADV (1<<0)
#define SHMEM_EEE_1G_ADV (1<<1)
#define SHMEM_EEE_10G_ADV (1<<2)
#define SHMEM_EEE_ADV_STATUS_SHIFT 20
#define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
#define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24
#define SHMEM_EEE_REQUESTED_BIT 0x10000000
#define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000
#define SHMEM_EEE_ACTIVE_BIT 0x40000000
#define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
uint32_t sizeof_port_stats;
uint32_t lfa_host_addr[PORT_MAX];
uint32_t extphy_temps_in_celsius;
#define EXTPHY1_TEMP_MASK 0x0000ffff
#define EXTPHY1_TEMP_SHIFT 0
#define ON_BOARD_TEMP_MASK 0xffff0000
#define ON_BOARD_TEMP_SHIFT 16
uint32_t ocdata_info_addr;
uint32_t drv_func_info_addr;
uint32_t drv_func_info_size;
uint32_t link_attr_sync[PORT_MAX];
#define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
#define LINK_ATTR_84858 0x00000002
#define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
#define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
#define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000
#define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000
#define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000
uint32_t ibft_host_addr_hi;
uint32_t fcode_ver;
uint32_t link_change_count[PORT_MAX];
#define LINK_CHANGE_COUNT_MASK 0xff
struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX];
uint32_t mfw_drv_indication;
#define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << _pf_)
union {
uint8_t storage_boot_prog[E2_FUNC_MAX];
#define STORAGE_BOOT_PROG_MASK 0x000000FF
#define STORAGE_BOOT_PROG_NONE 0x00000000
#define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002
#define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002
#define STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004
#define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008
#define STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008
#define STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010
#define STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020
#define STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040
#define STORAGE_BOOT_PROG_COMPLETED 0x00000080
uint32_t oem_i2c_data_addr;
}u;
uint32_t c2s_pcp_map_lower[E2_FUNC_MAX];
uint32_t c2s_pcp_map_upper[E2_FUNC_MAX];
uint32_t c2s_pcp_map_default[E2_FUNC_MAX];
uint32_t fc_npiv_nvram_tbl_addr[PORT_MAX];
enum curr_cfg_method_e curr_cfg;
uint32_t netproc_fw_ver;
uint32_t clp_ver;
uint32_t pcie_bus_num;
uint32_t sriov_switch_mode;
#define SRIOV_SWITCH_MODE_NONE 0x0
#define SRIOV_SWITCH_MODE_VEB 0x1
#define SRIOV_SWITCH_MODE_VEPA 0x2
uint8_t rsrv2[E2_FUNC_MAX];
uint32_t img_inv_table_addr;
uint32_t mtu_size[E2_FUNC_MAX];
uint32_t os_driver_state[E2_FUNC_MAX];
#define OS_DRIVER_STATE_NOT_LOADED 0
#define OS_DRIVER_STATE_LOADING 1
#define OS_DRIVER_STATE_DISABLED 2
#define OS_DRIVER_STATE_ACTIVE 3
struct mdump_driver_info drv_info;
};
struct emac_stats {
uint32_t rx_stat_ifhcinoctets;
uint32_t rx_stat_ifhcinbadoctets;
uint32_t rx_stat_etherstatsfragments;
uint32_t rx_stat_ifhcinucastpkts;
uint32_t rx_stat_ifhcinmulticastpkts;
uint32_t rx_stat_ifhcinbroadcastpkts;
uint32_t rx_stat_dot3statsfcserrors;
uint32_t rx_stat_dot3statsalignmenterrors;
uint32_t rx_stat_dot3statscarriersenseerrors;
uint32_t rx_stat_xonpauseframesreceived;
uint32_t rx_stat_xoffpauseframesreceived;
uint32_t rx_stat_maccontrolframesreceived;
uint32_t rx_stat_xoffstateentered;
uint32_t rx_stat_dot3statsframestoolong;
uint32_t rx_stat_etherstatsjabbers;
uint32_t rx_stat_etherstatsundersizepkts;
uint32_t rx_stat_etherstatspkts64octets;
uint32_t rx_stat_etherstatspkts65octetsto127octets;
uint32_t rx_stat_etherstatspkts128octetsto255octets;
uint32_t rx_stat_etherstatspkts256octetsto511octets;
uint32_t rx_stat_etherstatspkts512octetsto1023octets;
uint32_t rx_stat_etherstatspkts1024octetsto1522octets;
uint32_t rx_stat_etherstatspktsover1522octets;
uint32_t rx_stat_falsecarriererrors;
uint32_t tx_stat_ifhcoutoctets;
uint32_t tx_stat_ifhcoutbadoctets;
uint32_t tx_stat_etherstatscollisions;
uint32_t tx_stat_outxonsent;
uint32_t tx_stat_outxoffsent;
uint32_t tx_stat_flowcontroldone;
uint32_t tx_stat_dot3statssinglecollisionframes;
uint32_t tx_stat_dot3statsmultiplecollisionframes;
uint32_t tx_stat_dot3statsdeferredtransmissions;
uint32_t tx_stat_dot3statsexcessivecollisions;
uint32_t tx_stat_dot3statslatecollisions;
uint32_t tx_stat_ifhcoutucastpkts;
uint32_t tx_stat_ifhcoutmulticastpkts;
uint32_t tx_stat_ifhcoutbroadcastpkts;
uint32_t tx_stat_etherstatspkts64octets;
uint32_t tx_stat_etherstatspkts65octetsto127octets;
uint32_t tx_stat_etherstatspkts128octetsto255octets;
uint32_t tx_stat_etherstatspkts256octetsto511octets;
uint32_t tx_stat_etherstatspkts512octetsto1023octets;
uint32_t tx_stat_etherstatspkts1024octetsto1522octets;
uint32_t tx_stat_etherstatspktsover1522octets;
uint32_t tx_stat_dot3statsinternalmactransmiterrors;
};
struct bmac1_stats {
uint32_t tx_stat_gtpkt_lo;
uint32_t tx_stat_gtpkt_hi;
uint32_t tx_stat_gtxpf_lo;
uint32_t tx_stat_gtxpf_hi;
uint32_t tx_stat_gtfcs_lo;
uint32_t tx_stat_gtfcs_hi;
uint32_t tx_stat_gtmca_lo;
uint32_t tx_stat_gtmca_hi;
uint32_t tx_stat_gtbca_lo;
uint32_t tx_stat_gtbca_hi;
uint32_t tx_stat_gtfrg_lo;
uint32_t tx_stat_gtfrg_hi;
uint32_t tx_stat_gtovr_lo;
uint32_t tx_stat_gtovr_hi;
uint32_t tx_stat_gt64_lo;
uint32_t tx_stat_gt64_hi;
uint32_t tx_stat_gt127_lo;
uint32_t tx_stat_gt127_hi;
uint32_t tx_stat_gt255_lo;
uint32_t tx_stat_gt255_hi;
uint32_t tx_stat_gt511_lo;
uint32_t tx_stat_gt511_hi;
uint32_t tx_stat_gt1023_lo;
uint32_t tx_stat_gt1023_hi;
uint32_t tx_stat_gt1518_lo;
uint32_t tx_stat_gt1518_hi;
uint32_t tx_stat_gt2047_lo;
uint32_t tx_stat_gt2047_hi;
uint32_t tx_stat_gt4095_lo;
uint32_t tx_stat_gt4095_hi;
uint32_t tx_stat_gt9216_lo;
uint32_t tx_stat_gt9216_hi;
uint32_t tx_stat_gt16383_lo;
uint32_t tx_stat_gt16383_hi;
uint32_t tx_stat_gtmax_lo;
uint32_t tx_stat_gtmax_hi;
uint32_t tx_stat_gtufl_lo;
uint32_t tx_stat_gtufl_hi;
uint32_t tx_stat_gterr_lo;
uint32_t tx_stat_gterr_hi;
uint32_t tx_stat_gtbyt_lo;
uint32_t tx_stat_gtbyt_hi;
uint32_t rx_stat_gr64_lo;
uint32_t rx_stat_gr64_hi;
uint32_t rx_stat_gr127_lo;
uint32_t rx_stat_gr127_hi;
uint32_t rx_stat_gr255_lo;
uint32_t rx_stat_gr255_hi;
uint32_t rx_stat_gr511_lo;
uint32_t rx_stat_gr511_hi;
uint32_t rx_stat_gr1023_lo;
uint32_t rx_stat_gr1023_hi;
uint32_t rx_stat_gr1518_lo;
uint32_t rx_stat_gr1518_hi;
uint32_t rx_stat_gr2047_lo;
uint32_t rx_stat_gr2047_hi;
uint32_t rx_stat_gr4095_lo;
uint32_t rx_stat_gr4095_hi;
uint32_t rx_stat_gr9216_lo;
uint32_t rx_stat_gr9216_hi;
uint32_t rx_stat_gr16383_lo;
uint32_t rx_stat_gr16383_hi;
uint32_t rx_stat_grmax_lo;
uint32_t rx_stat_grmax_hi;
uint32_t rx_stat_grpkt_lo;
uint32_t rx_stat_grpkt_hi;
uint32_t rx_stat_grfcs_lo;
uint32_t rx_stat_grfcs_hi;
uint32_t rx_stat_grmca_lo;
uint32_t rx_stat_grmca_hi;
uint32_t rx_stat_grbca_lo;
uint32_t rx_stat_grbca_hi;
uint32_t rx_stat_grxcf_lo;
uint32_t rx_stat_grxcf_hi;
uint32_t rx_stat_grxpf_lo;
uint32_t rx_stat_grxpf_hi;
uint32_t rx_stat_grxuo_lo;
uint32_t rx_stat_grxuo_hi;
uint32_t rx_stat_grjbr_lo;
uint32_t rx_stat_grjbr_hi;
uint32_t rx_stat_grovr_lo;
uint32_t rx_stat_grovr_hi;
uint32_t rx_stat_grflr_lo;
uint32_t rx_stat_grflr_hi;
uint32_t rx_stat_grmeg_lo;
uint32_t rx_stat_grmeg_hi;
uint32_t rx_stat_grmeb_lo;
uint32_t rx_stat_grmeb_hi;
uint32_t rx_stat_grbyt_lo;
uint32_t rx_stat_grbyt_hi;
uint32_t rx_stat_grund_lo;
uint32_t rx_stat_grund_hi;
uint32_t rx_stat_grfrg_lo;
uint32_t rx_stat_grfrg_hi;
uint32_t rx_stat_grerb_lo;
uint32_t rx_stat_grerb_hi;
uint32_t rx_stat_grfre_lo;
uint32_t rx_stat_grfre_hi;
uint32_t rx_stat_gripj_lo;
uint32_t rx_stat_gripj_hi;
};
struct bmac2_stats {
uint32_t tx_stat_gtpk_lo;
uint32_t tx_stat_gtpk_hi;
uint32_t tx_stat_gtxpf_lo;
uint32_t tx_stat_gtxpf_hi;
uint32_t tx_stat_gtpp_lo;
uint32_t tx_stat_gtpp_hi;
uint32_t tx_stat_gtfcs_lo;
uint32_t tx_stat_gtfcs_hi;
uint32_t tx_stat_gtuca_lo;
uint32_t tx_stat_gtuca_hi;
uint32_t tx_stat_gtmca_lo;
uint32_t tx_stat_gtmca_hi;
uint32_t tx_stat_gtbca_lo;
uint32_t tx_stat_gtbca_hi;
uint32_t tx_stat_gtovr_lo;
uint32_t tx_stat_gtovr_hi;
uint32_t tx_stat_gtfrg_lo;
uint32_t tx_stat_gtfrg_hi;
uint32_t tx_stat_gtpkt1_lo;
uint32_t tx_stat_gtpkt1_hi;
uint32_t tx_stat_gt64_lo;
uint32_t tx_stat_gt64_hi;
uint32_t tx_stat_gt127_lo;
uint32_t tx_stat_gt127_hi;
uint32_t tx_stat_gt255_lo;
uint32_t tx_stat_gt255_hi;
uint32_t tx_stat_gt511_lo;
uint32_t tx_stat_gt511_hi;
uint32_t tx_stat_gt1023_lo;
uint32_t tx_stat_gt1023_hi;
uint32_t tx_stat_gt1518_lo;
uint32_t tx_stat_gt1518_hi;
uint32_t tx_stat_gt2047_lo;
uint32_t tx_stat_gt2047_hi;
uint32_t tx_stat_gt4095_lo;
uint32_t tx_stat_gt4095_hi;
uint32_t tx_stat_gt9216_lo;
uint32_t tx_stat_gt9216_hi;
uint32_t tx_stat_gt16383_lo;
uint32_t tx_stat_gt16383_hi;
uint32_t tx_stat_gtmax_lo;
uint32_t tx_stat_gtmax_hi;
uint32_t tx_stat_gtufl_lo;
uint32_t tx_stat_gtufl_hi;
uint32_t tx_stat_gterr_lo;
uint32_t tx_stat_gterr_hi;
uint32_t tx_stat_gtbyt_lo;
uint32_t tx_stat_gtbyt_hi;
uint32_t rx_stat_gr64_lo;
uint32_t rx_stat_gr64_hi;
uint32_t rx_stat_gr127_lo;
uint32_t rx_stat_gr127_hi;
uint32_t rx_stat_gr255_lo;
uint32_t rx_stat_gr255_hi;
uint32_t rx_stat_gr511_lo;
uint32_t rx_stat_gr511_hi;
uint32_t rx_stat_gr1023_lo;
uint32_t rx_stat_gr1023_hi;
uint32_t rx_stat_gr1518_lo;
uint32_t rx_stat_gr1518_hi;
uint32_t rx_stat_gr2047_lo;
uint32_t rx_stat_gr2047_hi;
uint32_t rx_stat_gr4095_lo;
uint32_t rx_stat_gr4095_hi;
uint32_t rx_stat_gr9216_lo;
uint32_t rx_stat_gr9216_hi;
uint32_t rx_stat_gr16383_lo;
uint32_t rx_stat_gr16383_hi;
uint32_t rx_stat_grmax_lo;
uint32_t rx_stat_grmax_hi;
uint32_t rx_stat_grpkt_lo;
uint32_t rx_stat_grpkt_hi;
uint32_t rx_stat_grfcs_lo;
uint32_t rx_stat_grfcs_hi;
uint32_t rx_stat_gruca_lo;
uint32_t rx_stat_gruca_hi;
uint32_t rx_stat_grmca_lo;
uint32_t rx_stat_grmca_hi;
uint32_t rx_stat_grbca_lo;
uint32_t rx_stat_grbca_hi;
uint32_t rx_stat_grxpf_lo;
uint32_t rx_stat_grxpf_hi;
uint32_t rx_stat_grpp_lo;
uint32_t rx_stat_grpp_hi;
uint32_t rx_stat_grxuo_lo;
uint32_t rx_stat_grxuo_hi;
uint32_t rx_stat_grjbr_lo;
uint32_t rx_stat_grjbr_hi;
uint32_t rx_stat_grovr_lo;
uint32_t rx_stat_grovr_hi;
uint32_t rx_stat_grxcf_lo;
uint32_t rx_stat_grxcf_hi;
uint32_t rx_stat_grflr_lo;
uint32_t rx_stat_grflr_hi;
uint32_t rx_stat_grpok_lo;
uint32_t rx_stat_grpok_hi;
uint32_t rx_stat_grmeg_lo;
uint32_t rx_stat_grmeg_hi;
uint32_t rx_stat_grmeb_lo;
uint32_t rx_stat_grmeb_hi;
uint32_t rx_stat_grbyt_lo;
uint32_t rx_stat_grbyt_hi;
uint32_t rx_stat_grund_lo;
uint32_t rx_stat_grund_hi;
uint32_t rx_stat_grfrg_lo;
uint32_t rx_stat_grfrg_hi;
uint32_t rx_stat_grerb_lo;
uint32_t rx_stat_grerb_hi;
uint32_t rx_stat_grfre_lo;
uint32_t rx_stat_grfre_hi;
uint32_t rx_stat_gripj_lo;
uint32_t rx_stat_gripj_hi;
};
struct mstat_stats {
struct {
uint32_t tx_gtxpok_lo;
uint32_t tx_gtxpok_hi;
uint32_t tx_gtxpf_lo;
uint32_t tx_gtxpf_hi;
uint32_t tx_gtxpp_lo;
uint32_t tx_gtxpp_hi;
uint32_t tx_gtfcs_lo;
uint32_t tx_gtfcs_hi;
uint32_t tx_gtuca_lo;
uint32_t tx_gtuca_hi;
uint32_t tx_gtmca_lo;
uint32_t tx_gtmca_hi;
uint32_t tx_gtgca_lo;
uint32_t tx_gtgca_hi;
uint32_t tx_gtpkt_lo;
uint32_t tx_gtpkt_hi;
uint32_t tx_gt64_lo;
uint32_t tx_gt64_hi;
uint32_t tx_gt127_lo;
uint32_t tx_gt127_hi;
uint32_t tx_gt255_lo;
uint32_t tx_gt255_hi;
uint32_t tx_gt511_lo;
uint32_t tx_gt511_hi;
uint32_t tx_gt1023_lo;
uint32_t tx_gt1023_hi;
uint32_t tx_gt1518_lo;
uint32_t tx_gt1518_hi;
uint32_t tx_gt2047_lo;
uint32_t tx_gt2047_hi;
uint32_t tx_gt4095_lo;
uint32_t tx_gt4095_hi;
uint32_t tx_gt9216_lo;
uint32_t tx_gt9216_hi;
uint32_t tx_gt16383_lo;
uint32_t tx_gt16383_hi;
uint32_t tx_gtufl_lo;
uint32_t tx_gtufl_hi;
uint32_t tx_gterr_lo;
uint32_t tx_gterr_hi;
uint32_t tx_gtbyt_lo;
uint32_t tx_gtbyt_hi;
uint32_t tx_collisions_lo;
uint32_t tx_collisions_hi;
uint32_t tx_singlecollision_lo;
uint32_t tx_singlecollision_hi;
uint32_t tx_multiplecollisions_lo;
uint32_t tx_multiplecollisions_hi;
uint32_t tx_deferred_lo;
uint32_t tx_deferred_hi;
uint32_t tx_excessivecollisions_lo;
uint32_t tx_excessivecollisions_hi;
uint32_t tx_latecollisions_lo;
uint32_t tx_latecollisions_hi;
} stats_tx;
struct {
uint32_t rx_gr64_lo;
uint32_t rx_gr64_hi;
uint32_t rx_gr127_lo;
uint32_t rx_gr127_hi;
uint32_t rx_gr255_lo;
uint32_t rx_gr255_hi;
uint32_t rx_gr511_lo;
uint32_t rx_gr511_hi;
uint32_t rx_gr1023_lo;
uint32_t rx_gr1023_hi;
uint32_t rx_gr1518_lo;
uint32_t rx_gr1518_hi;
uint32_t rx_gr2047_lo;
uint32_t rx_gr2047_hi;
uint32_t rx_gr4095_lo;
uint32_t rx_gr4095_hi;
uint32_t rx_gr9216_lo;
uint32_t rx_gr9216_hi;
uint32_t rx_gr16383_lo;
uint32_t rx_gr16383_hi;
uint32_t rx_grpkt_lo;
uint32_t rx_grpkt_hi;
uint32_t rx_grfcs_lo;
uint32_t rx_grfcs_hi;
uint32_t rx_gruca_lo;
uint32_t rx_gruca_hi;
uint32_t rx_grmca_lo;
uint32_t rx_grmca_hi;
uint32_t rx_grbca_lo;
uint32_t rx_grbca_hi;
uint32_t rx_grxpf_lo;
uint32_t rx_grxpf_hi;
uint32_t rx_grxpp_lo;
uint32_t rx_grxpp_hi;
uint32_t rx_grxuo_lo;
uint32_t rx_grxuo_hi;
uint32_t rx_grovr_lo;
uint32_t rx_grovr_hi;
uint32_t rx_grxcf_lo;
uint32_t rx_grxcf_hi;
uint32_t rx_grflr_lo;
uint32_t rx_grflr_hi;
uint32_t rx_grpok_lo;
uint32_t rx_grpok_hi;
uint32_t rx_grbyt_lo;
uint32_t rx_grbyt_hi;
uint32_t rx_grund_lo;
uint32_t rx_grund_hi;
uint32_t rx_grfrg_lo;
uint32_t rx_grfrg_hi;
uint32_t rx_grerb_lo;
uint32_t rx_grerb_hi;
uint32_t rx_grfre_lo;
uint32_t rx_grfre_hi;
uint32_t rx_alignmenterrors_lo;
uint32_t rx_alignmenterrors_hi;
uint32_t rx_falsecarrier_lo;
uint32_t rx_falsecarrier_hi;
uint32_t rx_llfcmsgcnt_lo;
uint32_t rx_llfcmsgcnt_hi;
} stats_rx;
};
union mac_stats {
struct emac_stats emac_stats;
struct bmac1_stats bmac1_stats;
struct bmac2_stats bmac2_stats;
struct mstat_stats mstat_stats;
};
struct mac_stx {
uint32_t rx_stat_ifhcinbadoctets_hi;
uint32_t rx_stat_ifhcinbadoctets_lo;
uint32_t tx_stat_ifhcoutbadoctets_hi;
uint32_t tx_stat_ifhcoutbadoctets_lo;
uint32_t rx_stat_dot3statsfcserrors_hi;
uint32_t rx_stat_dot3statsfcserrors_lo;
uint32_t rx_stat_dot3statsalignmenterrors_hi;
uint32_t rx_stat_dot3statsalignmenterrors_lo;
uint32_t rx_stat_dot3statscarriersenseerrors_hi;
uint32_t rx_stat_dot3statscarriersenseerrors_lo;
uint32_t rx_stat_falsecarriererrors_hi;
uint32_t rx_stat_falsecarriererrors_lo;
uint32_t rx_stat_etherstatsundersizepkts_hi;
uint32_t rx_stat_etherstatsundersizepkts_lo;
uint32_t rx_stat_dot3statsframestoolong_hi;
uint32_t rx_stat_dot3statsframestoolong_lo;
uint32_t rx_stat_etherstatsfragments_hi;
uint32_t rx_stat_etherstatsfragments_lo;
uint32_t rx_stat_etherstatsjabbers_hi;
uint32_t rx_stat_etherstatsjabbers_lo;
uint32_t rx_stat_maccontrolframesreceived_hi;
uint32_t rx_stat_maccontrolframesreceived_lo;
uint32_t rx_stat_mac_xpf_hi;
uint32_t rx_stat_mac_xpf_lo;
uint32_t rx_stat_mac_xcf_hi;
uint32_t rx_stat_mac_xcf_lo;
uint32_t rx_stat_xoffstateentered_hi;
uint32_t rx_stat_xoffstateentered_lo;
uint32_t rx_stat_xonpauseframesreceived_hi;
uint32_t rx_stat_xonpauseframesreceived_lo;
uint32_t rx_stat_xoffpauseframesreceived_hi;
uint32_t rx_stat_xoffpauseframesreceived_lo;
uint32_t tx_stat_outxonsent_hi;
uint32_t tx_stat_outxonsent_lo;
uint32_t tx_stat_outxoffsent_hi;
uint32_t tx_stat_outxoffsent_lo;
uint32_t tx_stat_flowcontroldone_hi;
uint32_t tx_stat_flowcontroldone_lo;
uint32_t tx_stat_etherstatscollisions_hi;
uint32_t tx_stat_etherstatscollisions_lo;
uint32_t tx_stat_dot3statssinglecollisionframes_hi;
uint32_t tx_stat_dot3statssinglecollisionframes_lo;
uint32_t tx_stat_dot3statsmultiplecollisionframes_hi;
uint32_t tx_stat_dot3statsmultiplecollisionframes_lo;
uint32_t tx_stat_dot3statsdeferredtransmissions_hi;
uint32_t tx_stat_dot3statsdeferredtransmissions_lo;
uint32_t tx_stat_dot3statsexcessivecollisions_hi;
uint32_t tx_stat_dot3statsexcessivecollisions_lo;
uint32_t tx_stat_dot3statslatecollisions_hi;
uint32_t tx_stat_dot3statslatecollisions_lo;
uint32_t tx_stat_etherstatspkts64octets_hi;
uint32_t tx_stat_etherstatspkts64octets_lo;
uint32_t tx_stat_etherstatspkts65octetsto127octets_hi;
uint32_t tx_stat_etherstatspkts65octetsto127octets_lo;
uint32_t tx_stat_etherstatspkts128octetsto255octets_hi;
uint32_t tx_stat_etherstatspkts128octetsto255octets_lo;
uint32_t tx_stat_etherstatspkts256octetsto511octets_hi;
uint32_t tx_stat_etherstatspkts256octetsto511octets_lo;
uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi;
uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo;
uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi;
uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo;
uint32_t tx_stat_etherstatspktsover1522octets_hi;
uint32_t tx_stat_etherstatspktsover1522octets_lo;
uint32_t tx_stat_mac_2047_hi;
uint32_t tx_stat_mac_2047_lo;
uint32_t tx_stat_mac_4095_hi;
uint32_t tx_stat_mac_4095_lo;
uint32_t tx_stat_mac_9216_hi;
uint32_t tx_stat_mac_9216_lo;
uint32_t tx_stat_mac_16383_hi;
uint32_t tx_stat_mac_16383_lo;
uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi;
uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo;
uint32_t tx_stat_mac_ufl_hi;
uint32_t tx_stat_mac_ufl_lo;
};
#define MAC_STX_IDX_MAX 2
struct host_port_stats {
uint32_t host_port_stats_counter;
struct mac_stx mac_stx[MAC_STX_IDX_MAX];
uint32_t brb_drop_hi;
uint32_t brb_drop_lo;
uint32_t not_used;
uint32_t pfc_frames_tx_hi;
uint32_t pfc_frames_tx_lo;
uint32_t pfc_frames_rx_hi;
uint32_t pfc_frames_rx_lo;
uint32_t eee_lpi_count_hi;
uint32_t eee_lpi_count_lo;
};
struct host_func_stats {
uint32_t host_func_stats_start;
uint32_t total_bytes_received_hi;
uint32_t total_bytes_received_lo;
uint32_t total_bytes_transmitted_hi;
uint32_t total_bytes_transmitted_lo;
uint32_t total_unicast_packets_received_hi;
uint32_t total_unicast_packets_received_lo;
uint32_t total_multicast_packets_received_hi;
uint32_t total_multicast_packets_received_lo;
uint32_t total_broadcast_packets_received_hi;
uint32_t total_broadcast_packets_received_lo;
uint32_t total_unicast_packets_transmitted_hi;
uint32_t total_unicast_packets_transmitted_lo;
uint32_t total_multicast_packets_transmitted_hi;
uint32_t total_multicast_packets_transmitted_lo;
uint32_t total_broadcast_packets_transmitted_hi;
uint32_t total_broadcast_packets_transmitted_lo;
uint32_t valid_bytes_received_hi;
uint32_t valid_bytes_received_lo;
uint32_t host_func_stats_end;
};
#define VICSTATST_UIF_INDEX 2
struct afex_stats {
uint32_t tx_unicast_frames_hi;
uint32_t tx_unicast_frames_lo;
uint32_t tx_unicast_bytes_hi;
uint32_t tx_unicast_bytes_lo;
uint32_t tx_multicast_frames_hi;
uint32_t tx_multicast_frames_lo;
uint32_t tx_multicast_bytes_hi;
uint32_t tx_multicast_bytes_lo;
uint32_t tx_broadcast_frames_hi;
uint32_t tx_broadcast_frames_lo;
uint32_t tx_broadcast_bytes_hi;
uint32_t tx_broadcast_bytes_lo;
uint32_t tx_frames_discarded_hi;
uint32_t tx_frames_discarded_lo;
uint32_t tx_frames_dropped_hi;
uint32_t tx_frames_dropped_lo;
uint32_t rx_unicast_frames_hi;
uint32_t rx_unicast_frames_lo;
uint32_t rx_unicast_bytes_hi;
uint32_t rx_unicast_bytes_lo;
uint32_t rx_multicast_frames_hi;
uint32_t rx_multicast_frames_lo;
uint32_t rx_multicast_bytes_hi;
uint32_t rx_multicast_bytes_lo;
uint32_t rx_broadcast_frames_hi;
uint32_t rx_broadcast_frames_lo;
uint32_t rx_broadcast_bytes_hi;
uint32_t rx_broadcast_bytes_lo;
uint32_t rx_frames_discarded_hi;
uint32_t rx_frames_discarded_lo;
uint32_t rx_frames_dropped_hi;
uint32_t rx_frames_dropped_lo;
};
struct port_info {
uint32_t size;
uint32_t enabled;
uint32_t link_speed;
uint32_t wol_support;
uint32_t flow_control;
uint32_t flex10;
uint32_t rx_drops;
uint32_t rx_errors;
uint32_t rx_uncast_lo;
uint32_t rx_uncast_hi;
uint32_t rx_mcast_lo;
uint32_t rx_mcast_hi;
uint32_t rx_bcast_lo;
uint32_t rx_bcast_hi;
uint32_t tx_uncast_lo;
uint32_t tx_uncast_hi;
uint32_t tx_mcast_lo;
uint32_t tx_mcast_hi;
uint32_t tx_bcast_lo;
uint32_t tx_bcast_hi;
uint32_t tx_errors;
uint32_t tx_discards;
uint32_t rx_frames_lo;
uint32_t rx_frames_hi;
uint32_t rx_bytes_lo;
uint32_t rx_bytes_hi;
uint32_t tx_frames_lo;
uint32_t tx_frames_hi;
uint32_t tx_bytes_lo;
uint32_t tx_bytes_hi;
uint32_t link_status;
uint32_t tx_pfc_frames_lo;
uint32_t tx_pfc_frames_hi;
uint32_t rx_pfc_frames_lo;
uint32_t rx_pfc_frames_hi;
};
#define BCM_5710_FW_MAJOR_VERSION 7
#define BCM_5710_FW_MINOR_VERSION 13
#define BCM_5710_FW_REVISION_VERSION 1
#define BCM_5710_FW_ENGINEERING_VERSION 0
#define BCM_5710_FW_COMPILE_FLAGS 1
struct atten_sp_status_block
{
uint32_t attn_bits ;
uint32_t attn_bits_ack ;
uint8_t status_block_id ;
uint8_t reserved0 ;
uint16_t attn_bits_index ;
uint32_t reserved1 ;
};
struct cstorm_eth_ag_context
{
uint32_t __reserved0[10];
};
struct cstorm_iscsi_ag_context
{
uint32_t agg_vars1;
#define CSTORM_ISCSI_AG_CONTEXT_STATE (0xFF<<0)
#define CSTORM_ISCSI_AG_CONTEXT_STATE_SHIFT 0
#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<8)
#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 8
#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<9)
#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 9
#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<10)
#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 10
#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<11)
#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 11
#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN (0x1<<12)
#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN_SHIFT 12
#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN (0x1<<13)
#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN_SHIFT 13
#define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<14)
#define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_SHIFT 14
#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16)
#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66_SHIFT 16
#define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN (0x1<<18)
#define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN_SHIFT 18
#define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<19)
#define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 19
#define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN (0x1<<20)
#define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN_SHIFT 20
#define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<21)
#define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 21
#define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN (0x1<<22)
#define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN_SHIFT 22
#define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE (0x7<<23)
#define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE_SHIFT 23
#define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE (0x3<<26)
#define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE_SHIFT 26
#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52 (0x3<<28)
#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52_SHIFT 28
#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53 (0x3<<30)
#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53_SHIFT 30
#if defined(__BIG_ENDIAN)
uint8_t __aux1_th ;
uint8_t __aux1_val ;
uint16_t __agg_vars2 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_vars2 ;
uint8_t __aux1_val ;
uint8_t __aux1_th ;
#endif
uint32_t rel_seq ;
uint32_t rel_seq_th ;
#if defined(__BIG_ENDIAN)
uint16_t hq_cons ;
uint16_t hq_prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t hq_prod ;
uint16_t hq_cons ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t __reserved62 ;
uint8_t __reserved61 ;
uint8_t __reserved60 ;
uint8_t __reserved59 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __reserved59 ;
uint8_t __reserved60 ;
uint8_t __reserved61 ;
uint8_t __reserved62 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __reserved64 ;
uint16_t cq_u_prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t cq_u_prod ;
uint16_t __reserved64 ;
#endif
uint32_t __cq_u_prod1 ;
#if defined(__BIG_ENDIAN)
uint16_t __agg_vars3 ;
uint16_t cq_u_pend ;
#elif defined(__LITTLE_ENDIAN)
uint16_t cq_u_pend ;
uint16_t __agg_vars3 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __aux2_th ;
uint16_t aux2_val ;
#elif defined(__LITTLE_ENDIAN)
uint16_t aux2_val ;
uint16_t __aux2_th ;
#endif
};
struct cstorm_toe_ag_context
{
uint32_t __agg_vars1 ;
#if defined(__BIG_ENDIAN)
uint8_t __aux1_th ;
uint8_t __aux1_val ;
uint16_t __agg_vars2 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_vars2 ;
uint8_t __aux1_val ;
uint8_t __aux1_th ;
#endif
uint32_t rel_seq ;
uint32_t __rel_seq_threshold ;
#if defined(__BIG_ENDIAN)
uint16_t __reserved58 ;
uint16_t bd_prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t bd_prod ;
uint16_t __reserved58 ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t __reserved62 ;
uint8_t __reserved61 ;
uint8_t __reserved60 ;
uint8_t __completion_opcode ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __completion_opcode ;
uint8_t __reserved60 ;
uint8_t __reserved61 ;
uint8_t __reserved62 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __reserved64 ;
uint16_t __reserved63 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __reserved63 ;
uint16_t __reserved64 ;
#endif
uint32_t snd_max ;
#if defined(__BIG_ENDIAN)
uint16_t __agg_vars3 ;
uint16_t __reserved67 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __reserved67 ;
uint16_t __agg_vars3 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __aux2_th ;
uint16_t __aux2_val ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __aux2_val ;
uint16_t __aux2_th ;
#endif
};
struct dmae_cmd
{
uint32_t opcode;
#define DMAE_CMD_SRC (0x1<<0)
#define DMAE_CMD_SRC_SHIFT 0
#define DMAE_CMD_DST (0x3<<1)
#define DMAE_CMD_DST_SHIFT 1
#define DMAE_CMD_C_DST (0x1<<3)
#define DMAE_CMD_C_DST_SHIFT 3
#define DMAE_CMD_C_TYPE_ENABLE (0x1<<4)
#define DMAE_CMD_C_TYPE_ENABLE_SHIFT 4
#define DMAE_CMD_C_TYPE_CRC_ENABLE (0x1<<5)
#define DMAE_CMD_C_TYPE_CRC_ENABLE_SHIFT 5
#define DMAE_CMD_C_TYPE_CRC_OFFSET (0x7<<6)
#define DMAE_CMD_C_TYPE_CRC_OFFSET_SHIFT 6
#define DMAE_CMD_ENDIANITY (0x3<<9)
#define DMAE_CMD_ENDIANITY_SHIFT 9
#define DMAE_CMD_PORT (0x1<<11)
#define DMAE_CMD_PORT_SHIFT 11
#define DMAE_CMD_CRC_RESET (0x1<<12)
#define DMAE_CMD_CRC_RESET_SHIFT 12
#define DMAE_CMD_SRC_RESET (0x1<<13)
#define DMAE_CMD_SRC_RESET_SHIFT 13
#define DMAE_CMD_DST_RESET (0x1<<14)
#define DMAE_CMD_DST_RESET_SHIFT 14
#define DMAE_CMD_E1HVN (0x3<<15)
#define DMAE_CMD_E1HVN_SHIFT 15
#define DMAE_CMD_DST_VN (0x3<<17)
#define DMAE_CMD_DST_VN_SHIFT 17
#define DMAE_CMD_C_FUNC (0x1<<19)
#define DMAE_CMD_C_FUNC_SHIFT 19
#define DMAE_CMD_ERR_POLICY (0x3<<20)
#define DMAE_CMD_ERR_POLICY_SHIFT 20
#define DMAE_CMD_RESERVED0 (0x3FF<<22)
#define DMAE_CMD_RESERVED0_SHIFT 22
uint32_t src_addr_lo ;
uint32_t src_addr_hi ;
uint32_t dst_addr_lo ;
uint32_t dst_addr_hi ;
#if defined(__BIG_ENDIAN)
uint16_t opcode_iov;
#define DMAE_CMD_SRC_VFID (0x3F<<0)
#define DMAE_CMD_SRC_VFID_SHIFT 0
#define DMAE_CMD_SRC_VFPF (0x1<<6)
#define DMAE_CMD_SRC_VFPF_SHIFT 6
#define DMAE_CMD_RESERVED1 (0x1<<7)
#define DMAE_CMD_RESERVED1_SHIFT 7
#define DMAE_CMD_DST_VFID (0x3F<<8)
#define DMAE_CMD_DST_VFID_SHIFT 8
#define DMAE_CMD_DST_VFPF (0x1<<14)
#define DMAE_CMD_DST_VFPF_SHIFT 14
#define DMAE_CMD_RESERVED2 (0x1<<15)
#define DMAE_CMD_RESERVED2_SHIFT 15
uint16_t len ;
#elif defined(__LITTLE_ENDIAN)
uint16_t len ;
uint16_t opcode_iov;
#define DMAE_CMD_SRC_VFID (0x3F<<0)
#define DMAE_CMD_SRC_VFID_SHIFT 0
#define DMAE_CMD_SRC_VFPF (0x1<<6)
#define DMAE_CMD_SRC_VFPF_SHIFT 6
#define DMAE_CMD_RESERVED1 (0x1<<7)
#define DMAE_CMD_RESERVED1_SHIFT 7
#define DMAE_CMD_DST_VFID (0x3F<<8)
#define DMAE_CMD_DST_VFID_SHIFT 8
#define DMAE_CMD_DST_VFPF (0x1<<14)
#define DMAE_CMD_DST_VFPF_SHIFT 14
#define DMAE_CMD_RESERVED2 (0x1<<15)
#define DMAE_CMD_RESERVED2_SHIFT 15
#endif
uint32_t comp_addr_lo ;
uint32_t comp_addr_hi ;
uint32_t comp_val ;
uint32_t crc32 ;
uint32_t crc32_c ;
#if defined(__BIG_ENDIAN)
uint16_t crc16_c ;
uint16_t crc16 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t crc16 ;
uint16_t crc16_c ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t reserved3;
uint16_t crc_t10 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t crc_t10 ;
uint16_t reserved3;
#endif
#if defined(__BIG_ENDIAN)
uint16_t xsum8 ;
uint16_t xsum16 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t xsum16 ;
uint16_t xsum8 ;
#endif
};
struct doorbell_hdr_t
{
uint8_t data;
#define DOORBELL_HDR_T_RX (0x1<<0)
#define DOORBELL_HDR_T_RX_SHIFT 0
#define DOORBELL_HDR_T_DB_TYPE (0x1<<1)
#define DOORBELL_HDR_T_DB_TYPE_SHIFT 1
#define DOORBELL_HDR_T_DPM_SIZE (0x3<<2)
#define DOORBELL_HDR_T_DPM_SIZE_SHIFT 2
#define DOORBELL_HDR_T_CONN_TYPE (0xF<<4)
#define DOORBELL_HDR_T_CONN_TYPE_SHIFT 4
};
struct eth_tx_doorbell
{
#if defined(__BIG_ENDIAN)
uint16_t npackets ;
uint8_t params;
#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
#define ETH_TX_DOORBELL_SPARE (0x1<<7)
#define ETH_TX_DOORBELL_SPARE_SHIFT 7
struct doorbell_hdr_t hdr;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr_t hdr;
uint8_t params;
#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
#define ETH_TX_DOORBELL_SPARE (0x1<<7)
#define ETH_TX_DOORBELL_SPARE_SHIFT 7
uint16_t npackets ;
#endif
};
struct hc_status_block_e1x
{
uint16_t index_values[HC_SB_MAX_INDICES_E1X] ;
uint16_t running_index[HC_SB_MAX_SM] ;
uint32_t rsrv[11];
};
struct host_hc_status_block_e1x
{
struct hc_status_block_e1x sb ;
};
struct hc_status_block_e2
{
uint16_t index_values[HC_SB_MAX_INDICES_E2] ;
uint16_t running_index[HC_SB_MAX_SM] ;
uint32_t reserved[11];
};
struct host_hc_status_block_e2
{
struct hc_status_block_e2 sb ;
};
struct hc_sp_status_block
{
uint16_t index_values[HC_SP_SB_MAX_INDICES] ;
uint16_t running_index ;
uint16_t rsrv;
uint32_t rsrv1;
};
struct host_sp_status_block
{
struct atten_sp_status_block atten_status_block ;
struct hc_sp_status_block sp_sb ;
};
struct igu_ack_register
{
#if defined(__BIG_ENDIAN)
uint16_t sb_id_and_flags;
#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
uint16_t status_block_index ;
#elif defined(__LITTLE_ENDIAN)
uint16_t status_block_index ;
uint16_t sb_id_and_flags;
#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
#endif
};
struct igu_backward_compatible
{
uint32_t sb_id_and_flags;
#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
uint32_t reserved_2;
};
struct igu_regular
{
uint32_t sb_id_and_flags;
#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
#define IGU_REGULAR_SB_INDEX_SHIFT 0
#define IGU_REGULAR_RESERVED0 (0x1<<20)
#define IGU_REGULAR_RESERVED0_SHIFT 20
#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
#define IGU_REGULAR_BUPDATE (0x1<<24)
#define IGU_REGULAR_BUPDATE_SHIFT 24
#define IGU_REGULAR_ENABLE_INT (0x3<<25)
#define IGU_REGULAR_ENABLE_INT_SHIFT 25
#define IGU_REGULAR_RESERVED_1 (0x1<<27)
#define IGU_REGULAR_RESERVED_1_SHIFT 27
#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
#define IGU_REGULAR_CLEANUP_SET (0x1<<30)
#define IGU_REGULAR_CLEANUP_SET_SHIFT 30
#define IGU_REGULAR_BCLEANUP (0x1<<31)
#define IGU_REGULAR_BCLEANUP_SHIFT 31
uint32_t reserved_2;
};
union igu_consprod_reg
{
struct igu_regular regular;
struct igu_backward_compatible backward_compatible;
};
enum igu_ctrl_cmd
{
IGU_CTRL_CMD_TYPE_RD,
IGU_CTRL_CMD_TYPE_WR,
MAX_IGU_CTRL_CMD};
struct igu_ctrl_reg
{
uint32_t ctrl_data;
#define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
#define IGU_CTRL_REG_ADDRESS_SHIFT 0
#define IGU_CTRL_REG_FID (0x7F<<12)
#define IGU_CTRL_REG_FID_SHIFT 12
#define IGU_CTRL_REG_RESERVED (0x1<<19)
#define IGU_CTRL_REG_RESERVED_SHIFT 19
#define IGU_CTRL_REG_TYPE (0x1<<20)
#define IGU_CTRL_REG_TYPE_SHIFT 20
#define IGU_CTRL_REG_UNUSED (0x7FF<<21)
#define IGU_CTRL_REG_UNUSED_SHIFT 21
};
enum igu_int_cmd
{
IGU_INT_ENABLE,
IGU_INT_DISABLE,
IGU_INT_NOP,
IGU_INT_NOP2,
MAX_IGU_INT_CMD};
enum igu_seg_access
{
IGU_SEG_ACCESS_NORM,
IGU_SEG_ACCESS_DEF,
IGU_SEG_ACCESS_ATTN,
MAX_IGU_SEG_ACCESS};
struct iscsi_tx_doorbell
{
#if defined(__BIG_ENDIAN)
uint16_t reserved ;
uint8_t params;
#define ISCSI_TX_DOORBELL_NUM_WQES (0x3F<<0)
#define ISCSI_TX_DOORBELL_NUM_WQES_SHIFT 0
#define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
#define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
#define ISCSI_TX_DOORBELL_SPARE (0x1<<7)
#define ISCSI_TX_DOORBELL_SPARE_SHIFT 7
struct doorbell_hdr_t hdr;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr_t hdr;
uint8_t params;
#define ISCSI_TX_DOORBELL_NUM_WQES (0x3F<<0)
#define ISCSI_TX_DOORBELL_NUM_WQES_SHIFT 0
#define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
#define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
#define ISCSI_TX_DOORBELL_SPARE (0x1<<7)
#define ISCSI_TX_DOORBELL_SPARE_SHIFT 7
uint16_t reserved ;
#endif
};
struct parsing_flags
{
uint16_t flags;
#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
#define PARSING_FLAGS_INNER_VLAN_EXIST (0x1<<1)
#define PARSING_FLAGS_INNER_VLAN_EXIST_SHIFT 1
#define PARSING_FLAGS_OUTER_VLAN_EXIST (0x1<<2)
#define PARSING_FLAGS_OUTER_VLAN_EXIST_SHIFT 2
#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
#define PARSING_FLAGS_LLC_SNAP (0x1<<13)
#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
#define PARSING_FLAGS_RESERVED0 (0x3<<14)
#define PARSING_FLAGS_RESERVED0_SHIFT 14
};
enum prs_flags_ack_type
{
PRS_FLAG_PUREACK_PIGGY,
PRS_FLAG_PUREACK_PURE,
MAX_PRS_FLAGS_ACK_TYPE};
enum prs_flags_eth_addr_type
{
PRS_FLAG_ETHTYPE_NON_UNICAST,
PRS_FLAG_ETHTYPE_UNICAST,
MAX_PRS_FLAGS_ETH_ADDR_TYPE};
enum prs_flags_over_eth
{
PRS_FLAG_OVERETH_UNKNOWN,
PRS_FLAG_OVERETH_IPV4,
PRS_FLAG_OVERETH_IPV6,
PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
MAX_PRS_FLAGS_OVER_ETH};
enum prs_flags_over_ip
{
PRS_FLAG_OVERIP_UNKNOWN,
PRS_FLAG_OVERIP_TCP,
PRS_FLAG_OVERIP_UDP,
MAX_PRS_FLAGS_OVER_IP};
struct sdm_op_gen
{
uint32_t command;
#define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
#define SDM_OP_GEN_COMP_TYPE (0x7<<5)
#define SDM_OP_GEN_COMP_TYPE_SHIFT 5
#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
#define SDM_OP_GEN_RESERVED (0x7FFF<<17)
#define SDM_OP_GEN_RESERVED_SHIFT 17
};
struct timers_block_context
{
uint32_t __client0 ;
uint32_t __client1 ;
uint32_t __client2 ;
uint32_t flags;
#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
};
struct toe_adv_wnd_doorbell
{
#if defined(__BIG_ENDIAN)
uint16_t wnd_sz_lsb ;
uint8_t wnd_sz_msb ;
struct doorbell_hdr_t hdr ;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr_t hdr ;
uint8_t wnd_sz_msb ;
uint16_t wnd_sz_lsb ;
#endif
};
struct toe_rx_bds_doorbell
{
#if defined(__BIG_ENDIAN)
uint16_t nbds ;
uint8_t params;
#define TOE_RX_BDS_DOORBELL_RESERVED (0x1F<<0)
#define TOE_RX_BDS_DOORBELL_RESERVED_SHIFT 0
#define TOE_RX_BDS_DOORBELL_OPCODE (0x7<<5)
#define TOE_RX_BDS_DOORBELL_OPCODE_SHIFT 5
struct doorbell_hdr_t hdr;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr_t hdr;
uint8_t params;
#define TOE_RX_BDS_DOORBELL_RESERVED (0x1F<<0)
#define TOE_RX_BDS_DOORBELL_RESERVED_SHIFT 0
#define TOE_RX_BDS_DOORBELL_OPCODE (0x7<<5)
#define TOE_RX_BDS_DOORBELL_OPCODE_SHIFT 5
uint16_t nbds ;
#endif
};
struct toe_rx_bytes_and_bds_doorbell
{
#if defined(__BIG_ENDIAN)
uint16_t nbytes ;
uint8_t params;
#define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS (0x1F<<0)
#define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS_SHIFT 0
#define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE (0x7<<5)
#define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE_SHIFT 5
struct doorbell_hdr_t hdr;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr_t hdr;
uint8_t params;
#define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS (0x1F<<0)
#define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS_SHIFT 0
#define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE (0x7<<5)
#define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE_SHIFT 5
uint16_t nbytes ;
#endif
};
struct toe_rx_byte_doorbell
{
#if defined(__BIG_ENDIAN)
uint16_t nbytes_lsb ;
uint8_t params;
#define TOE_RX_BYTE_DOORBELL_NBYTES_MSB (0x1F<<0)
#define TOE_RX_BYTE_DOORBELL_NBYTES_MSB_SHIFT 0
#define TOE_RX_BYTE_DOORBELL_OPCODE (0x7<<5)
#define TOE_RX_BYTE_DOORBELL_OPCODE_SHIFT 5
struct doorbell_hdr_t hdr;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr_t hdr;
uint8_t params;
#define TOE_RX_BYTE_DOORBELL_NBYTES_MSB (0x1F<<0)
#define TOE_RX_BYTE_DOORBELL_NBYTES_MSB_SHIFT 0
#define TOE_RX_BYTE_DOORBELL_OPCODE (0x7<<5)
#define TOE_RX_BYTE_DOORBELL_OPCODE_SHIFT 5
uint16_t nbytes_lsb ;
#endif
};
struct toe_rx_grq_doorbell
{
#if defined(__BIG_ENDIAN)
uint16_t nbytes_lsb ;
uint8_t params;
#define TOE_RX_GRQ_DOORBELL_NBYTES_MSB (0x1F<<0)
#define TOE_RX_GRQ_DOORBELL_NBYTES_MSB_SHIFT 0
#define TOE_RX_GRQ_DOORBELL_OPCODE (0x7<<5)
#define TOE_RX_GRQ_DOORBELL_OPCODE_SHIFT 5
struct doorbell_hdr_t hdr;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr_t hdr;
uint8_t params;
#define TOE_RX_GRQ_DOORBELL_NBYTES_MSB (0x1F<<0)
#define TOE_RX_GRQ_DOORBELL_NBYTES_MSB_SHIFT 0
#define TOE_RX_GRQ_DOORBELL_OPCODE (0x7<<5)
#define TOE_RX_GRQ_DOORBELL_OPCODE_SHIFT 5
uint16_t nbytes_lsb ;
#endif
};
struct toe_tx_doorbell
{
#if defined(__BIG_ENDIAN)
uint16_t nbytes ;
uint8_t params;
#define TOE_TX_DOORBELL_NUM_BDS (0x3F<<0)
#define TOE_TX_DOORBELL_NUM_BDS_SHIFT 0
#define TOE_TX_DOORBELL_TX_FIN_FLAG (0x1<<6)
#define TOE_TX_DOORBELL_TX_FIN_FLAG_SHIFT 6
#define TOE_TX_DOORBELL_FLUSH (0x1<<7)
#define TOE_TX_DOORBELL_FLUSH_SHIFT 7
struct doorbell_hdr_t hdr;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr_t hdr;
uint8_t params;
#define TOE_TX_DOORBELL_NUM_BDS (0x3F<<0)
#define TOE_TX_DOORBELL_NUM_BDS_SHIFT 0
#define TOE_TX_DOORBELL_TX_FIN_FLAG (0x1<<6)
#define TOE_TX_DOORBELL_TX_FIN_FLAG_SHIFT 6
#define TOE_TX_DOORBELL_FLUSH (0x1<<7)
#define TOE_TX_DOORBELL_FLUSH_SHIFT 7
uint16_t nbytes ;
#endif
};
struct tstorm_eth_ag_context
{
uint32_t __reserved0[14];
};
struct tstorm_fcoe_extra_ag_context_section
{
uint32_t __agg_val1 ;
#if defined(__BIG_ENDIAN)
uint8_t __tcp_agg_vars2 ;
uint8_t __agg_val3 ;
uint16_t __agg_val2 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_val2 ;
uint8_t __agg_val3 ;
uint8_t __tcp_agg_vars2 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __agg_val5;
uint8_t __agg_val6;
uint8_t __tcp_agg_vars3 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __tcp_agg_vars3 ;
uint8_t __agg_val6;
uint16_t __agg_val5;
#endif
uint32_t __lcq_prod ;
uint32_t rtt_seq ;
uint32_t rtt_time ;
uint32_t __reserved66;
uint32_t wnd_right_edge ;
uint32_t tcp_agg_vars1;
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9)
#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN_SHIFT 9
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
uint32_t snd_max ;
uint32_t __lcq_cons ;
uint32_t __reserved2;
};
struct tstorm_fcoe_ag_context
{
#if defined(__BIG_ENDIAN)
uint16_t ulp_credit;
uint8_t agg_vars1;
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
uint8_t state ;
#elif defined(__LITTLE_ENDIAN)
uint8_t state ;
uint8_t agg_vars1;
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
uint16_t ulp_credit;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __agg_val4;
uint16_t agg_vars2;
#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
#elif defined(__LITTLE_ENDIAN)
uint16_t agg_vars2;
#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
uint16_t __agg_val4;
#endif
struct tstorm_fcoe_extra_ag_context_section __extra_section ;
};
struct tstorm_iscsi_tcp_ag_context_section
{
uint32_t __agg_val1 ;
#if defined(__BIG_ENDIAN)
uint8_t __tcp_agg_vars2 ;
uint8_t __agg_val3 ;
uint16_t __agg_val2 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_val2 ;
uint8_t __agg_val3 ;
uint8_t __tcp_agg_vars2 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __agg_val5;
uint8_t __agg_val6;
uint8_t __tcp_agg_vars3 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __tcp_agg_vars3 ;
uint8_t __agg_val6;
uint16_t __agg_val5;
#endif
uint32_t snd_nxt ;
uint32_t rtt_seq ;
uint32_t rtt_time ;
uint32_t wnd_right_edge_local;
uint32_t wnd_right_edge ;
uint32_t tcp_agg_vars1;
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
#define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
#define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
#define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
#define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
#define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
#define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
#define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
#define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
uint32_t snd_max ;
uint32_t snd_una ;
uint32_t __reserved2;
};
struct tstorm_iscsi_ag_context
{
#if defined(__BIG_ENDIAN)
uint16_t ulp_credit;
uint8_t agg_vars1;
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
#define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4)
#define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
#define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6)
#define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6
#define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7)
#define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7
uint8_t state ;
#elif defined(__LITTLE_ENDIAN)
uint8_t state ;
uint8_t agg_vars1;
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
#define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4)
#define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
#define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6)
#define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6
#define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7)
#define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7
uint16_t ulp_credit;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __agg_val4;
uint16_t agg_vars2;
#define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0)
#define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0
#define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1)
#define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1
#define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2)
#define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2
#define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4)
#define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4
#define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6)
#define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6
#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8)
#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8
#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10)
#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10
#define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11)
#define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
#define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12)
#define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12
#define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13)
#define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13
#define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
#define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
#define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
#define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
#elif defined(__LITTLE_ENDIAN)
uint16_t agg_vars2;
#define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0)
#define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0
#define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1)
#define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1
#define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2)
#define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2
#define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4)
#define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4
#define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6)
#define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6
#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8)
#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8
#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10)
#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10
#define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11)
#define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
#define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12)
#define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12
#define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13)
#define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13
#define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
#define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
#define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
#define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
uint16_t __agg_val4;
#endif
struct tstorm_iscsi_tcp_ag_context_section tcp ;
};
struct tstorm_tcp_tcp_ag_context_section
{
uint32_t __agg_val1 ;
#if defined(__BIG_ENDIAN)
uint8_t __tcp_agg_vars2 ;
uint8_t __agg_val3 ;
uint16_t __agg_val2 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_val2 ;
uint8_t __agg_val3 ;
uint8_t __tcp_agg_vars2 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __agg_val5;
uint8_t __agg_val6;
uint8_t __tcp_agg_vars3 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __tcp_agg_vars3 ;
uint8_t __agg_val6;
uint16_t __agg_val5;
#endif
uint32_t snd_nxt ;
uint32_t rtt_seq ;
uint32_t rtt_time ;
uint32_t __reserved66;
uint32_t wnd_right_edge ;
uint32_t tcp_agg_vars1;
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
uint32_t snd_max ;
uint32_t snd_una ;
uint32_t __reserved2;
};
struct tstorm_toe_tcp_ag_context_section
{
uint32_t __agg_val1 ;
#if defined(__BIG_ENDIAN)
uint8_t __tcp_agg_vars2 ;
uint8_t __agg_val3 ;
uint16_t __agg_val2 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_val2 ;
uint8_t __agg_val3 ;
uint8_t __tcp_agg_vars2 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __agg_val5;
uint8_t __agg_val6;
uint8_t __tcp_agg_vars3 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __tcp_agg_vars3 ;
uint8_t __agg_val6;
uint16_t __agg_val5;
#endif
uint32_t snd_nxt ;
uint32_t rtt_seq ;
uint32_t rtt_time ;
uint32_t __reserved66;
uint32_t wnd_right_edge ;
uint32_t tcp_agg_vars1;
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED52 (0x3<<2)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED52_SHIFT 2
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_WND_UPD_CF_EN (0x1<<6)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_WND_UPD_CF_EN_SHIFT 6
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_NEWRTTSAMPLE (0x1<<10)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_NEWRTTSAMPLE_SHIFT 10
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED55 (0x1<<11)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED55_SHIFT 11
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX1_CF_EN (0x1<<12)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX1_CF_EN_SHIFT 12
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX2_CF_EN (0x1<<13)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX2_CF_EN_SHIFT 13
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED56 (0x3<<14)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED56_SHIFT 14
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED57 (0x3<<16)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED57_SHIFT 16
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
#define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
#define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
#define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
#define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
#define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
#define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
#define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
#define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
uint32_t snd_max ;
uint32_t snd_una ;
uint32_t __reserved2;
};
struct tstorm_toe_ag_context
{
#if defined(__BIG_ENDIAN)
uint16_t reserved54;
uint8_t agg_vars1;
#define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define TSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<1)
#define TSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 1
#define TSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<2)
#define TSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 2
#define TSTORM_TOE_AG_CONTEXT_RESERVED53 (0x1<<3)
#define TSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 3
#define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4)
#define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
#define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
#define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
#define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
#define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
uint8_t __state ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __state ;
uint8_t agg_vars1;
#define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define TSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<1)
#define TSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 1
#define TSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<2)
#define TSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 2
#define TSTORM_TOE_AG_CONTEXT_RESERVED53 (0x1<<3)
#define TSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 3
#define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4)
#define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
#define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
#define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
#define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
#define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
uint16_t reserved54;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __agg_val4;
uint16_t agg_vars2;
#define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
#define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
#define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
#define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
#define __TSTORM_TOE_AG_CONTEXT_AUX4_CF (0x3<<2)
#define __TSTORM_TOE_AG_CONTEXT_AUX4_CF_SHIFT 2
#define __TSTORM_TOE_AG_CONTEXT_AUX5_CF (0x3<<4)
#define __TSTORM_TOE_AG_CONTEXT_AUX5_CF_SHIFT 4
#define __TSTORM_TOE_AG_CONTEXT_AUX6_CF (0x3<<6)
#define __TSTORM_TOE_AG_CONTEXT_AUX6_CF_SHIFT 6
#define __TSTORM_TOE_AG_CONTEXT_AUX7_CF (0x3<<8)
#define __TSTORM_TOE_AG_CONTEXT_AUX7_CF_SHIFT 8
#define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
#define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
#define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11)
#define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN (0x1<<12)
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN_SHIFT 12
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN (0x1<<13)
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN_SHIFT 13
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN (0x1<<14)
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN_SHIFT 14
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN (0x1<<15)
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN_SHIFT 15
#elif defined(__LITTLE_ENDIAN)
uint16_t agg_vars2;
#define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
#define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
#define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
#define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
#define __TSTORM_TOE_AG_CONTEXT_AUX4_CF (0x3<<2)
#define __TSTORM_TOE_AG_CONTEXT_AUX4_CF_SHIFT 2
#define __TSTORM_TOE_AG_CONTEXT_AUX5_CF (0x3<<4)
#define __TSTORM_TOE_AG_CONTEXT_AUX5_CF_SHIFT 4
#define __TSTORM_TOE_AG_CONTEXT_AUX6_CF (0x3<<6)
#define __TSTORM_TOE_AG_CONTEXT_AUX6_CF_SHIFT 6
#define __TSTORM_TOE_AG_CONTEXT_AUX7_CF (0x3<<8)
#define __TSTORM_TOE_AG_CONTEXT_AUX7_CF_SHIFT 8
#define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
#define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
#define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11)
#define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN (0x1<<12)
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN_SHIFT 12
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN (0x1<<13)
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN_SHIFT 13
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN (0x1<<14)
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN_SHIFT 14
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN (0x1<<15)
#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN_SHIFT 15
uint16_t __agg_val4;
#endif
struct tstorm_toe_tcp_ag_context_section tcp ;
};
struct ustorm_eth_ag_context
{
uint32_t __reserved0;
#if defined(__BIG_ENDIAN)
uint8_t cdu_usage ;
uint8_t __reserved2;
uint16_t __reserved1;
#elif defined(__LITTLE_ENDIAN)
uint16_t __reserved1;
uint8_t __reserved2;
uint8_t cdu_usage ;
#endif
uint32_t __reserved3[6];
};
struct ustorm_fcoe_ag_context
{
#if defined(__BIG_ENDIAN)
uint8_t __aux_counter_flags ;
uint8_t agg_vars2;
#define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
#define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
uint8_t agg_vars1;
#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
#define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
#define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
uint8_t state ;
#elif defined(__LITTLE_ENDIAN)
uint8_t state ;
uint8_t agg_vars1;
#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
#define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
#define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
uint8_t agg_vars2;
#define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
#define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
uint8_t __aux_counter_flags ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t cdu_usage ;
uint8_t agg_misc2;
uint16_t pbf_tx_seq_ack ;
#elif defined(__LITTLE_ENDIAN)
uint16_t pbf_tx_seq_ack ;
uint8_t agg_misc2;
uint8_t cdu_usage ;
#endif
uint32_t agg_misc4;
#if defined(__BIG_ENDIAN)
uint8_t agg_val3_th;
uint8_t agg_val3;
uint16_t agg_misc3;
#elif defined(__LITTLE_ENDIAN)
uint16_t agg_misc3;
uint8_t agg_val3;
uint8_t agg_val3_th;
#endif
uint32_t expired_task_id ;
uint32_t agg_misc4_th;
#if defined(__BIG_ENDIAN)
uint16_t cq_prod ;
uint16_t cq_cons ;
#elif defined(__LITTLE_ENDIAN)
uint16_t cq_cons ;
uint16_t cq_prod ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __reserved2;
uint8_t decision_rules;
#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
#define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
#define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
uint8_t decision_rule_enable_bits;
#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
#elif defined(__LITTLE_ENDIAN)
uint8_t decision_rule_enable_bits;
#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
uint8_t decision_rules;
#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
#define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
#define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
uint16_t __reserved2;
#endif
};
struct ustorm_iscsi_ag_context
{
#if defined(__BIG_ENDIAN)
uint8_t __aux_counter_flags ;
uint8_t agg_vars2;
#define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0)
#define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0
#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2)
#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2
#define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
#define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
uint8_t agg_vars1;
#define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
#define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4)
#define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4
#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6)
#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6
uint8_t state ;
#elif defined(__LITTLE_ENDIAN)
uint8_t state ;
uint8_t agg_vars1;
#define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
#define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4)
#define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4
#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6)
#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6
uint8_t agg_vars2;
#define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0)
#define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0
#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2)
#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2
#define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
#define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
uint8_t __aux_counter_flags ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t cdu_usage ;
uint8_t agg_misc2;
uint16_t __cq_local_comp_itt_val ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __cq_local_comp_itt_val ;
uint8_t agg_misc2;
uint8_t cdu_usage ;
#endif
uint32_t agg_misc4;
#if defined(__BIG_ENDIAN)
uint8_t agg_val3_th;
uint8_t agg_val3;
uint16_t agg_misc3;
#elif defined(__LITTLE_ENDIAN)
uint16_t agg_misc3;
uint8_t agg_val3;
uint8_t agg_val3_th;
#endif
uint32_t agg_val1;
uint32_t agg_misc4_th;
#if defined(__BIG_ENDIAN)
uint16_t agg_val2_th;
uint16_t agg_val2;
#elif defined(__LITTLE_ENDIAN)
uint16_t agg_val2;
uint16_t agg_val2_th;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __reserved2;
uint8_t decision_rules;
#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0)
#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6)
#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
#define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7)
#define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7
uint8_t decision_rule_enable_bits;
#define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0)
#define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0
#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
#define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2)
#define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2
#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
#define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4)
#define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4
#define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5)
#define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5
#define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
#define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
#define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
#define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
#elif defined(__LITTLE_ENDIAN)
uint8_t decision_rule_enable_bits;
#define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0)
#define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0
#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
#define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2)
#define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2
#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
#define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4)
#define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4
#define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5)
#define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5
#define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
#define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
#define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
#define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
uint8_t decision_rules;
#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0)
#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6)
#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
#define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7)
#define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7
uint16_t __reserved2;
#endif
};
struct ustorm_toe_ag_context
{
#if defined(__BIG_ENDIAN)
uint8_t __aux_counter_flags ;
uint8_t __agg_vars2 ;
uint8_t __agg_vars1 ;
uint8_t __state ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __state ;
uint8_t __agg_vars1 ;
uint8_t __agg_vars2 ;
uint8_t __aux_counter_flags ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t cdu_usage ;
uint8_t __agg_misc2;
uint16_t __agg_misc1;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_misc1;
uint8_t __agg_misc2;
uint8_t cdu_usage ;
#endif
uint32_t __agg_misc4;
#if defined(__BIG_ENDIAN)
uint8_t __agg_val3_th;
uint8_t __agg_val3;
uint16_t __agg_misc3;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_misc3;
uint8_t __agg_val3;
uint8_t __agg_val3_th;
#endif
uint32_t driver_doorbell_info_ptr_lo ;
uint32_t driver_doorbell_info_ptr_hi ;
#if defined(__BIG_ENDIAN)
uint16_t __agg_val2_th;
uint16_t rq_prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t rq_prod ;
uint16_t __agg_val2_th;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __reserved2;
uint8_t decision_rules;
#define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0)
#define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
#define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
#define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
#define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6)
#define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
#define __USTORM_TOE_AG_CONTEXT_RESERVED1 (0x1<<7)
#define __USTORM_TOE_AG_CONTEXT_RESERVED1_SHIFT 7
uint8_t __decision_rule_enable_bits ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __decision_rule_enable_bits ;
uint8_t decision_rules;
#define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0)
#define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
#define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
#define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
#define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6)
#define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
#define __USTORM_TOE_AG_CONTEXT_RESERVED1 (0x1<<7)
#define __USTORM_TOE_AG_CONTEXT_RESERVED1_SHIFT 7
uint16_t __reserved2;
#endif
};
struct xstorm_eth_ag_context
{
uint32_t reserved0;
#if defined(__BIG_ENDIAN)
uint8_t cdu_reserved ;
uint8_t reserved2;
uint16_t reserved1;
#elif defined(__LITTLE_ENDIAN)
uint16_t reserved1;
uint8_t reserved2;
uint8_t cdu_reserved ;
#endif
uint32_t reserved3[30];
};
struct xstorm_fcoe_extra_ag_context_section
{
#if defined(__BIG_ENDIAN)
uint8_t tcp_agg_vars1;
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
uint8_t __reserved_da_cnt ;
uint16_t __mtu ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __mtu ;
uint8_t __reserved_da_cnt ;
uint8_t tcp_agg_vars1;
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
#endif
uint32_t snd_nxt ;
uint32_t __xfrqe_bd_addr_lo ;
uint32_t __xfrqe_bd_addr_hi ;
uint32_t __xfrqe_data1 ;
#if defined(__BIG_ENDIAN)
uint8_t __agg_val8_th ;
uint8_t __tx_dest ;
uint16_t tcp_agg_vars2;
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
#elif defined(__LITTLE_ENDIAN)
uint16_t tcp_agg_vars2;
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
uint8_t __tx_dest ;
uint8_t __agg_val8_th ;
#endif
uint32_t __sq_base_addr_lo ;
uint32_t __sq_base_addr_hi ;
uint32_t __xfrq_base_addr_lo ;
uint32_t __xfrq_base_addr_hi ;
#if defined(__BIG_ENDIAN)
uint16_t __xfrq_cons ;
uint16_t __xfrq_prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __xfrq_prod ;
uint16_t __xfrq_cons ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t __tcp_agg_vars5 ;
uint8_t __tcp_agg_vars4 ;
uint8_t __tcp_agg_vars3 ;
uint8_t __reserved_force_pure_ack_cnt ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __reserved_force_pure_ack_cnt ;
uint8_t __tcp_agg_vars3 ;
uint8_t __tcp_agg_vars4 ;
uint8_t __tcp_agg_vars5 ;
#endif
uint32_t __tcp_agg_vars6 ;
#if defined(__BIG_ENDIAN)
uint16_t __xfrqe_mng ;
uint16_t __tcp_agg_vars7 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __tcp_agg_vars7 ;
uint16_t __xfrqe_mng ;
#endif
uint32_t __xfrqe_data0 ;
uint32_t __agg_val10_th ;
#if defined(__BIG_ENDIAN)
uint16_t __reserved3;
uint8_t __reserved2;
uint8_t __da_only_cnt ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __da_only_cnt ;
uint8_t __reserved2;
uint16_t __reserved3;
#endif
};
struct xstorm_fcoe_ag_context
{
#if defined(__BIG_ENDIAN)
uint16_t agg_val1 ;
uint8_t agg_vars1;
#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
uint8_t __state ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __state ;
uint8_t agg_vars1;
#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
uint16_t agg_val1 ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t cdu_reserved ;
uint8_t __agg_vars4 ;
uint8_t agg_vars3;
#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
uint8_t agg_vars2;
#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
#elif defined(__LITTLE_ENDIAN)
uint8_t agg_vars2;
#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
uint8_t agg_vars3;
#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
uint8_t __agg_vars4 ;
uint8_t cdu_reserved ;
#endif
uint32_t more_to_send ;
#if defined(__BIG_ENDIAN)
uint16_t agg_vars5;
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
uint16_t sq_cons ;
#elif defined(__LITTLE_ENDIAN)
uint16_t sq_cons ;
uint16_t agg_vars5;
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
#endif
struct xstorm_fcoe_extra_ag_context_section __extra_section ;
#if defined(__BIG_ENDIAN)
uint16_t agg_vars7;
#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
uint8_t agg_val3_th ;
uint8_t agg_vars6;
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
#elif defined(__LITTLE_ENDIAN)
uint8_t agg_vars6;
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
uint8_t agg_val3_th ;
uint16_t agg_vars7;
#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
#endif
#if defined(__BIG_ENDIAN)
uint16_t __agg_val11_th ;
uint16_t __agg_val11 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_val11 ;
uint16_t __agg_val11_th ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t __reserved1;
uint8_t __agg_val6_th ;
uint16_t __agg_val9 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_val9 ;
uint8_t __agg_val6_th ;
uint8_t __reserved1;
#endif
#if defined(__BIG_ENDIAN)
uint16_t confq_cons ;
uint16_t confq_prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t confq_prod ;
uint16_t confq_cons ;
#endif
uint32_t agg_varint8_t;
#define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)
#define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2_SHIFT 0
#define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
#define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24
#if defined(__BIG_ENDIAN)
uint16_t __cache_wqe_db ;
uint16_t sq_prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t sq_prod ;
uint16_t __cache_wqe_db ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t agg_val3 ;
uint8_t agg_val6 ;
uint8_t agg_val5_th ;
uint8_t agg_val5 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t agg_val5 ;
uint8_t agg_val5_th ;
uint8_t agg_val6 ;
uint8_t agg_val3 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __agg_misc1 ;
uint16_t agg_limit1 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t agg_limit1 ;
uint16_t __agg_misc1 ;
#endif
uint32_t completion_seq ;
uint32_t confq_pbl_base_lo ;
uint32_t confq_pbl_base_hi ;
};
struct xstorm_tcp_tcp_ag_context_section
{
#if defined(__BIG_ENDIAN)
uint8_t tcp_agg_vars1;
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
uint8_t __da_cnt ;
uint16_t mss ;
#elif defined(__LITTLE_ENDIAN)
uint16_t mss ;
uint8_t __da_cnt ;
uint8_t tcp_agg_vars1;
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
#endif
uint32_t snd_nxt ;
uint32_t tx_wnd ;
uint32_t snd_una ;
uint32_t local_adv_wnd ;
#if defined(__BIG_ENDIAN)
uint8_t __agg_val8_th ;
uint8_t __tx_dest ;
uint16_t tcp_agg_vars2;
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0)
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5)
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
#elif defined(__LITTLE_ENDIAN)
uint16_t tcp_agg_vars2;
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0)
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5)
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
uint8_t __tx_dest ;
uint8_t __agg_val8_th ;
#endif
uint32_t ack_to_far_end ;
uint32_t rto_timer ;
uint32_t ka_timer ;
uint32_t ts_to_echo ;
#if defined(__BIG_ENDIAN)
uint16_t __agg_val7_th ;
uint16_t __agg_val7 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_val7 ;
uint16_t __agg_val7_th ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t __tcp_agg_vars5 ;
uint8_t __tcp_agg_vars4 ;
uint8_t __tcp_agg_vars3 ;
uint8_t __force_pure_ack_cnt ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __force_pure_ack_cnt ;
uint8_t __tcp_agg_vars3 ;
uint8_t __tcp_agg_vars4 ;
uint8_t __tcp_agg_vars5 ;
#endif
uint32_t tcp_agg_vars6;
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26)
#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31)
#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31
#if defined(__BIG_ENDIAN)
uint16_t __agg_misc6 ;
uint16_t __tcp_agg_vars7 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __tcp_agg_vars7 ;
uint16_t __agg_misc6 ;
#endif
uint32_t __agg_val10 ;
uint32_t __agg_val10_th ;
#if defined(__BIG_ENDIAN)
uint16_t __reserved3;
uint8_t __reserved2;
uint8_t __da_only_cnt ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __da_only_cnt ;
uint8_t __reserved2;
uint16_t __reserved3;
#endif
};
struct xstorm_iscsi_ag_context
{
#if defined(__BIG_ENDIAN)
uint16_t agg_val1 ;
uint8_t agg_vars1;
#define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
#define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
#define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
#define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5)
#define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
#define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
#define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
uint8_t state ;
#elif defined(__LITTLE_ENDIAN)
uint8_t state ;
uint8_t agg_vars1;
#define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
#define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
#define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
#define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5)
#define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
#define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
#define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
uint16_t agg_val1 ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t cdu_reserved ;
uint8_t __agg_vars4 ;
uint8_t agg_vars3;
#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
#define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
#define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
uint8_t agg_vars2;
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0)
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
#define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3)
#define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3
#define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4)
#define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
#elif defined(__LITTLE_ENDIAN)
uint8_t agg_vars2;
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0)
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
#define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3)
#define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3
#define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4)
#define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
uint8_t agg_vars3;
#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
#define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
#define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
uint8_t __agg_vars4 ;
uint8_t cdu_reserved ;
#endif
uint32_t more_to_send ;
#if defined(__BIG_ENDIAN)
uint16_t agg_vars5;
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0
#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14
uint16_t sq_cons ;
#elif defined(__LITTLE_ENDIAN)
uint16_t sq_cons ;
uint16_t agg_vars5;
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0
#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14
#endif
struct xstorm_tcp_tcp_ag_context_section tcp ;
#if defined(__BIG_ENDIAN)
uint16_t agg_vars7;
#define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
#define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
#define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3)
#define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3
#define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
#define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6
#define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8)
#define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8
#define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
#define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
#define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
#define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
#define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12)
#define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12
#define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13)
#define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13
#define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14)
#define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14
#define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
#define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
uint8_t agg_val3_th ;
uint8_t agg_vars6;
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6
#elif defined(__LITTLE_ENDIAN)
uint8_t agg_vars6;
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6
uint8_t agg_val3_th ;
uint16_t agg_vars7;
#define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
#define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
#define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3)
#define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3
#define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
#define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
#define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6
#define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8)
#define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8
#define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
#define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
#define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
#define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
#define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12)
#define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12
#define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13)
#define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13
#define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14)
#define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14
#define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
#define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
#endif
#if defined(__BIG_ENDIAN)
uint16_t __agg_val11_th ;
uint16_t __gen_data ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __gen_data ;
uint16_t __agg_val11_th ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t __reserved1;
uint8_t __agg_val6_th ;
uint16_t __agg_val9 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_val9 ;
uint8_t __agg_val6_th ;
uint8_t __reserved1;
#endif
#if defined(__BIG_ENDIAN)
uint16_t hq_prod ;
uint16_t hq_cons ;
#elif defined(__LITTLE_ENDIAN)
uint16_t hq_cons ;
uint16_t hq_prod ;
#endif
uint32_t agg_varint8_t;
#define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)
#define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2_SHIFT 0
#define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
#define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3_SHIFT 24
#if defined(__BIG_ENDIAN)
uint16_t r2tq_prod ;
uint16_t sq_prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t sq_prod ;
uint16_t r2tq_prod ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t agg_val3 ;
uint8_t agg_val6 ;
uint8_t agg_val5_th ;
uint8_t agg_val5 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t agg_val5 ;
uint8_t agg_val5_th ;
uint8_t agg_val6 ;
uint8_t agg_val3 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __agg_misc1 ;
uint16_t agg_limit1 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t agg_limit1 ;
uint16_t __agg_misc1 ;
#endif
uint32_t hq_cons_tcp_seq ;
uint32_t exp_stat_sn ;
uint32_t rst_seq_num ;
};
struct xstorm_toe_tcp_ag_context_section
{
#if defined(__BIG_ENDIAN)
uint8_t tcp_agg_vars1;
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
uint8_t __da_cnt ;
uint16_t mss ;
#elif defined(__LITTLE_ENDIAN)
uint16_t mss ;
uint8_t __da_cnt ;
uint8_t tcp_agg_vars1;
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
#endif
uint32_t snd_nxt ;
uint32_t tx_wnd ;
uint32_t snd_una ;
uint32_t local_adv_wnd ;
#if defined(__BIG_ENDIAN)
uint8_t __agg_val8_th ;
uint8_t __tx_dest ;
uint16_t tcp_agg_vars2;
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0)
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5)
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
#elif defined(__LITTLE_ENDIAN)
uint16_t tcp_agg_vars2;
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0)
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5)
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
uint8_t __tx_dest ;
uint8_t __agg_val8_th ;
#endif
uint32_t ack_to_far_end ;
uint32_t rto_timer ;
uint32_t ka_timer ;
uint32_t ts_to_echo ;
#if defined(__BIG_ENDIAN)
uint16_t __agg_val7_th ;
uint16_t __agg_val7 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_val7 ;
uint16_t __agg_val7_th ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t __tcp_agg_vars5 ;
uint8_t __tcp_agg_vars4 ;
uint8_t __tcp_agg_vars3 ;
uint8_t __force_pure_ack_cnt ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __force_pure_ack_cnt ;
uint8_t __tcp_agg_vars3 ;
uint8_t __tcp_agg_vars4 ;
uint8_t __tcp_agg_vars5 ;
#endif
uint32_t tcp_agg_vars6;
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26)
#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31)
#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31
#if defined(__BIG_ENDIAN)
uint16_t __agg_misc6 ;
uint16_t __tcp_agg_vars7 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __tcp_agg_vars7 ;
uint16_t __agg_misc6 ;
#endif
uint32_t __agg_val10 ;
uint32_t __agg_val10_th ;
#if defined(__BIG_ENDIAN)
uint16_t __reserved3;
uint8_t __reserved2;
uint8_t __da_only_cnt ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __da_only_cnt ;
uint8_t __reserved2;
uint16_t __reserved3;
#endif
};
struct xstorm_toe_ag_context
{
#if defined(__BIG_ENDIAN)
uint16_t agg_val1 ;
uint8_t agg_vars1;
#define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define __XSTORM_TOE_AG_CONTEXT_RESERVED50 (0x1<<1)
#define __XSTORM_TOE_AG_CONTEXT_RESERVED50_SHIFT 1
#define __XSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<2)
#define __XSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 2
#define __XSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<3)
#define __XSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 3
#define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
#define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
#define XSTORM_TOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
#define XSTORM_TOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
#define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG (0x1<<6)
#define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_SHIFT 6
#define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
#define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
uint8_t __state ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __state ;
uint8_t agg_vars1;
#define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
#define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
#define __XSTORM_TOE_AG_CONTEXT_RESERVED50 (0x1<<1)
#define __XSTORM_TOE_AG_CONTEXT_RESERVED50_SHIFT 1
#define __XSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<2)
#define __XSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 2
#define __XSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<3)
#define __XSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 3
#define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
#define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
#define XSTORM_TOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
#define XSTORM_TOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
#define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG (0x1<<6)
#define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_SHIFT 6
#define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
#define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
uint16_t agg_val1 ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t cdu_reserved ;
uint8_t __agg_vars4 ;
uint8_t agg_vars3;
#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
#define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF (0x3<<6)
#define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF_SHIFT 6
uint8_t agg_vars2;
#define __XSTORM_TOE_AG_CONTEXT_DQ_CF (0x3<<0)
#define __XSTORM_TOE_AG_CONTEXT_DQ_CF_SHIFT 0
#define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN (0x1<<2)
#define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN_SHIFT 2
#define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
#define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
#define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
#define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
#define XSTORM_TOE_AG_CONTEXT_RESERVED53 (0x3<<5)
#define XSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 5
#define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
#define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
#elif defined(__LITTLE_ENDIAN)
uint8_t agg_vars2;
#define __XSTORM_TOE_AG_CONTEXT_DQ_CF (0x3<<0)
#define __XSTORM_TOE_AG_CONTEXT_DQ_CF_SHIFT 0
#define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN (0x1<<2)
#define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN_SHIFT 2
#define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
#define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
#define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
#define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
#define XSTORM_TOE_AG_CONTEXT_RESERVED53 (0x3<<5)
#define XSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 5
#define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
#define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
uint8_t agg_vars3;
#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
#define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF (0x3<<6)
#define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF_SHIFT 6
uint8_t __agg_vars4 ;
uint8_t cdu_reserved ;
#endif
uint32_t more_to_send ;
#if defined(__BIG_ENDIAN)
uint16_t agg_vars5;
#define __XSTORM_TOE_AG_CONTEXT_RESERVED54 (0x3<<0)
#define __XSTORM_TOE_AG_CONTEXT_RESERVED54_SHIFT 0
#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
#define __XSTORM_TOE_AG_CONTEXT_RESERVED56 (0x3<<14)
#define __XSTORM_TOE_AG_CONTEXT_RESERVED56_SHIFT 14
uint16_t __agg_val4_th ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_val4_th ;
uint16_t agg_vars5;
#define __XSTORM_TOE_AG_CONTEXT_RESERVED54 (0x3<<0)
#define __XSTORM_TOE_AG_CONTEXT_RESERVED54_SHIFT 0
#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
#define __XSTORM_TOE_AG_CONTEXT_RESERVED56 (0x3<<14)
#define __XSTORM_TOE_AG_CONTEXT_RESERVED56_SHIFT 14
#endif
struct xstorm_toe_tcp_ag_context_section tcp ;
#if defined(__BIG_ENDIAN)
uint16_t __agg_vars7 ;
uint8_t __agg_val3_th ;
uint8_t __agg_vars6 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __agg_vars6 ;
uint8_t __agg_val3_th ;
uint16_t __agg_vars7 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __agg_val11_th ;
uint16_t __agg_val11 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_val11 ;
uint16_t __agg_val11_th ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t __reserved1;
uint8_t __agg_val6_th ;
uint16_t __agg_val9 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_val9 ;
uint8_t __agg_val6_th ;
uint8_t __reserved1;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __agg_val2_th ;
uint16_t cmp_bd_cons ;
#elif defined(__LITTLE_ENDIAN)
uint16_t cmp_bd_cons ;
uint16_t __agg_val2_th ;
#endif
uint32_t __agg_varint8_t ;
#if defined(__BIG_ENDIAN)
uint16_t __agg_misc0 ;
uint16_t __agg_val4 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __agg_val4 ;
uint16_t __agg_misc0 ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t __agg_val3 ;
uint8_t __agg_val6 ;
uint8_t __agg_val5_th ;
uint8_t __agg_val5 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t __agg_val5 ;
uint8_t __agg_val5_th ;
uint8_t __agg_val6 ;
uint8_t __agg_val3 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t __agg_misc1 ;
uint16_t __bd_ind_max_val ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __bd_ind_max_val ;
uint16_t __agg_misc1 ;
#endif
uint32_t cmp_bd_start_seq ;
uint32_t cmp_bd_page_0_to_31 ;
uint32_t cmp_bd_page_32_to_63 ;
};
struct doorbell
{
#if defined(__BIG_ENDIAN)
uint16_t zero_fill2 ;
uint8_t zero_fill1 ;
struct doorbell_hdr_t header;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr_t header;
uint8_t zero_fill1 ;
uint16_t zero_fill2 ;
#endif
};
struct doorbell_set_prod
{
#if defined(__BIG_ENDIAN)
uint16_t prod ;
uint8_t zero_fill1 ;
struct doorbell_hdr_t header;
#elif defined(__LITTLE_ENDIAN)
struct doorbell_hdr_t header;
uint8_t zero_fill1 ;
uint16_t prod ;
#endif
};
struct regpair_native_t
{
uint32_t lo ;
uint32_t hi ;
};
struct regpair_t
{
uint32_t lo ;
uint32_t hi ;
};
enum classify_rule
{
CLASSIFY_RULE_OPCODE_MAC ,
CLASSIFY_RULE_OPCODE_VLAN ,
CLASSIFY_RULE_OPCODE_PAIR ,
CLASSIFY_RULE_OPCODE_IMAC_VNI ,
MAX_CLASSIFY_RULE};
enum classify_rule_action_type
{
CLASSIFY_RULE_REMOVE,
CLASSIFY_RULE_ADD,
MAX_CLASSIFY_RULE_ACTION_TYPE};
struct client_init_general_data
{
uint8_t client_id ;
uint8_t statistics_counter_id ;
uint8_t statistics_en_flg ;
uint8_t is_fcoe_flg ;
uint8_t activate_flg ;
uint8_t sp_client_id ;
uint16_t mtu ;
uint8_t statistics_zero_flg ;
uint8_t func_id ;
uint8_t cos ;
uint8_t traffic_type;
uint8_t fp_hsi_ver ;
uint8_t reserved0[3];
};
struct client_init_rx_data
{
uint8_t tpa_en;
#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)
#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
uint8_t vmqueue_mode_en_flg ;
uint8_t extra_data_over_sgl_en_flg ;
uint8_t cache_line_alignment_log_size ;
uint8_t enable_dynamic_hc ;
uint8_t max_sges_for_packet ;
uint8_t client_qzone_id ;
uint8_t drop_ip_cs_err_flg ;
uint8_t drop_tcp_cs_err_flg ;
uint8_t drop_ttl0_flg ;
uint8_t drop_udp_cs_err_flg ;
uint8_t inner_vlan_removal_enable_flg ;
uint8_t outer_vlan_removal_enable_flg ;
uint8_t status_block_id ;
uint8_t rx_sb_index_number ;
uint8_t dont_verify_rings_pause_thr_flg ;
uint8_t max_tpa_queues ;
uint8_t silent_vlan_removal_flg ;
uint16_t max_bytes_on_bd ;
uint16_t sge_buff_size ;
uint8_t approx_mcast_engine_id ;
uint8_t rss_engine_id ;
struct regpair_t bd_page_base ;
struct regpair_t sge_page_base ;
struct regpair_t cqe_page_base ;
uint8_t is_leading_rss;
uint8_t is_approx_mcast;
uint16_t max_agg_size ;
uint16_t state;
#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
uint16_t cqe_pause_thr_low ;
uint16_t cqe_pause_thr_high ;
uint16_t bd_pause_thr_low ;
uint16_t bd_pause_thr_high ;
uint16_t sge_pause_thr_low ;
uint16_t sge_pause_thr_high ;
uint16_t rx_cos_mask ;
uint16_t silent_vlan_value ;
uint16_t silent_vlan_mask ;
uint8_t handle_ptp_pkts_flg ;
uint8_t reserved6[3];
uint32_t reserved7;
};
struct client_init_tx_data
{
uint8_t enforce_security_flg ;
uint8_t tx_status_block_id ;
uint8_t tx_sb_index_number ;
uint8_t tss_leading_client_id ;
uint8_t tx_switching_flg ;
uint8_t anti_spoofing_flg ;
uint16_t default_vlan ;
struct regpair_t tx_bd_page_base ;
uint16_t state;
#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4)
#define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4
uint8_t default_vlan_flg ;
uint8_t force_default_pri_flg ;
uint8_t tunnel_lso_inc_ip_id ;
uint8_t refuse_outband_vlan_flg ;
uint8_t tunnel_non_lso_pcsum_location ;
uint8_t tunnel_non_lso_outer_ip_csum_location ;
};
struct client_init_ramrod_data
{
struct client_init_general_data general ;
struct client_init_rx_data rx ;
struct client_init_tx_data tx ;
};
struct client_update_ramrod_data
{
uint8_t client_id ;
uint8_t func_id ;
uint8_t inner_vlan_removal_enable_flg ;
uint8_t inner_vlan_removal_change_flg ;
uint8_t outer_vlan_removal_enable_flg ;
uint8_t outer_vlan_removal_change_flg ;
uint8_t anti_spoofing_enable_flg ;
uint8_t anti_spoofing_change_flg ;
uint8_t activate_flg ;
uint8_t activate_change_flg ;
uint16_t default_vlan ;
uint8_t default_vlan_enable_flg;
uint8_t default_vlan_change_flg;
uint16_t silent_vlan_value ;
uint16_t silent_vlan_mask ;
uint8_t silent_vlan_removal_flg ;
uint8_t silent_vlan_change_flg;
uint8_t refuse_outband_vlan_flg ;
uint8_t refuse_outband_vlan_change_flg ;
uint8_t tx_switching_flg ;
uint8_t tx_switching_change_flg ;
uint8_t handle_ptp_pkts_flg ;
uint8_t handle_ptp_pkts_change_flg ;
uint16_t reserved1;
uint32_t echo ;
};
struct cstorm_eth_st_context
{
uint32_t __reserved0[4];
};
struct double_regpair
{
uint32_t regpair0_lo ;
uint32_t regpair0_hi ;
uint32_t regpair1_lo ;
uint32_t regpair1_hi ;
};
enum eth_2nd_parse_bd_type
{
ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL,
MAX_ETH_2ND_PARSE_BD_TYPE};
enum eth_addr_type
{
UNKNOWN_ADDRESS,
UNICAST_ADDRESS,
MULTICAST_ADDRESS,
BROADCAST_ADDRESS,
MAX_ETH_ADDR_TYPE};
struct eth_classify_cmd_header
{
uint8_t cmd_general_data;
#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
uint8_t func_id ;
uint8_t client_id;
uint8_t reserved1;
};
struct eth_classify_header
{
uint8_t rule_cnt ;
uint8_t reserved0;
uint16_t reserved1;
uint32_t echo ;
};
struct eth_classify_imac_vni_cmd
{
struct eth_classify_cmd_header header;
uint32_t vni;
uint16_t imac_lsb;
uint16_t imac_mid;
uint16_t imac_msb;
uint16_t reserved1;
};
struct eth_classify_mac_cmd
{
struct eth_classify_cmd_header header;
uint16_t reserved0;
uint16_t inner_mac;
uint16_t mac_lsb;
uint16_t mac_mid;
uint16_t mac_msb;
uint16_t reserved1;
};
struct eth_classify_pair_cmd
{
struct eth_classify_cmd_header header;
uint16_t reserved0;
uint16_t inner_mac;
uint16_t mac_lsb;
uint16_t mac_mid;
uint16_t mac_msb;
uint16_t vlan;
};
struct eth_classify_vlan_cmd
{
struct eth_classify_cmd_header header;
uint32_t reserved0;
uint32_t reserved1;
uint16_t reserved2;
uint16_t vlan;
};
union eth_classify_rule_cmd
{
struct eth_classify_mac_cmd mac;
struct eth_classify_vlan_cmd vlan;
struct eth_classify_pair_cmd pair;
struct eth_classify_imac_vni_cmd imac_vni;
};
struct eth_classify_rules_ramrod_data
{
struct eth_classify_header header;
union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
};
struct eth_common_ramrod_data
{
uint32_t client_id ;
uint32_t reserved1;
};
struct ustorm_eth_st_context
{
uint32_t reserved0[52];
};
struct tstorm_eth_st_context
{
uint32_t __reserved0[28];
};
struct xstorm_eth_st_context
{
uint32_t reserved0[60];
};
struct eth_context
{
struct ustorm_eth_st_context ustorm_st_context ;
struct tstorm_eth_st_context tstorm_st_context ;
struct xstorm_eth_ag_context xstorm_ag_context ;
struct tstorm_eth_ag_context tstorm_ag_context ;
struct cstorm_eth_ag_context cstorm_ag_context ;
struct ustorm_eth_ag_context ustorm_ag_context ;
struct timers_block_context timers_context ;
struct xstorm_eth_st_context xstorm_st_context ;
struct cstorm_eth_st_context cstorm_st_context ;
};
union eth_sgl_or_raw_data
{
uint16_t sgl[8] ;
uint32_t raw_data[4] ;
};
struct eth_end_agg_rx_cqe
{
uint8_t type_error_flags;
#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
uint8_t reserved1;
uint8_t queue_index ;
uint8_t reserved2;
uint32_t timestamp_delta ;
uint16_t num_of_coalesced_segs ;
uint16_t pkt_len ;
uint8_t pure_ack_count ;
uint8_t reserved3;
uint16_t reserved4;
union eth_sgl_or_raw_data sgl_or_raw_data ;
uint32_t padding[8];
};
struct eth_fast_path_rx_cqe
{
uint8_t type_error_flags;
#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
#define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6)
#define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6
#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7)
#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7
uint8_t status_flags;
#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
uint8_t queue_index ;
uint8_t placement_offset ;
uint32_t rss_hash_result ;
uint16_t vlan_tag ;
uint16_t pkt_len_or_gro_seg_len ;
uint16_t len_on_bd ;
struct parsing_flags pars_flags;
union eth_sgl_or_raw_data sgl_or_raw_data ;
uint8_t tunn_type ;
uint8_t tunn_inner_hdrs_offset ;
uint16_t reserved1;
uint32_t tunn_tenant_id ;
uint32_t padding[5];
uint32_t marker ;
};
struct eth_filter_rules_cmd
{
uint8_t cmd_general_data;
#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
uint8_t func_id ;
uint8_t client_id ;
uint8_t reserved1;
uint16_t state;
#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
uint16_t reserved3;
struct regpair_t reserved4;
};
struct eth_filter_rules_ramrod_data
{
struct eth_classify_header header;
struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
};
enum eth_fp_hsi_ver
{
ETH_FP_HSI_VER_0 ,
ETH_FP_HSI_VER_1 ,
ETH_FP_HSI_VER_2 ,
MAX_ETH_FP_HSI_VER};
struct eth_general_rules_ramrod_data
{
struct eth_classify_header header;
union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
};
struct eth_halt_ramrod_data
{
uint32_t client_id ;
uint32_t reserved0;
};
struct eth_mac_addresses
{
#if defined(__BIG_ENDIAN)
uint16_t dst_mid ;
uint16_t dst_lo ;
#elif defined(__LITTLE_ENDIAN)
uint16_t dst_lo ;
uint16_t dst_mid ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t src_lo ;
uint16_t dst_hi ;
#elif defined(__LITTLE_ENDIAN)
uint16_t dst_hi ;
uint16_t src_lo ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t src_hi ;
uint16_t src_mid ;
#elif defined(__LITTLE_ENDIAN)
uint16_t src_mid ;
uint16_t src_hi ;
#endif
};
struct eth_tunnel_data
{
uint16_t dst_lo ;
uint16_t dst_mid ;
uint16_t dst_hi ;
uint16_t fw_ip_hdr_csum ;
uint16_t pseudo_csum ;
uint8_t ip_hdr_start_inner_w ;
uint8_t flags;
#define ETH_TUNNEL_DATA_IPV6_OUTER (0x1<<0)
#define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0
#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)
#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
};
union eth_mac_addr_or_tunnel_data
{
struct eth_mac_addresses mac_addr ;
struct eth_tunnel_data tunnel_data ;
};
struct eth_multicast_rules_cmd
{
uint8_t cmd_general_data;
#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
uint8_t func_id ;
uint8_t bin_id ;
uint8_t engine_id ;
uint32_t reserved2;
struct regpair_t reserved3;
};
struct eth_multicast_rules_ramrod_data
{
struct eth_classify_header header;
struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
};
struct ramrod_data
{
uint32_t data_lo;
uint32_t data_hi;
};
union eth_ramrod_data
{
struct ramrod_data general;
};
enum eth_rss_hash_type
{
DEFAULT_HASH_TYPE,
IPV4_HASH_TYPE,
TCP_IPV4_HASH_TYPE,
IPV6_HASH_TYPE,
TCP_IPV6_HASH_TYPE,
VLAN_PRI_HASH_TYPE,
E1HOV_PRI_HASH_TYPE,
DSCP_HASH_TYPE,
MAX_ETH_RSS_HASH_TYPE};
enum eth_rss_mode
{
ETH_RSS_MODE_DISABLED,
ETH_RSS_MODE_REGULAR ,
ETH_RSS_MODE_ESX51 ,
ETH_RSS_MODE_VLAN_PRI ,
ETH_RSS_MODE_E1HOV_PRI ,
ETH_RSS_MODE_IP_DSCP ,
MAX_ETH_RSS_MODE};
struct eth_rss_update_ramrod_data
{
uint8_t rss_engine_id;
uint8_t rss_mode ;
uint16_t capabilities;
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7)
#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7
#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1<<8)
#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8
#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<9)
#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9
#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F<<10)
#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10
uint8_t rss_result_mask ;
uint8_t reserved3;
uint16_t reserved4;
uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] ;
uint32_t rss_key[T_ETH_RSS_KEY] ;
uint32_t echo;
uint32_t reserved5;
};
struct eth_rx_bd
{
uint32_t addr_lo ;
uint32_t addr_hi ;
};
struct eth_rx_bd_next_page
{
uint32_t addr_lo ;
uint32_t addr_hi ;
uint8_t reserved[8];
};
struct common_ramrod_eth_rx_cqe
{
uint8_t ramrod_type;
#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
uint8_t conn_type ;
uint16_t reserved1 ;
uint32_t conn_and_cmd_data;
#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
struct ramrod_data protocol_data ;
uint32_t echo;
uint32_t reserved2[11];
};
struct eth_rx_cqe_next_page
{
uint32_t addr_lo ;
uint32_t addr_hi ;
uint32_t reserved[14];
};
union eth_rx_cqe
{
struct eth_fast_path_rx_cqe fast_path_cqe;
struct common_ramrod_eth_rx_cqe ramrod_cqe;
struct eth_rx_cqe_next_page next_page_cqe;
struct eth_end_agg_rx_cqe end_agg_cqe;
};
enum eth_rx_cqe_type
{
RX_ETH_CQE_TYPE_ETH_FASTPATH ,
RX_ETH_CQE_TYPE_ETH_RAMROD ,
RX_ETH_CQE_TYPE_ETH_START_AGG ,
RX_ETH_CQE_TYPE_ETH_STOP_AGG ,
MAX_ETH_RX_CQE_TYPE};
enum eth_rx_fp_sel
{
ETH_FP_CQE_REGULAR ,
ETH_FP_CQE_RAW ,
MAX_ETH_RX_FP_SEL};
struct eth_rx_sge
{
uint32_t addr_lo ;
uint32_t addr_hi ;
};
struct spe_hdr_t
{
uint32_t conn_and_cmd_data;
#define SPE_HDR_T_CID (0xFFFFFF<<0)
#define SPE_HDR_T_CID_SHIFT 0
#define SPE_HDR_T_CMD_ID (0xFFUL<<24)
#define SPE_HDR_T_CMD_ID_SHIFT 24
uint16_t type;
#define SPE_HDR_T_CONN_TYPE (0xFF<<0)
#define SPE_HDR_T_CONN_TYPE_SHIFT 0
#define SPE_HDR_T_FUNCTION_ID (0xFF<<8)
#define SPE_HDR_T_FUNCTION_ID_SHIFT 8
uint16_t reserved1;
};
union eth_specific_data
{
uint8_t protocol_data[8] ;
struct regpair_t client_update_ramrod_data ;
struct regpair_t client_init_ramrod_init_data ;
struct eth_halt_ramrod_data halt_ramrod_data ;
struct regpair_t update_data_addr ;
struct eth_common_ramrod_data common_ramrod_data ;
struct regpair_t classify_cfg_addr ;
struct regpair_t filter_cfg_addr ;
struct regpair_t mcast_cfg_addr ;
};
struct eth_spe
{
struct spe_hdr_t hdr ;
union eth_specific_data data ;
};
enum eth_spqe_cmd_id
{
RAMROD_CMD_ID_ETH_UNUSED,
RAMROD_CMD_ID_ETH_CLIENT_SETUP ,
RAMROD_CMD_ID_ETH_HALT ,
RAMROD_CMD_ID_ETH_FORWARD_SETUP ,
RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP ,
RAMROD_CMD_ID_ETH_CLIENT_UPDATE ,
RAMROD_CMD_ID_ETH_EMPTY ,
RAMROD_CMD_ID_ETH_TERMINATE ,
RAMROD_CMD_ID_ETH_TPA_UPDATE ,
RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES ,
RAMROD_CMD_ID_ETH_FILTER_RULES ,
RAMROD_CMD_ID_ETH_MULTICAST_RULES ,
RAMROD_CMD_ID_ETH_RSS_UPDATE ,
RAMROD_CMD_ID_ETH_SET_MAC ,
MAX_ETH_SPQE_CMD_ID};
enum eth_tpa_update_command
{
TPA_UPDATE_NONE_COMMAND ,
TPA_UPDATE_ENABLE_COMMAND ,
TPA_UPDATE_DISABLE_COMMAND ,
MAX_ETH_TPA_UPDATE_COMMAND};
enum eth_tunnel_lso_inc_ip_id
{
EXT_HEADER ,
INT_HEADER ,
MAX_ETH_TUNNEL_LSO_INC_IP_ID};
enum eth_tunnel_non_lso_csum_location
{
CSUM_ON_PKT ,
CSUM_ON_BD ,
MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION};
enum eth_tunn_type
{
TUNN_TYPE_NONE,
TUNN_TYPE_VXLAN,
TUNN_TYPE_L2_GRE ,
TUNN_TYPE_IPV4_GRE ,
TUNN_TYPE_IPV6_GRE ,
TUNN_TYPE_L2_GENEVE ,
TUNN_TYPE_IPV4_GENEVE ,
TUNN_TYPE_IPV6_GENEVE ,
MAX_ETH_TUNN_TYPE};
struct eth_tx_bd
{
uint32_t addr_lo ;
uint32_t addr_hi ;
uint16_t total_pkt_bytes ;
uint16_t nbytes ;
uint8_t reserved[4] ;
};
struct eth_tx_bd_flags
{
uint8_t as_bitfield;
#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
};
struct eth_tx_start_bd
{
uint32_t addr_lo ;
uint32_t addr_hi ;
uint16_t nbd ;
uint16_t nbytes ;
uint16_t vlan_or_ethertype ;
struct eth_tx_bd_flags bd_flags;
uint8_t general_data;
#define ETH_TX_START_BD_HDR_NBDS (0x7<<0)
#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
#define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3)
#define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3
#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7)
#define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7
};
struct eth_tx_parse_bd_e1x
{
uint16_t global_data;
#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
uint8_t tcp_flags;
#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
uint8_t ip_hlen_w ;
uint16_t total_hlen_w ;
uint16_t tcp_pseudo_csum ;
uint16_t lso_mss ;
uint16_t ip_id ;
uint32_t tcp_send_seq ;
};
struct eth_tx_parse_bd_e2
{
union eth_mac_addr_or_tunnel_data data ;
uint32_t parsing_data;
#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0)
#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
};
struct eth_tx_parse_2nd_bd
{
uint16_t global_data;
#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0)
#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4)
#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4
#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5)
#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6)
#define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6
#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7)
#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8)
#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13)
#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13
uint8_t bd_type;
#define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0)
#define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0
#define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4)
#define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4
uint8_t reserved3;
uint8_t tcp_flags;
#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0)
#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1)
#define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1
#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2)
#define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2
#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3)
#define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3
#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4)
#define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4
#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5)
#define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5
#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6)
#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7)
#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
uint8_t reserved4;
uint8_t tunnel_udp_hdr_start_w ;
uint8_t fw_ip_hdr_to_payload_w ;
uint16_t fw_ip_csum_wo_len_flags_frag ;
uint16_t hw_ip_id ;
uint32_t tcp_send_seq ;
};
struct eth_tx_next_bd
{
uint32_t addr_lo ;
uint32_t addr_hi ;
uint8_t reserved[8] ;
};
union eth_tx_bd_types
{
struct eth_tx_start_bd start_bd ;
struct eth_tx_bd reg_bd ;
struct eth_tx_parse_bd_e1x parse_bd_e1x ;
struct eth_tx_parse_bd_e2 parse_bd_e2 ;
struct eth_tx_parse_2nd_bd parse_2nd_bd ;
struct eth_tx_next_bd next_bd ;
};
struct eth_tx_bds_array
{
union eth_tx_bd_types bds[13];
};
enum eth_tx_vlan_type
{
X_ETH_NO_VLAN,
X_ETH_OUTBAND_VLAN,
X_ETH_INBAND_VLAN,
X_ETH_FW_ADDED_VLAN ,
MAX_ETH_TX_VLAN_TYPE};
enum eth_vlan_filter_mode
{
ETH_VLAN_FILTER_ANY_VLAN ,
ETH_VLAN_FILTER_SPECIFIC_VLAN ,
ETH_VLAN_FILTER_CLASSIFY ,
MAX_ETH_VLAN_FILTER_MODE};
struct mac_configuration_hdr
{
uint8_t length ;
uint8_t offset ;
uint16_t client_id ;
uint32_t echo ;
};
struct mac_configuration_entry
{
uint16_t lsb_mac_addr ;
uint16_t middle_mac_addr ;
uint16_t msb_mac_addr ;
uint16_t vlan_id ;
uint8_t pf_id ;
uint8_t flags;
#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
uint16_t reserved0;
uint32_t clients_bit_vector ;
};
struct mac_configuration_cmd
{
struct mac_configuration_hdr hdr ;
struct mac_configuration_entry config_table[64] ;
};
enum set_mac_action_type
{
T_ETH_MAC_COMMAND_INVALIDATE,
T_ETH_MAC_COMMAND_SET,
MAX_SET_MAC_ACTION_TYPE};
enum tpa_mode
{
TPA_LRO ,
TPA_GRO ,
MAX_TPA_MODE};
struct tpa_update_ramrod_data
{
uint8_t update_ipv4 ;
uint8_t update_ipv6 ;
uint8_t client_id ;
uint8_t max_tpa_queues ;
uint8_t max_sges_for_packet ;
uint8_t complete_on_both_clients ;
uint8_t dont_verify_rings_pause_thr_flg ;
uint8_t tpa_mode ;
uint16_t sge_buff_size ;
uint16_t max_agg_size ;
uint32_t sge_page_base_lo ;
uint32_t sge_page_base_hi ;
uint16_t sge_pause_thr_low ;
uint16_t sge_pause_thr_high ;
};
struct tstorm_eth_approximate_match_multicast_filtering
{
uint32_t mcast_add_hash_bit_array[8] ;
};
struct tstorm_eth_function_common_config
{
uint16_t config_flags;
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
uint8_t rss_result_mask ;
uint8_t reserved1;
uint16_t vlan_id[2] ;
};
struct tstorm_eth_mac_filter_config
{
uint32_t ucast_drop_all ;
uint32_t ucast_accept_all ;
uint32_t mcast_drop_all ;
uint32_t mcast_accept_all ;
uint32_t bcast_accept_all ;
uint32_t vlan_filter[2] ;
uint32_t unmatched_unicast ;
};
struct tx_queue_init_ramrod_data
{
struct client_init_general_data general ;
struct client_init_tx_data tx ;
};
struct ustorm_eth_rx_producers
{
#if defined(__BIG_ENDIAN)
uint16_t bd_prod ;
uint16_t cqe_prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t cqe_prod ;
uint16_t bd_prod ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t reserved;
uint16_t sge_prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t sge_prod ;
uint16_t reserved;
#endif
};
struct fcoe_abts_info
{
uint16_t aborted_task_id ;
uint16_t reserved0;
uint32_t reserved1;
};
struct fcoe_abts_rsp_union
{
uint8_t r_ctl ;
uint8_t rsrv[3];
uint32_t abts_rsp_payload[7] ;
};
struct fcoe_bd_ctx
{
uint32_t buf_addr_hi ;
uint32_t buf_addr_lo ;
uint16_t buf_len ;
uint16_t rsrv0;
uint16_t flags ;
uint16_t rsrv1;
};
struct fcoe_cached_sge_ctx
{
struct regpair_t cur_buf_addr ;
uint16_t cur_buf_rem ;
uint16_t second_buf_rem ;
struct regpair_t second_buf_addr ;
};
struct fcoe_cleanup_info
{
uint16_t cleaned_task_id ;
uint16_t rolled_tx_seq_cnt ;
uint32_t rolled_tx_data_offset ;
};
struct fcoe_fcp_rsp_flags
{
uint8_t flags;
#define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
#define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0
#define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1)
#define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1
#define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2)
#define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2
#define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3)
#define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3
#define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4)
#define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4
#define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5)
#define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
};
struct fcoe_fcp_rsp_payload
{
struct regpair_t reserved0;
uint32_t fcp_resid;
uint8_t scsi_status_code;
struct fcoe_fcp_rsp_flags fcp_flags;
uint16_t retry_delay_timer;
uint32_t fcp_rsp_len;
uint32_t fcp_sns_len;
};
struct fcoe_fcp_rsp_union
{
struct fcoe_fcp_rsp_payload payload;
struct regpair_t reserved0;
};
struct fcoe_fc_hdr
{
uint8_t s_id[3];
uint8_t cs_ctl;
uint8_t d_id[3];
uint8_t r_ctl;
uint16_t seq_cnt;
uint8_t df_ctl;
uint8_t seq_id;
uint8_t f_ctl[3];
uint8_t type;
uint32_t parameters;
uint16_t rx_id;
uint16_t ox_id;
};
struct fcoe_mp_rsp_union
{
struct fcoe_fc_hdr fc_hdr ;
uint32_t mp_payload_len ;
uint32_t rsrv;
};
union fcoe_comp_flow_info
{
struct fcoe_fcp_rsp_union fcp_rsp ;
struct fcoe_abts_rsp_union abts_rsp ;
struct fcoe_mp_rsp_union mp_rsp ;
uint32_t opaque[8];
};
struct fcoe_ext_abts_info
{
uint32_t rsrv0[6];
struct fcoe_abts_info ctx ;
};
struct fcoe_ext_cleanup_info
{
uint32_t rsrv0[6];
struct fcoe_cleanup_info ctx ;
};
struct fcoe_fw_tx_seq_ctx
{
uint32_t data_offset ;
uint16_t seq_cnt ;
uint16_t rsrv0;
};
struct fcoe_ext_fw_tx_seq_ctx
{
uint32_t rsrv0[6];
struct fcoe_fw_tx_seq_ctx ctx ;
};
struct fcoe_mul_sges_ctx
{
struct regpair_t cur_sge_addr ;
uint16_t cur_sge_off ;
uint8_t cur_sge_idx ;
uint8_t sgl_size ;
};
struct fcoe_ext_mul_sges_ctx
{
struct fcoe_mul_sges_ctx mul_sgl ;
struct regpair_t rsrv0;
};
struct fcoe_fcp_cmd_payload
{
uint32_t opaque[8];
};
struct fcoe_fcp_xfr_rdy_payload
{
uint32_t burst_len;
uint32_t data_ro;
};
struct fcoe_fc_frame
{
struct fcoe_fc_hdr fc_hdr;
uint32_t reserved0[2];
};
union fcoe_kcqe_params
{
uint32_t reserved0[4];
};
struct fcoe_kcqe
{
uint32_t fcoe_conn_id ;
uint32_t completion_status ;
uint32_t fcoe_conn_context_id ;
union fcoe_kcqe_params params ;
uint16_t qe_self_seq ;
uint8_t op_code ;
uint8_t flags;
#define FCOE_KCQE_RESERVED0 (0x7<<0)
#define FCOE_KCQE_RESERVED0_SHIFT 0
#define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
#define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
#define FCOE_KCQE_LAYER_CODE (0x7<<4)
#define FCOE_KCQE_LAYER_CODE_SHIFT 4
#define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
#define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
};
struct fcoe_kwqe_header
{
uint8_t op_code ;
uint8_t flags;
#define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
#define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
#define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
#define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
#define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
#define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
};
struct fcoe_kwqe_init1
{
uint16_t num_tasks ;
struct fcoe_kwqe_header hdr ;
uint32_t task_list_pbl_addr_lo ;
uint32_t task_list_pbl_addr_hi ;
uint32_t dummy_buffer_addr_lo ;
uint32_t dummy_buffer_addr_hi ;
uint16_t sq_num_wqes ;
uint16_t rq_num_wqes ;
uint16_t rq_buffer_log_size ;
uint16_t cq_num_wqes ;
uint16_t mtu ;
uint8_t num_sessions_log ;
uint8_t flags;
#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
#define FCOE_KWQE_INIT1_CLASSIFY_FAILED_ALLOWED (0x1<<7)
#define FCOE_KWQE_INIT1_CLASSIFY_FAILED_ALLOWED_SHIFT 7
};
struct fcoe_kwqe_init2
{
uint8_t hsi_major_version ;
uint8_t hsi_minor_version ;
struct fcoe_kwqe_header hdr ;
uint32_t hash_tbl_pbl_addr_lo ;
uint32_t hash_tbl_pbl_addr_hi ;
uint32_t t2_hash_tbl_addr_lo ;
uint32_t t2_hash_tbl_addr_hi ;
uint32_t t2_ptr_hash_tbl_addr_lo ;
uint32_t t2_ptr_hash_tbl_addr_hi ;
uint32_t free_list_count ;
};
struct fcoe_kwqe_init3
{
uint16_t reserved0;
struct fcoe_kwqe_header hdr ;
uint32_t error_bit_map_lo ;
uint32_t error_bit_map_hi ;
uint8_t perf_config ;
uint8_t reserved21[3];
uint32_t reserved2[4];
};
struct fcoe_kwqe_conn_offload1
{
uint16_t fcoe_conn_id ;
struct fcoe_kwqe_header hdr ;
uint32_t sq_addr_lo ;
uint32_t sq_addr_hi ;
uint32_t rq_pbl_addr_lo ;
uint32_t rq_pbl_addr_hi ;
uint32_t rq_first_pbe_addr_lo ;
uint32_t rq_first_pbe_addr_hi ;
uint16_t rq_prod ;
uint16_t reserved0;
};
struct fcoe_kwqe_conn_offload2
{
uint16_t tx_max_fc_pay_len ;
struct fcoe_kwqe_header hdr ;
uint32_t cq_addr_lo ;
uint32_t cq_addr_hi ;
uint32_t xferq_addr_lo ;
uint32_t xferq_addr_hi ;
uint32_t conn_db_addr_lo ;
uint32_t conn_db_addr_hi ;
uint32_t reserved1;
};
struct fcoe_kwqe_conn_offload3
{
uint16_t vlan_tag;
#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
#define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
#define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
struct fcoe_kwqe_header hdr ;
uint8_t s_id[3] ;
uint8_t tx_max_conc_seqs_c3 ;
uint8_t d_id[3] ;
uint8_t flags;
#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
uint32_t reserved;
uint32_t confq_first_pbe_addr_lo ;
uint32_t confq_first_pbe_addr_hi ;
uint16_t tx_total_conc_seqs ;
uint16_t rx_max_fc_pay_len ;
uint16_t rx_total_conc_seqs ;
uint8_t rx_max_conc_seqs_c3 ;
uint8_t rx_open_seqs_exch_c3 ;
};
struct fcoe_kwqe_conn_offload4
{
uint8_t e_d_tov_timer_val ;
uint8_t reserved2;
struct fcoe_kwqe_header hdr ;
uint8_t src_mac_addr_lo[2] ;
uint8_t src_mac_addr_mid[2] ;
uint8_t src_mac_addr_hi[2] ;
uint8_t dst_mac_addr_hi[2] ;
uint8_t dst_mac_addr_lo[2] ;
uint8_t dst_mac_addr_mid[2] ;
uint32_t lcq_addr_lo ;
uint32_t lcq_addr_hi ;
uint32_t confq_pbl_base_addr_lo ;
uint32_t confq_pbl_base_addr_hi ;
};
struct fcoe_kwqe_conn_enable_disable
{
uint16_t reserved0;
struct fcoe_kwqe_header hdr ;
uint8_t src_mac_addr_lo[2] ;
uint8_t src_mac_addr_mid[2] ;
uint8_t src_mac_addr_hi[2] ;
uint16_t vlan_tag;
#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
uint8_t dst_mac_addr_lo[2] ;
uint8_t dst_mac_addr_mid[2] ;
uint8_t dst_mac_addr_hi[2] ;
uint16_t reserved1;
uint8_t s_id[3] ;
uint8_t vlan_flag ;
uint8_t d_id[3] ;
uint8_t reserved3;
uint32_t context_id ;
uint32_t conn_id ;
uint32_t reserved4;
};
struct fcoe_kwqe_conn_destroy
{
uint16_t reserved0;
struct fcoe_kwqe_header hdr ;
uint32_t context_id ;
uint32_t conn_id ;
uint32_t reserved1[5];
};
struct fcoe_kwqe_destroy
{
uint16_t reserved0;
struct fcoe_kwqe_header hdr ;
uint32_t reserved1[7];
};
struct fcoe_kwqe_stat
{
uint16_t reserved0;
struct fcoe_kwqe_header hdr ;
uint32_t stat_params_addr_lo ;
uint32_t stat_params_addr_hi ;
uint32_t reserved1[5];
};
union fcoe_kwqe
{
struct fcoe_kwqe_init1 init1;
struct fcoe_kwqe_init2 init2;
struct fcoe_kwqe_init3 init3;
struct fcoe_kwqe_conn_offload1 conn_offload1;
struct fcoe_kwqe_conn_offload2 conn_offload2;
struct fcoe_kwqe_conn_offload3 conn_offload3;
struct fcoe_kwqe_conn_offload4 conn_offload4;
struct fcoe_kwqe_conn_enable_disable conn_enable_disable;
struct fcoe_kwqe_conn_destroy conn_destroy;
struct fcoe_kwqe_destroy destroy;
struct fcoe_kwqe_stat statistics;
};
union fcoe_sgl_union_ctx
{
struct fcoe_cached_sge_ctx cached_sge ;
struct fcoe_ext_mul_sges_ctx sgl ;
uint32_t opaque[5];
};
struct fcoe_read_flow_info
{
union fcoe_sgl_union_ctx sgl_ctx ;
uint32_t rsrv0[3];
};
struct fcoe_s_stat_ctx
{
uint8_t flags;
#define FCOE_S_STAT_CTX_ACTIVE (0x1<<0)
#define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0
#define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1)
#define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1
#define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2)
#define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2
#define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3)
#define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3
#define FCOE_S_STAT_CTX_P_RJT (0x1<<4)
#define FCOE_S_STAT_CTX_P_RJT_SHIFT 4
#define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5)
#define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5
#define FCOE_S_STAT_CTX_RSRV1 (0x3<<6)
#define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
};
struct fcoe_rx_seq_ctx
{
uint8_t seq_id ;
struct fcoe_s_stat_ctx s_stat ;
uint16_t seq_cnt ;
uint32_t low_exp_ro ;
uint32_t high_exp_ro ;
};
struct fcoe_rx_stat_params_section0
{
uint32_t fcoe_rx_pkt_cnt ;
uint32_t fcoe_rx_byte_cnt ;
};
struct fcoe_rx_stat_params_section1
{
uint32_t fcoe_ver_cnt ;
uint32_t fcoe_rx_drop_pkt_cnt ;
};
struct fcoe_rx_stat_params_section2
{
uint32_t fc_crc_cnt ;
uint32_t eofa_del_cnt ;
uint32_t miss_frame_cnt ;
uint32_t seq_timeout_cnt ;
uint32_t drop_seq_cnt ;
uint32_t fcoe_rx_drop_pkt_cnt ;
uint32_t fcp_rx_pkt_cnt ;
uint32_t reserved0;
};
union fcoe_rx_wr_union_ctx
{
struct fcoe_read_flow_info read_info ;
union fcoe_comp_flow_info comp_info ;
uint32_t opaque[8];
};
struct fcoe_sqe
{
uint16_t wqe;
#define FCOE_SQE_TASK_ID (0x7FFF<<0)
#define FCOE_SQE_TASK_ID_SHIFT 0
#define FCOE_SQE_TOGGLE_BIT (0x1<<15)
#define FCOE_SQE_TOGGLE_BIT_SHIFT 15
};
struct fcoe_tx_stat_params
{
uint32_t fcoe_tx_pkt_cnt ;
uint32_t fcoe_tx_byte_cnt ;
uint32_t fcp_tx_pkt_cnt ;
uint32_t reserved0;
};
struct fcoe_statistics_params
{
struct fcoe_tx_stat_params tx_stat ;
struct fcoe_rx_stat_params_section0 rx_stat0 ;
struct fcoe_rx_stat_params_section1 rx_stat1 ;
struct fcoe_rx_stat_params_section2 rx_stat2 ;
};
struct fcoe_tce_tx_only
{
union fcoe_sgl_union_ctx sgl_ctx ;
uint32_t rsrv0;
};
union fcoe_tx_wr_rx_rd_union_ctx
{
struct fcoe_fc_frame tx_frame ;
struct fcoe_fcp_cmd_payload fcp_cmd ;
struct fcoe_ext_cleanup_info cleanup ;
struct fcoe_ext_abts_info abts ;
struct fcoe_ext_fw_tx_seq_ctx tx_seq ;
uint32_t opaque[8];
};
struct fcoe_tce_tx_wr_rx_rd_const
{
uint8_t init_flags;
#define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0)
#define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0
#define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3)
#define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3
#define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4)
#define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4
#define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5)
#define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5
#define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7)
#define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7
uint8_t tx_flags;
#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0)
#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0
#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1)
#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1
#define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5)
#define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5
#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6)
#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6
#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS (0x1<<7)
#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS_SHIFT 7
uint16_t rsrv3;
uint32_t verify_tx_seq ;
};
struct fcoe_tce_tx_wr_rx_rd
{
union fcoe_tx_wr_rx_rd_union_ctx union_ctx ;
struct fcoe_tce_tx_wr_rx_rd_const const_ctx ;
};
struct fcoe_tce_rx_wr_tx_rd_const
{
uint32_t data_2_trns ;
uint32_t init_flags;
#define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0)
#define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0
#define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24)
#define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24
};
struct fcoe_tce_rx_wr_tx_rd_var
{
uint16_t rx_flags;
#define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0)
#define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0
#define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4)
#define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4
#define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7)
#define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7
#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8)
#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8
#define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12)
#define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12
#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13)
#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13
#define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14)
#define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14
#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15)
#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15
uint16_t rx_id ;
struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy ;
};
struct fcoe_tce_rx_wr_tx_rd
{
struct fcoe_tce_rx_wr_tx_rd_const const_ctx ;
struct fcoe_tce_rx_wr_tx_rd_var var_ctx ;
};
struct fcoe_tce_rx_only
{
struct fcoe_rx_seq_ctx rx_seq_ctx ;
union fcoe_rx_wr_union_ctx union_ctx ;
};
struct fcoe_task_ctx_entry
{
struct fcoe_tce_tx_only txwr_only ;
struct fcoe_tce_tx_wr_rx_rd txwr_rxrd ;
struct fcoe_tce_rx_wr_tx_rd rxwr_txrd ;
struct fcoe_tce_rx_only rxwr_only ;
};
struct fcoe_xfrqe
{
uint16_t wqe;
#define FCOE_XFRQE_TASK_ID (0x7FFF<<0)
#define FCOE_XFRQE_TASK_ID_SHIFT 0
#define FCOE_XFRQE_TOGGLE_BIT (0x1<<15)
#define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15
};
struct common_fcoe_sgl
{
struct fcoe_bd_ctx sge[3];
};
struct fcoe_cached_wqe
{
struct fcoe_sqe sqe ;
struct fcoe_xfrqe xfrqe ;
};
struct fcoe_conn_enable_disable_ramrod_params
{
struct fcoe_kwqe_conn_enable_disable enable_disable_kwqe;
};
struct fcoe_conn_offload_ramrod_params
{
struct fcoe_kwqe_conn_offload1 offload_kwqe1;
struct fcoe_kwqe_conn_offload2 offload_kwqe2;
struct fcoe_kwqe_conn_offload3 offload_kwqe3;
struct fcoe_kwqe_conn_offload4 offload_kwqe4;
};
struct ustorm_fcoe_mng_ctx
{
#if defined(__BIG_ENDIAN)
uint8_t mid_seq_proc_flag ;
uint8_t tce_in_cam_flag ;
uint8_t tce_on_ior_flag ;
uint8_t en_cached_tce_flag ;
#elif defined(__LITTLE_ENDIAN)
uint8_t en_cached_tce_flag ;
uint8_t tce_on_ior_flag ;
uint8_t tce_in_cam_flag ;
uint8_t mid_seq_proc_flag ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t tce_cam_addr ;
uint8_t cached_conn_flag ;
uint16_t rsrv0;
#elif defined(__LITTLE_ENDIAN)
uint16_t rsrv0;
uint8_t cached_conn_flag ;
uint8_t tce_cam_addr ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t dma_tce_ram_addr ;
uint16_t tce_ram_addr ;
#elif defined(__LITTLE_ENDIAN)
uint16_t tce_ram_addr ;
uint16_t dma_tce_ram_addr ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t ox_id ;
uint16_t wr_done_seq ;
#elif defined(__LITTLE_ENDIAN)
uint16_t wr_done_seq ;
uint16_t ox_id ;
#endif
struct regpair_t task_addr ;
};
struct ustorm_fcoe_params
{
#if defined(__BIG_ENDIAN)
uint16_t fcoe_conn_id ;
uint16_t flags;
#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
#define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
#define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
#define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
#define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
#define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT (0x1<<7)
#define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT_SHIFT 7
#define USTORM_FCOE_PARAMS_RSRV0 (0xFF<<8)
#define USTORM_FCOE_PARAMS_RSRV0_SHIFT 8
#elif defined(__LITTLE_ENDIAN)
uint16_t flags;
#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
#define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
#define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
#define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
#define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
#define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT (0x1<<7)
#define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT_SHIFT 7
#define USTORM_FCOE_PARAMS_RSRV0 (0xFF<<8)
#define USTORM_FCOE_PARAMS_RSRV0_SHIFT 8
uint16_t fcoe_conn_id ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t hc_csdm_byte_en ;
uint8_t func_id ;
uint8_t port_id ;
uint8_t vnic_id ;
#elif defined(__LITTLE_ENDIAN)
uint8_t vnic_id ;
uint8_t port_id ;
uint8_t func_id ;
uint8_t hc_csdm_byte_en ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t rx_total_conc_seqs ;
uint16_t rx_max_fc_pay_len ;
#elif defined(__LITTLE_ENDIAN)
uint16_t rx_max_fc_pay_len ;
uint16_t rx_total_conc_seqs ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t task_pbe_idx_off ;
uint8_t task_in_page_log_size ;
uint16_t rx_max_conc_seqs ;
#elif defined(__LITTLE_ENDIAN)
uint16_t rx_max_conc_seqs ;
uint8_t task_in_page_log_size ;
uint8_t task_pbe_idx_off ;
#endif
};
struct fcoe_idx16_fields
{
uint16_t fields;
#define FCOE_IDX16_FIELDS_IDX (0x7FFF<<0)
#define FCOE_IDX16_FIELDS_IDX_SHIFT 0
#define FCOE_IDX16_FIELDS_MSB (0x1<<15)
#define FCOE_IDX16_FIELDS_MSB_SHIFT 15
};
union fcoe_idx16_field_union
{
struct fcoe_idx16_fields fields ;
uint16_t val ;
};
struct ustorm_fcoe_data_place_mng
{
#if defined(__BIG_ENDIAN)
uint16_t sge_off;
uint8_t num_sges ;
uint8_t sge_idx ;
#elif defined(__LITTLE_ENDIAN)
uint8_t sge_idx ;
uint8_t num_sges ;
uint16_t sge_off;
#endif
};
struct ustorm_fcoe_data_place
{
struct ustorm_fcoe_data_place_mng cached_mng ;
struct fcoe_bd_ctx cached_sge[2];
};
union fcoe_u_tce_tx_wr_rx_rd_union
{
struct fcoe_abts_info abts ;
struct fcoe_cleanup_info cleanup ;
struct fcoe_fw_tx_seq_ctx tx_seq_ctx ;
uint32_t opaque[2];
};
struct fcoe_u_tce_tx_wr_rx_rd
{
union fcoe_u_tce_tx_wr_rx_rd_union union_ctx ;
struct fcoe_tce_tx_wr_rx_rd_const const_ctx ;
};
struct ustorm_fcoe_tce
{
struct fcoe_u_tce_tx_wr_rx_rd txwr_rxrd ;
struct fcoe_tce_rx_wr_tx_rd rxwr_txrd ;
struct fcoe_tce_rx_only rxwr ;
};
struct ustorm_fcoe_cache_ctx
{
uint32_t rsrv0;
struct ustorm_fcoe_data_place data_place;
struct ustorm_fcoe_tce tce ;
};
struct ustorm_fcoe_st_context
{
struct ustorm_fcoe_mng_ctx mng_ctx ;
struct ustorm_fcoe_params fcoe_params ;
struct regpair_t cq_base_addr ;
struct regpair_t rq_pbl_base ;
struct regpair_t rq_cur_page_addr ;
struct regpair_t confq_pbl_base_addr ;
struct regpair_t conn_db_base ;
struct regpair_t xfrq_base_addr ;
struct regpair_t lcq_base_addr ;
#if defined(__BIG_ENDIAN)
union fcoe_idx16_field_union rq_cons ;
union fcoe_idx16_field_union rq_prod ;
#elif defined(__LITTLE_ENDIAN)
union fcoe_idx16_field_union rq_prod ;
union fcoe_idx16_field_union rq_cons ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t xfrq_prod ;
uint16_t cq_cons ;
#elif defined(__LITTLE_ENDIAN)
uint16_t cq_cons ;
uint16_t xfrq_prod ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t lcq_cons ;
uint16_t hc_cram_address ;
#elif defined(__LITTLE_ENDIAN)
uint16_t hc_cram_address ;
uint16_t lcq_cons ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t sq_xfrq_lcq_confq_size ;
uint16_t confq_prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t confq_prod ;
uint16_t sq_xfrq_lcq_confq_size ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t hc_csdm_agg_int ;
uint8_t rsrv2;
uint8_t available_rqes ;
uint8_t sp_q_flush_cnt ;
#elif defined(__LITTLE_ENDIAN)
uint8_t sp_q_flush_cnt ;
uint8_t available_rqes ;
uint8_t rsrv2;
uint8_t hc_csdm_agg_int ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t num_pend_tasks ;
uint16_t pbf_ack_ram_addr ;
#elif defined(__LITTLE_ENDIAN)
uint16_t pbf_ack_ram_addr ;
uint16_t num_pend_tasks ;
#endif
struct ustorm_fcoe_cache_ctx cache_ctx ;
};
struct tstorm_fcoe_st_context
{
struct regpair_t reserved0;
struct regpair_t reserved1;
};
struct xstorm_fcoe_eth_context_section
{
#if defined(__BIG_ENDIAN)
uint8_t remote_addr_4 ;
uint8_t remote_addr_5 ;
uint8_t local_addr_0 ;
uint8_t local_addr_1 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t local_addr_1 ;
uint8_t local_addr_0 ;
uint8_t remote_addr_5 ;
uint8_t remote_addr_4 ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t remote_addr_0 ;
uint8_t remote_addr_1 ;
uint8_t remote_addr_2 ;
uint8_t remote_addr_3 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t remote_addr_3 ;
uint8_t remote_addr_2 ;
uint8_t remote_addr_1 ;
uint8_t remote_addr_0 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t reserved_vlan_type ;
uint16_t params;
#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
#elif defined(__LITTLE_ENDIAN)
uint16_t params;
#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
uint16_t reserved_vlan_type ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t local_addr_2 ;
uint8_t local_addr_3 ;
uint8_t local_addr_4 ;
uint8_t local_addr_5 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t local_addr_5 ;
uint8_t local_addr_4 ;
uint8_t local_addr_3 ;
uint8_t local_addr_2 ;
#endif
};
struct xstorm_fcoe_context_flags
{
uint8_t flags;
#define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0)
#define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0
#define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2)
#define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ_SHIFT 2
#define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ (0x1<<3)
#define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ_SHIFT 3
#define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4)
#define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT_SHIFT 4
#define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5)
#define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE_SHIFT 5
#define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6)
#define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE_SHIFT 6
#define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN (0x1<<7)
#define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN_SHIFT 7
};
struct xstorm_fcoe_tce
{
struct fcoe_tce_tx_only txwr ;
struct fcoe_tce_tx_wr_rx_rd txwr_rxrd ;
};
struct xstorm_fcoe_fcp_data
{
uint32_t io_rem ;
#if defined(__BIG_ENDIAN)
uint16_t cached_sge_off;
uint8_t cached_num_sges ;
uint8_t cached_sge_idx ;
#elif defined(__LITTLE_ENDIAN)
uint8_t cached_sge_idx ;
uint8_t cached_num_sges ;
uint16_t cached_sge_off;
#endif
uint32_t buf_addr_hi_0 ;
uint32_t buf_addr_lo_0 ;
#if defined(__BIG_ENDIAN)
uint16_t num_of_pending_tasks ;
uint16_t buf_len_0 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t buf_len_0 ;
uint16_t num_of_pending_tasks ;
#endif
uint32_t buf_addr_hi_1 ;
uint32_t buf_addr_lo_1 ;
#if defined(__BIG_ENDIAN)
uint16_t task_pbe_idx_off ;
uint16_t buf_len_1 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t buf_len_1 ;
uint16_t task_pbe_idx_off ;
#endif
uint32_t buf_addr_hi_2 ;
uint32_t buf_addr_lo_2 ;
#if defined(__BIG_ENDIAN)
uint16_t ox_id ;
uint16_t buf_len_2 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t buf_len_2 ;
uint16_t ox_id ;
#endif
};
struct xstorm_fcoe_context_flags_cont
{
uint8_t flags;
#define XSTORM_FCOE_CONTEXT_FLAGS_CONT_B_CONFQ_TOGGLE (0x1<<0)
#define XSTORM_FCOE_CONTEXT_FLAGS_CONT_B_CONFQ_TOGGLE_SHIFT 0
#define XSTORM_FCOE_CONTEXT_FLAGS_CONT_VLAN_FLAG (0x1<<1)
#define XSTORM_FCOE_CONTEXT_FLAGS_CONT_VLAN_FLAG_SHIFT 1
#define XSTORM_FCOE_CONTEXT_FLAGS_CONT_RESERVED (0x3F<<2)
#define XSTORM_FCOE_CONTEXT_FLAGS_CONT_RESERVED_SHIFT 2
};
struct xstorm_fcoe_vlan_conf
{
uint8_t vlan_conf;
#define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_PRIORITY (0x7<<0)
#define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_PRIORITY_SHIFT 0
#define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG (0x1<<3)
#define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG_SHIFT 3
#define XSTORM_FCOE_VLAN_CONF_OUTER_VLAN_PRIORITY (0x7<<4)
#define XSTORM_FCOE_VLAN_CONF_OUTER_VLAN_PRIORITY_SHIFT 4
#define XSTORM_FCOE_VLAN_CONF_RESERVED (0x1<<7)
#define XSTORM_FCOE_VLAN_CONF_RESERVED_SHIFT 7
};
struct fcoe_vlan_fields
{
uint16_t fields;
#define FCOE_VLAN_FIELDS_VID (0xFFF<<0)
#define FCOE_VLAN_FIELDS_VID_SHIFT 0
#define FCOE_VLAN_FIELDS_CLI (0x1<<12)
#define FCOE_VLAN_FIELDS_CLI_SHIFT 12
#define FCOE_VLAN_FIELDS_PRI (0x7<<13)
#define FCOE_VLAN_FIELDS_PRI_SHIFT 13
};
union fcoe_vlan_field_union
{
struct fcoe_vlan_fields fields ;
uint16_t val ;
};
union fcoe_vlan_vif_field_union
{
union fcoe_vlan_field_union vlan ;
uint16_t vif ;
};
struct xstorm_fcoe_context_section
{
#if defined(__BIG_ENDIAN)
uint8_t cs_ctl ;
uint8_t s_id[3] ;
#elif defined(__LITTLE_ENDIAN)
uint8_t s_id[3] ;
uint8_t cs_ctl ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t rctl ;
uint8_t d_id[3] ;
#elif defined(__LITTLE_ENDIAN)
uint8_t d_id[3] ;
uint8_t rctl ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t sq_xfrq_lcq_confq_size ;
uint16_t tx_max_fc_pay_len ;
#elif defined(__LITTLE_ENDIAN)
uint16_t tx_max_fc_pay_len ;
uint16_t sq_xfrq_lcq_confq_size ;
#endif
uint32_t lcq_prod ;
#if defined(__BIG_ENDIAN)
uint8_t port_id ;
uint8_t func_id ;
uint8_t seq_id ;
struct xstorm_fcoe_context_flags tx_flags;
#elif defined(__LITTLE_ENDIAN)
struct xstorm_fcoe_context_flags tx_flags;
uint8_t seq_id ;
uint8_t func_id ;
uint8_t port_id ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t mtu ;
uint8_t func_mode ;
uint8_t vnic_id ;
#elif defined(__LITTLE_ENDIAN)
uint8_t vnic_id ;
uint8_t func_mode ;
uint16_t mtu ;
#endif
struct regpair_t confq_curr_page_addr ;
struct fcoe_cached_wqe cached_wqe[8] ;
struct regpair_t lcq_base_addr ;
struct xstorm_fcoe_tce tce ;
struct xstorm_fcoe_fcp_data fcp_data ;
#if defined(__BIG_ENDIAN)
uint8_t tx_max_conc_seqs_c3 ;
struct xstorm_fcoe_context_flags_cont tx_flags_cont;
uint8_t dcb_val ;
uint8_t data_pb_cmd_size ;
#elif defined(__LITTLE_ENDIAN)
uint8_t data_pb_cmd_size ;
uint8_t dcb_val ;
struct xstorm_fcoe_context_flags_cont tx_flags_cont;
uint8_t tx_max_conc_seqs_c3 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t fcoe_tx_stat_params_ram_addr ;
uint16_t fcoe_tx_fc_seq_ram_addr ;
#elif defined(__LITTLE_ENDIAN)
uint16_t fcoe_tx_fc_seq_ram_addr ;
uint16_t fcoe_tx_stat_params_ram_addr ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t fcp_cmd_line_credit;
uint8_t eth_hdr_size ;
uint16_t pbf_addr ;
#elif defined(__LITTLE_ENDIAN)
uint16_t pbf_addr ;
uint8_t eth_hdr_size ;
uint8_t fcp_cmd_line_credit;
#endif
#if defined(__BIG_ENDIAN)
union fcoe_vlan_vif_field_union multi_func_val ;
uint8_t page_log_size ;
struct xstorm_fcoe_vlan_conf orig_vlan_conf ;
#elif defined(__LITTLE_ENDIAN)
struct xstorm_fcoe_vlan_conf orig_vlan_conf ;
uint8_t page_log_size ;
union fcoe_vlan_vif_field_union multi_func_val ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t fcp_cmd_frame_size ;
uint16_t pbf_addr_ff ;
#elif defined(__LITTLE_ENDIAN)
uint16_t pbf_addr_ff ;
uint16_t fcp_cmd_frame_size ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t vlan_num ;
uint8_t cos ;
uint8_t cache_xfrq_cons ;
uint8_t cache_sq_cons ;
#elif defined(__LITTLE_ENDIAN)
uint8_t cache_sq_cons ;
uint8_t cache_xfrq_cons ;
uint8_t cos ;
uint8_t vlan_num ;
#endif
uint32_t verify_tx_seq ;
};
struct xstorm_fcoe_st_context
{
struct xstorm_fcoe_eth_context_section eth;
struct xstorm_fcoe_context_section fcoe;
};
struct fcoe_context
{
struct ustorm_fcoe_st_context ustorm_st_context ;
struct tstorm_fcoe_st_context tstorm_st_context ;
struct xstorm_fcoe_ag_context xstorm_ag_context ;
struct tstorm_fcoe_ag_context tstorm_ag_context ;
struct ustorm_fcoe_ag_context ustorm_ag_context ;
struct timers_block_context timers_context ;
struct xstorm_fcoe_st_context xstorm_st_context ;
};
struct fcoe_init_ramrod_params
{
struct fcoe_kwqe_init1 init_kwqe1;
struct fcoe_kwqe_init2 init_kwqe2;
struct fcoe_kwqe_init3 init_kwqe3;
struct regpair_t eq_pbl_base ;
uint32_t eq_pbl_size ;
uint32_t reserved2;
uint16_t eq_prod ;
uint16_t sb_num ;
uint8_t sb_id ;
uint8_t reserved0;
uint16_t reserved1;
};
struct fcoe_stat_ramrod_params
{
struct fcoe_kwqe_stat stat_kwqe;
};
struct iscsi_cq_db_prod_pnd_cmpltn_cnt
{
#if defined(__BIG_ENDIAN)
uint16_t cntr ;
uint16_t prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t prod ;
uint16_t cntr ;
#endif
};
struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr
{
struct iscsi_cq_db_prod_pnd_cmpltn_cnt prod_pend_comp[8] ;
};
struct iscsi_cq_db_pnd_comp_itt_arr
{
uint16_t itt[8] ;
};
struct iscsi_cq_db_sqn_2_notify_arr
{
uint16_t sqn[8] ;
};
struct iscsi_cq_db
{
struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_u_prod_pend_comp_ctr_arr ;
struct iscsi_cq_db_pnd_comp_itt_arr cq_c_pend_comp_itt_arr ;
struct iscsi_cq_db_sqn_2_notify_arr cq_drv_sqn_2_notify_arr ;
uint32_t reserved[4] ;
};
union iscsi_kcqe_params
{
uint32_t reserved0[4];
};
struct iscsi_kcqe
{
uint32_t iscsi_conn_id ;
uint32_t completion_status ;
uint32_t iscsi_conn_context_id ;
union iscsi_kcqe_params params ;
#if defined(__BIG_ENDIAN)
uint8_t flags;
#define ISCSI_KCQE_RESERVED0 (0x7<<0)
#define ISCSI_KCQE_RESERVED0_SHIFT 0
#define ISCSI_KCQE_RAMROD_COMPLETION (0x1<<3)
#define ISCSI_KCQE_RAMROD_COMPLETION_SHIFT 3
#define ISCSI_KCQE_LAYER_CODE (0x7<<4)
#define ISCSI_KCQE_LAYER_CODE_SHIFT 4
#define ISCSI_KCQE_LINKED_WITH_NEXT (0x1<<7)
#define ISCSI_KCQE_LINKED_WITH_NEXT_SHIFT 7
uint8_t op_code ;
uint16_t qe_self_seq ;
#elif defined(__LITTLE_ENDIAN)
uint16_t qe_self_seq ;
uint8_t op_code ;
uint8_t flags;
#define ISCSI_KCQE_RESERVED0 (0x7<<0)
#define ISCSI_KCQE_RESERVED0_SHIFT 0
#define ISCSI_KCQE_RAMROD_COMPLETION (0x1<<3)
#define ISCSI_KCQE_RAMROD_COMPLETION_SHIFT 3
#define ISCSI_KCQE_LAYER_CODE (0x7<<4)
#define ISCSI_KCQE_LAYER_CODE_SHIFT 4
#define ISCSI_KCQE_LINKED_WITH_NEXT (0x1<<7)
#define ISCSI_KCQE_LINKED_WITH_NEXT_SHIFT 7
#endif
};
struct iscsi_kwqe_header
{
#if defined(__BIG_ENDIAN)
uint8_t flags;
#define ISCSI_KWQE_HEADER_RESERVED0 (0xF<<0)
#define ISCSI_KWQE_HEADER_RESERVED0_SHIFT 0
#define ISCSI_KWQE_HEADER_LAYER_CODE (0x7<<4)
#define ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT 4
#define ISCSI_KWQE_HEADER_RESERVED1 (0x1<<7)
#define ISCSI_KWQE_HEADER_RESERVED1_SHIFT 7
uint8_t op_code ;
#elif defined(__LITTLE_ENDIAN)
uint8_t op_code ;
uint8_t flags;
#define ISCSI_KWQE_HEADER_RESERVED0 (0xF<<0)
#define ISCSI_KWQE_HEADER_RESERVED0_SHIFT 0
#define ISCSI_KWQE_HEADER_LAYER_CODE (0x7<<4)
#define ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT 4
#define ISCSI_KWQE_HEADER_RESERVED1 (0x1<<7)
#define ISCSI_KWQE_HEADER_RESERVED1_SHIFT 7
#endif
};
struct iscsi_kwqe_init1
{
#if defined(__BIG_ENDIAN)
struct iscsi_kwqe_header hdr ;
uint8_t hsi_version ;
uint8_t num_cqs ;
#elif defined(__LITTLE_ENDIAN)
uint8_t num_cqs ;
uint8_t hsi_version ;
struct iscsi_kwqe_header hdr ;
#endif
uint32_t dummy_buffer_addr_lo ;
uint32_t dummy_buffer_addr_hi ;
#if defined(__BIG_ENDIAN)
uint16_t num_ccells_per_conn ;
uint16_t num_tasks_per_conn ;
#elif defined(__LITTLE_ENDIAN)
uint16_t num_tasks_per_conn ;
uint16_t num_ccells_per_conn ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t sq_wqes_per_page ;
uint16_t sq_num_wqes ;
#elif defined(__LITTLE_ENDIAN)
uint16_t sq_num_wqes ;
uint16_t sq_wqes_per_page ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t cq_log_wqes_per_page ;
uint8_t flags;
#define ISCSI_KWQE_INIT1_PAGE_SIZE (0xF<<0)
#define ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT 0
#define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE (0x1<<4)
#define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE_SHIFT 4
#define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE (0x1<<5)
#define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE_SHIFT 5
#define ISCSI_KWQE_INIT1_RESERVED1 (0x3<<6)
#define ISCSI_KWQE_INIT1_RESERVED1_SHIFT 6
uint16_t cq_num_wqes ;
#elif defined(__LITTLE_ENDIAN)
uint16_t cq_num_wqes ;
uint8_t flags;
#define ISCSI_KWQE_INIT1_PAGE_SIZE (0xF<<0)
#define ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT 0
#define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE (0x1<<4)
#define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE_SHIFT 4
#define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE (0x1<<5)
#define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE_SHIFT 5
#define ISCSI_KWQE_INIT1_RESERVED1 (0x3<<6)
#define ISCSI_KWQE_INIT1_RESERVED1_SHIFT 6
uint8_t cq_log_wqes_per_page ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t cq_num_pages ;
uint16_t sq_num_pages ;
#elif defined(__LITTLE_ENDIAN)
uint16_t sq_num_pages ;
uint16_t cq_num_pages ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t rq_buffer_size ;
uint16_t rq_num_wqes ;
#elif defined(__LITTLE_ENDIAN)
uint16_t rq_num_wqes ;
uint16_t rq_buffer_size ;
#endif
};
struct iscsi_kwqe_init2
{
#if defined(__BIG_ENDIAN)
struct iscsi_kwqe_header hdr ;
uint16_t max_cq_sqn ;
#elif defined(__LITTLE_ENDIAN)
uint16_t max_cq_sqn ;
struct iscsi_kwqe_header hdr ;
#endif
uint32_t error_bit_map[2] ;
uint32_t tcp_keepalive ;
uint32_t reserved1[4];
};
struct iscsi_kwqe_conn_offload1
{
#if defined(__BIG_ENDIAN)
struct iscsi_kwqe_header hdr ;
uint16_t iscsi_conn_id ;
#elif defined(__LITTLE_ENDIAN)
uint16_t iscsi_conn_id ;
struct iscsi_kwqe_header hdr ;
#endif
uint32_t sq_page_table_addr_lo ;
uint32_t sq_page_table_addr_hi ;
uint32_t cq_page_table_addr_lo ;
uint32_t cq_page_table_addr_hi ;
uint32_t reserved0[3];
};
struct iscsi_pte
{
uint32_t hi ;
uint32_t lo ;
};
struct iscsi_kwqe_conn_offload2
{
#if defined(__BIG_ENDIAN)
struct iscsi_kwqe_header hdr ;
uint16_t reserved0;
#elif defined(__LITTLE_ENDIAN)
uint16_t reserved0;
struct iscsi_kwqe_header hdr ;
#endif
uint32_t rq_page_table_addr_lo ;
uint32_t rq_page_table_addr_hi ;
struct iscsi_pte sq_first_pte ;
struct iscsi_pte cq_first_pte ;
uint32_t num_additional_wqes ;
};
struct iscsi_kwqe_conn_offload3
{
#if defined(__BIG_ENDIAN)
struct iscsi_kwqe_header hdr ;
uint16_t reserved0;
#elif defined(__LITTLE_ENDIAN)
uint16_t reserved0;
struct iscsi_kwqe_header hdr ;
#endif
uint32_t reserved1;
struct iscsi_pte qp_first_pte[3] ;
};
struct iscsi_kwqe_conn_update
{
#if defined(__BIG_ENDIAN)
struct iscsi_kwqe_header hdr ;
uint16_t reserved0;
#elif defined(__LITTLE_ENDIAN)
uint16_t reserved0;
struct iscsi_kwqe_header hdr ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t session_error_recovery_level ;
uint8_t max_outstanding_r2ts ;
uint8_t reserved2;
uint8_t conn_flags;
#define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST (0x1<<0)
#define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT 0
#define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST (0x1<<1)
#define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST_SHIFT 1
#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T (0x1<<2)
#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2
#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3)
#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3
#define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE (0x3<<4)
#define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE_SHIFT 4
#define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0x3<<6)
#define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 6
#elif defined(__LITTLE_ENDIAN)
uint8_t conn_flags;
#define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST (0x1<<0)
#define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT 0
#define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST (0x1<<1)
#define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST_SHIFT 1
#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T (0x1<<2)
#define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2
#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3)
#define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3
#define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE (0x3<<4)
#define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE_SHIFT 4
#define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0x3<<6)
#define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 6
uint8_t reserved2;
uint8_t max_outstanding_r2ts ;
uint8_t session_error_recovery_level ;
#endif
uint32_t context_id ;
uint32_t max_send_pdu_length ;
uint32_t max_recv_pdu_length ;
uint32_t first_burst_length ;
uint32_t max_burst_length ;
uint32_t exp_stat_sn ;
};
struct iscsi_kwqe_conn_destroy
{
#if defined(__BIG_ENDIAN)
struct iscsi_kwqe_header hdr ;
uint16_t iscsi_conn_id ;
#elif defined(__LITTLE_ENDIAN)
uint16_t iscsi_conn_id ;
struct iscsi_kwqe_header hdr ;
#endif
uint32_t context_id ;
uint32_t reserved1[6];
};
union iscsi_kwqe
{
struct iscsi_kwqe_init1 init1;
struct iscsi_kwqe_init2 init2;
struct iscsi_kwqe_conn_offload1 conn_offload1;
struct iscsi_kwqe_conn_offload2 conn_offload2;
struct iscsi_kwqe_conn_offload3 conn_offload3;
struct iscsi_kwqe_conn_update conn_update;
struct iscsi_kwqe_conn_destroy conn_destroy;
};
struct iscsi_rq_db
{
#if defined(__BIG_ENDIAN)
uint16_t reserved1;
uint16_t rq_prod;
#elif defined(__LITTLE_ENDIAN)
uint16_t rq_prod;
uint16_t reserved1;
#endif
uint32_t __fw_hdr[15] ;
};
struct iscsi_sq_db
{
#if defined(__BIG_ENDIAN)
uint16_t reserved0 ;
uint16_t sq_prod;
#elif defined(__LITTLE_ENDIAN)
uint16_t sq_prod;
uint16_t reserved0 ;
#endif
uint32_t reserved1[3] ;
};
struct tstorm_l5cm_tcp_flags
{
uint16_t flags;
#define TSTORM_L5CM_TCP_FLAGS_VLAN_ID (0xFFF<<0)
#define TSTORM_L5CM_TCP_FLAGS_VLAN_ID_SHIFT 0
#define TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN (0x1<<12)
#define TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN_SHIFT 12
#define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<13)
#define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 13
#define TSTORM_L5CM_TCP_FLAGS_RSRV1 (0x3<<14)
#define TSTORM_L5CM_TCP_FLAGS_RSRV1_SHIFT 14
};
struct cstorm_iscsi_st_context
{
struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_c_prod_pend_comp_ctr_arr ;
struct iscsi_cq_db_sqn_2_notify_arr cq_c_prod_sqn_arr ;
struct iscsi_cq_db_sqn_2_notify_arr cq_c_sqn_2_notify_arr ;
struct regpair_t hq_pbl_base ;
struct regpair_t hq_curr_pbe ;
struct regpair_t task_pbl_base ;
struct regpair_t cq_db_base ;
#if defined(__BIG_ENDIAN)
uint16_t hq_bd_itt ;
uint16_t iscsi_conn_id;
#elif defined(__LITTLE_ENDIAN)
uint16_t iscsi_conn_id;
uint16_t hq_bd_itt ;
#endif
uint32_t hq_bd_data_segment_len ;
uint32_t hq_bd_buffer_offset ;
#if defined(__BIG_ENDIAN)
uint8_t rsrv;
uint8_t cq_proc_en_bit_map ;
uint8_t cq_pend_comp_itt_valid_bit_map ;
uint8_t hq_bd_opcode ;
#elif defined(__LITTLE_ENDIAN)
uint8_t hq_bd_opcode ;
uint8_t cq_pend_comp_itt_valid_bit_map ;
uint8_t cq_proc_en_bit_map ;
uint8_t rsrv;
#endif
uint32_t hq_tcp_seq ;
#if defined(__BIG_ENDIAN)
uint16_t flags;
#define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0)
#define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0
#define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1)
#define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1
#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2)
#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2
#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3)
#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3
#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4)
#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4
#define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5)
#define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5
uint16_t hq_cons ;
#elif defined(__LITTLE_ENDIAN)
uint16_t hq_cons ;
uint16_t flags;
#define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0)
#define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0
#define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1)
#define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1
#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2)
#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2
#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3)
#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3
#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4)
#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4
#define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5)
#define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5
#endif
struct regpair_t rsrv1;
};
struct iscsi_cmd_pdu_hdr_little_endian
{
#if defined(__BIG_ENDIAN)
uint8_t opcode;
uint8_t op_attr;
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0)
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3)
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5)
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6)
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
uint16_t rsrv0;
#elif defined(__LITTLE_ENDIAN)
uint16_t rsrv0;
uint8_t op_attr;
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0)
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3)
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5)
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6)
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
uint8_t opcode;
#endif
uint32_t data_fields;
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
struct regpair_t lun;
uint32_t itt;
uint32_t expected_data_transfer_length;
uint32_t cmd_sn;
uint32_t exp_stat_sn;
uint32_t scsi_command_block[4];
};
struct iscsi_conn_buf
{
struct regpair_t reserved[8];
};
struct ustorm_iscsi_rq_db
{
struct regpair_t pbl_base ;
struct regpair_t curr_pbe ;
};
struct ustorm_iscsi_r2tq_db
{
struct regpair_t pbl_base ;
struct regpair_t curr_pbe ;
};
struct ustorm_iscsi_cq_db
{
#if defined(__BIG_ENDIAN)
uint16_t cq_sn ;
uint16_t prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t prod ;
uint16_t cq_sn ;
#endif
struct regpair_t curr_pbe ;
};
struct rings_db
{
struct ustorm_iscsi_rq_db rq ;
struct ustorm_iscsi_r2tq_db r2tq ;
struct ustorm_iscsi_cq_db cq[8] ;
#if defined(__BIG_ENDIAN)
uint16_t rq_prod ;
uint16_t r2tq_prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t r2tq_prod ;
uint16_t rq_prod ;
#endif
struct regpair_t cq_pbl_base ;
};
struct ustorm_iscsi_placement_db
{
uint32_t sgl_base_lo ;
uint32_t sgl_base_hi ;
uint32_t local_sge_0_address_hi ;
uint32_t local_sge_0_address_lo ;
#if defined(__BIG_ENDIAN)
uint16_t curr_sge_offset ;
uint16_t local_sge_0_size ;
#elif defined(__LITTLE_ENDIAN)
uint16_t local_sge_0_size ;
uint16_t curr_sge_offset ;
#endif
uint32_t local_sge_1_address_hi ;
uint32_t local_sge_1_address_lo ;
#if defined(__BIG_ENDIAN)
uint8_t exp_padding_2b ;
uint8_t nal_len_3b ;
uint16_t local_sge_1_size ;
#elif defined(__LITTLE_ENDIAN)
uint16_t local_sge_1_size ;
uint8_t nal_len_3b ;
uint8_t exp_padding_2b ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t sgl_size ;
uint8_t local_sge_index_2b ;
uint16_t reserved7;
#elif defined(__LITTLE_ENDIAN)
uint16_t reserved7;
uint8_t local_sge_index_2b ;
uint8_t sgl_size ;
#endif
uint32_t rem_pdu ;
uint32_t place_db_bitfield_1;
#define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD (0xFFFFFF<<0)
#define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT 0
#define USTORM_ISCSI_PLACEMENT_DB_CQ_ID (0xFF<<24)
#define USTORM_ISCSI_PLACEMENT_DB_CQ_ID_SHIFT 24
uint32_t place_db_bitfield_2;
#define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE (0xFFFFFF<<0)
#define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT 0
#define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX (0xFF<<24)
#define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX_SHIFT 24
uint32_t nal;
#define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE (0xFFFFFF<<0)
#define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT 0
#define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B (0xFF<<24)
#define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B_SHIFT 24
};
struct ustorm_iscsi_st_context
{
uint32_t exp_stat_sn ;
uint32_t exp_data_sn ;
struct rings_db ring ;
struct regpair_t task_pbl_base ;
struct regpair_t tce_phy_addr ;
struct ustorm_iscsi_placement_db place_db;
uint32_t reserved8 ;
uint32_t rem_rcv_len ;
#if defined(__BIG_ENDIAN)
uint16_t hdr_itt ;
uint16_t iscsi_conn_id;
#elif defined(__LITTLE_ENDIAN)
uint16_t iscsi_conn_id;
uint16_t hdr_itt ;
#endif
uint32_t nal_bytes ;
#if defined(__BIG_ENDIAN)
uint8_t hdr_second_byte_union ;
uint8_t bitfield_0;
#define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0)
#define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0
#define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1)
#define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1
#define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2)
#define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2
#define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3)
#define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3
uint8_t task_pdu_cache_index;
uint8_t task_pbe_cache_index;
#elif defined(__LITTLE_ENDIAN)
uint8_t task_pbe_cache_index;
uint8_t task_pdu_cache_index;
uint8_t bitfield_0;
#define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0)
#define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0
#define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1)
#define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1
#define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2)
#define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2
#define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3)
#define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3
uint8_t hdr_second_byte_union ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t reserved3 ;
uint8_t reserved2 ;
uint8_t acDecrement ;
#elif defined(__LITTLE_ENDIAN)
uint8_t acDecrement ;
uint8_t reserved2 ;
uint16_t reserved3 ;
#endif
uint32_t task_stat ;
#if defined(__BIG_ENDIAN)
uint8_t hdr_opcode ;
uint8_t num_cqs ;
uint16_t reserved5 ;
#elif defined(__LITTLE_ENDIAN)
uint16_t reserved5 ;
uint8_t num_cqs ;
uint8_t hdr_opcode ;
#endif
uint32_t negotiated_rx;
#define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH (0xFFFFFF<<0)
#define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT 0
#define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS (0xFF<<24)
#define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT 24
uint32_t negotiated_rx_and_flags;
#define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH (0xFFFFFF<<0)
#define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT 0
#define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED (0x1<<24)
#define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED_SHIFT 24
#define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN (0x1<<25)
#define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN_SHIFT 25
#define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN (0x1<<26)
#define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN_SHIFT 26
#define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR (0x1<<27)
#define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR_SHIFT 27
#define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID (0x1<<28)
#define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID_SHIFT 28
#define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE (0x3<<29)
#define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE_SHIFT 29
#define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED (0x1<<31)
#define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED_SHIFT 31
};
struct tstorm_tcp_st_context_section
{
uint32_t flags1;
#define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT (0xFFFFFF<<0)
#define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_SHIFT 0
#define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID (0x1<<24)
#define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID_SHIFT 24
#define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS (0x1<<25)
#define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS_SHIFT 25
#define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0 (0x1<<26)
#define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0_SHIFT 26
#define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD (0x1<<27)
#define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD_SHIFT 27
#define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED (0x1<<28)
#define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED_SHIFT 28
#define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE (0x1<<29)
#define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE_SHIFT 29
#define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN (0x1<<30)
#define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN_SHIFT 30
#define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN (0x1<<31)
#define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN_SHIFT 31
uint32_t flags2;
#define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION (0xFFFFFF<<0)
#define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_SHIFT 0
#define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN (0x1<<24)
#define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN_SHIFT 24
#define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN (0x1<<25)
#define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN_SHIFT 25
#define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT (0x1<<26)
#define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT_SHIFT 26
#define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT (0x1<<27)
#define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT_SHIFT 27
#define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<28)
#define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 28
#define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<29)
#define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 29
#define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK (0x1<<30)
#define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK_SHIFT 30
#define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK (0x1<<31)
#define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK_SHIFT 31
#if defined(__BIG_ENDIAN)
uint16_t mss;
uint8_t tcp_sm_state ;
uint8_t rto_exp ;
#elif defined(__LITTLE_ENDIAN)
uint8_t rto_exp ;
uint8_t tcp_sm_state ;
uint16_t mss;
#endif
uint32_t rcv_nxt ;
uint32_t timestamp_recent ;
uint32_t timestamp_recent_time ;
uint32_t cwnd ;
uint32_t ss_thresh ;
uint32_t cwnd_accum ;
uint32_t prev_seg_seq ;
uint32_t expected_rel_seq ;
uint32_t recover ;
#if defined(__BIG_ENDIAN)
uint8_t retransmit_count ;
uint8_t ka_max_probe_count ;
uint8_t persist_probe_count ;
uint8_t ka_probe_count ;
#elif defined(__LITTLE_ENDIAN)
uint8_t ka_probe_count ;
uint8_t persist_probe_count ;
uint8_t ka_max_probe_count ;
uint8_t retransmit_count ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t statistics_counter_id ;
uint8_t ooo_support_mode;
uint8_t snd_wnd_scale ;
uint8_t dup_ack_count ;
#elif defined(__LITTLE_ENDIAN)
uint8_t dup_ack_count ;
uint8_t snd_wnd_scale ;
uint8_t ooo_support_mode;
uint8_t statistics_counter_id ;
#endif
uint32_t retransmit_start_time ;
uint32_t ka_timeout ;
uint32_t ka_interval ;
uint32_t isle_start_seq ;
uint32_t isle_end_seq ;
#if defined(__BIG_ENDIAN)
uint16_t second_isle_address ;
uint16_t recent_seg_wnd ;
#elif defined(__LITTLE_ENDIAN)
uint16_t recent_seg_wnd ;
uint16_t second_isle_address ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t max_isles_ever_happened ;
uint8_t isles_number ;
uint16_t last_isle_address ;
#elif defined(__LITTLE_ENDIAN)
uint16_t last_isle_address ;
uint8_t isles_number ;
uint8_t max_isles_ever_happened ;
#endif
uint32_t max_rt_time;
#if defined(__BIG_ENDIAN)
uint16_t lsb_mac_address ;
uint16_t vlan_id ;
#elif defined(__LITTLE_ENDIAN)
uint16_t vlan_id ;
uint16_t lsb_mac_address ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t msb_mac_address ;
uint16_t mid_mac_address ;
#elif defined(__LITTLE_ENDIAN)
uint16_t mid_mac_address ;
uint16_t msb_mac_address ;
#endif
uint32_t rightmost_received_seq ;
};
struct iscsi_term_vars
{
uint8_t BitMap;
#define ISCSI_TERM_VARS_TCP_STATE (0xF<<0)
#define ISCSI_TERM_VARS_TCP_STATE_SHIFT 0
#define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4)
#define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4
#define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5)
#define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5
#define ISCSI_TERM_VARS_TERM_ON_CHIP (0x1<<6)
#define ISCSI_TERM_VARS_TERM_ON_CHIP_SHIFT 6
#define ISCSI_TERM_VARS_RSRV (0x1<<7)
#define ISCSI_TERM_VARS_RSRV_SHIFT 7
};
struct tstorm_iscsi_st_context_section
{
uint32_t nalPayload ;
uint32_t b2nh ;
#if defined(__BIG_ENDIAN)
uint16_t rq_cons ;
uint8_t flags;
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0)
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1)
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2)
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3)
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4)
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5)
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7)
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7
uint8_t hdr_bytes_2_fetch ;
#elif defined(__LITTLE_ENDIAN)
uint8_t hdr_bytes_2_fetch ;
uint8_t flags;
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0)
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1)
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2)
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3)
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4)
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5)
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7)
#define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7
uint16_t rq_cons ;
#endif
struct regpair_t rq_db_phy_addr;
#if defined(__BIG_ENDIAN)
struct iscsi_term_vars term_vars ;
uint8_t rsrv1;
uint16_t iscsi_conn_id;
#elif defined(__LITTLE_ENDIAN)
uint16_t iscsi_conn_id;
uint8_t rsrv1;
struct iscsi_term_vars term_vars ;
#endif
uint32_t process_nxt ;
};
struct tstorm_iscsi_st_context
{
struct tstorm_tcp_st_context_section tcp ;
struct tstorm_iscsi_st_context_section iscsi ;
};
struct xstorm_eth_context_section
{
#if defined(__BIG_ENDIAN)
uint8_t remote_addr_4 ;
uint8_t remote_addr_5 ;
uint8_t local_addr_0 ;
uint8_t local_addr_1 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t local_addr_1 ;
uint8_t local_addr_0 ;
uint8_t remote_addr_5 ;
uint8_t remote_addr_4 ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t remote_addr_0 ;
uint8_t remote_addr_1 ;
uint8_t remote_addr_2 ;
uint8_t remote_addr_3 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t remote_addr_3 ;
uint8_t remote_addr_2 ;
uint8_t remote_addr_1 ;
uint8_t remote_addr_0 ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t reserved_vlan_type ;
uint16_t vlan_params;
#define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
#define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
#define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12)
#define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12
#define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
#define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
#elif defined(__LITTLE_ENDIAN)
uint16_t vlan_params;
#define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
#define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
#define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12)
#define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12
#define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
#define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
uint16_t reserved_vlan_type ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t local_addr_2 ;
uint8_t local_addr_3 ;
uint8_t local_addr_4 ;
uint8_t local_addr_5 ;
#elif defined(__LITTLE_ENDIAN)
uint8_t local_addr_5 ;
uint8_t local_addr_4 ;
uint8_t local_addr_3 ;
uint8_t local_addr_2 ;
#endif
};
struct xstorm_ip_v4_context_section
{
#if defined(__BIG_ENDIAN)
uint16_t __pbf_hdr_cmd_rsvd_id;
uint16_t __pbf_hdr_cmd_rsvd_flags_offset;
#elif defined(__LITTLE_ENDIAN)
uint16_t __pbf_hdr_cmd_rsvd_flags_offset;
uint16_t __pbf_hdr_cmd_rsvd_id;
#endif
#if defined(__BIG_ENDIAN)
uint8_t __pbf_hdr_cmd_rsvd_ver_ihl;
uint8_t tos ;
uint16_t __pbf_hdr_cmd_rsvd_length;
#elif defined(__LITTLE_ENDIAN)
uint16_t __pbf_hdr_cmd_rsvd_length;
uint8_t tos ;
uint8_t __pbf_hdr_cmd_rsvd_ver_ihl;
#endif
uint32_t ip_local_addr ;
#if defined(__BIG_ENDIAN)
uint8_t ttl ;
uint8_t __pbf_hdr_cmd_rsvd_protocol;
uint16_t __pbf_hdr_cmd_rsvd_csum;
#elif defined(__LITTLE_ENDIAN)
uint16_t __pbf_hdr_cmd_rsvd_csum;
uint8_t __pbf_hdr_cmd_rsvd_protocol;
uint8_t ttl ;
#endif
uint32_t __pbf_hdr_cmd_rsvd_1 ;
uint32_t ip_remote_addr ;
};
struct xstorm_padded_ip_v4_context_section
{
struct xstorm_ip_v4_context_section ip_v4;
uint32_t reserved1[4];
};
struct xstorm_ip_v6_context_section
{
#if defined(__BIG_ENDIAN)
uint16_t pbf_hdr_cmd_rsvd_payload_len;
uint8_t pbf_hdr_cmd_rsvd_nxt_hdr;
uint8_t hop_limit ;
#elif defined(__LITTLE_ENDIAN)
uint8_t hop_limit ;
uint8_t pbf_hdr_cmd_rsvd_nxt_hdr;
uint16_t pbf_hdr_cmd_rsvd_payload_len;
#endif
uint32_t priority_flow_label;
#define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL (0xFFFFF<<0)
#define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL_SHIFT 0
#define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS (0xFF<<20)
#define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS_SHIFT 20
#define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER (0xF<<28)
#define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER_SHIFT 28
uint32_t ip_local_addr_lo_hi ;
uint32_t ip_local_addr_lo_lo ;
uint32_t ip_local_addr_hi_hi ;
uint32_t ip_local_addr_hi_lo ;
uint32_t ip_remote_addr_lo_hi ;
uint32_t ip_remote_addr_lo_lo ;
uint32_t ip_remote_addr_hi_hi ;
uint32_t ip_remote_addr_hi_lo ;
};
union xstorm_ip_context_section_types
{
struct xstorm_padded_ip_v4_context_section padded_ip_v4;
struct xstorm_ip_v6_context_section ip_v6;
};
struct xstorm_tcp_context_section
{
uint32_t snd_max;
#if defined(__BIG_ENDIAN)
uint16_t remote_port ;
uint16_t local_port ;
#elif defined(__LITTLE_ENDIAN)
uint16_t local_port ;
uint16_t remote_port ;
#endif
#if defined(__BIG_ENDIAN)
uint8_t original_nagle_1b;
uint8_t ts_enabled ;
uint16_t tcp_params;
#define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0)
#define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0
#define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8)
#define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8
#define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9)
#define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9
#define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10)
#define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10
#define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11)
#define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11
#define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12)
#define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12
#define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13)
#define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13
#define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14)
#define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14
#elif defined(__LITTLE_ENDIAN)
uint16_t tcp_params;
#define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0)
#define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0
#define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8)
#define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8
#define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9)
#define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9
#define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10)
#define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10
#define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11)
#define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11
#define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12)
#define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12
#define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13)
#define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13
#define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14)
#define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14
uint8_t ts_enabled ;
uint8_t original_nagle_1b;
#endif
#if defined(__BIG_ENDIAN)
uint16_t pseudo_csum ;
uint16_t window_scaling_factor ;
#elif defined(__LITTLE_ENDIAN)
uint16_t window_scaling_factor ;
uint16_t pseudo_csum ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t reserved2 ;
uint8_t statistics_counter_id ;
uint8_t statistics_params;
#define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0)
#define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0
#define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1)
#define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1
#define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2)
#define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2
#elif defined(__LITTLE_ENDIAN)
uint8_t statistics_params;
#define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0)
#define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0
#define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1)
#define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1
#define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2)
#define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2
uint8_t statistics_counter_id ;
uint16_t reserved2 ;
#endif
uint32_t ts_time_diff ;
uint32_t __next_timer_expir ;
};
struct xstorm_common_context_section
{
struct xstorm_eth_context_section ethernet;
union xstorm_ip_context_section_types ip_union;
struct xstorm_tcp_context_section tcp;
#if defined(__BIG_ENDIAN)
uint8_t __dcb_val;
uint8_t flags;
#define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0)
#define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0
#define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1)
#define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1
#define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4)
#define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4
#define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5)
#define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5
uint8_t outer_tag_flags;
#define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI (0x7<<0)
#define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI_SHIFT 0
#define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI (0x7<<3)
#define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI_SHIFT 3
#define XSTORM_COMMON_CONTEXT_SECTION_RESERVED (0x3<<6)
#define XSTORM_COMMON_CONTEXT_SECTION_RESERVED_SHIFT 6
uint8_t ip_version_1b;
#elif defined(__LITTLE_ENDIAN)
uint8_t ip_version_1b;
uint8_t outer_tag_flags;
#define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI (0x7<<0)
#define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI_SHIFT 0
#define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI (0x7<<3)
#define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI_SHIFT 3
#define XSTORM_COMMON_CONTEXT_SECTION_RESERVED (0x3<<6)
#define XSTORM_COMMON_CONTEXT_SECTION_RESERVED_SHIFT 6
uint8_t flags;
#define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0)
#define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0
#define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1)
#define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1
#define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4)
#define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4
#define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5)
#define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5
uint8_t __dcb_val;
#endif
};
struct xstorm_iscsi_context_flags
{
uint8_t flags;
#define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA (0x1<<0)
#define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA_SHIFT 0
#define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T (0x1<<1)
#define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T_SHIFT 1
#define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST (0x1<<2)
#define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST_SHIFT 2
#define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST (0x1<<3)
#define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST_SHIFT 3
#define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN (0x1<<4)
#define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN_SHIFT 4
#define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ (0x1<<5)
#define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ_SHIFT 5
#define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT (0x1<<6)
#define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT_SHIFT 6
#define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4 (0x1<<7)
#define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4_SHIFT 7
};
struct iscsi_task_context_entry_x
{
uint32_t data_out_buffer_offset;
uint32_t itt;
uint32_t data_sn;
};
struct iscsi_task_context_entry_xuc_x_write_only
{
uint32_t tx_r2t_sn ;
};
struct iscsi_task_context_entry_xuc_xu_write_both
{
uint32_t sgl_base_lo;
uint32_t sgl_base_hi;
#if defined(__BIG_ENDIAN)
uint8_t sgl_size;
uint8_t sge_index;
uint16_t sge_offset;
#elif defined(__LITTLE_ENDIAN)
uint16_t sge_offset;
uint8_t sge_index;
uint8_t sgl_size;
#endif
};
struct xstorm_iscsi_context_section
{
uint32_t first_burst_length;
uint32_t max_send_pdu_length;
struct regpair_t sq_pbl_base;
struct regpair_t sq_curr_pbe;
struct regpair_t hq_pbl_base;
struct regpair_t hq_curr_pbe_base;
struct regpair_t r2tq_pbl_base;
struct regpair_t r2tq_curr_pbe_base;
struct regpair_t task_pbl_base;
#if defined(__BIG_ENDIAN)
uint16_t data_out_count;
struct xstorm_iscsi_context_flags flags;
uint8_t task_pbl_cache_idx ;
#elif defined(__LITTLE_ENDIAN)
uint8_t task_pbl_cache_idx ;
struct xstorm_iscsi_context_flags flags;
uint16_t data_out_count;
#endif
uint32_t seq_more_2_send;
uint32_t pdu_more_2_send;
struct iscsi_task_context_entry_x temp_tce_x;
struct iscsi_task_context_entry_xuc_x_write_only temp_tce_x_wr;
struct iscsi_task_context_entry_xuc_xu_write_both temp_tce_xu_wr;
struct regpair_t lun;
uint32_t exp_data_transfer_len_ttt ;
uint32_t pdu_data_2_rxmit;
uint32_t rxmit_bytes_2_dr;
#if defined(__BIG_ENDIAN)
uint16_t rxmit_sge_offset;
uint16_t hq_rxmit_cons;
#elif defined(__LITTLE_ENDIAN)
uint16_t hq_rxmit_cons;
uint16_t rxmit_sge_offset;
#endif
#if defined(__BIG_ENDIAN)
uint16_t r2tq_cons;
uint8_t rxmit_flags;
#define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0)
#define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1)
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2)
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3)
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4)
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5)
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5
#define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7)
#define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7
uint8_t rxmit_sge_idx;
#elif defined(__LITTLE_ENDIAN)
uint8_t rxmit_sge_idx;
uint8_t rxmit_flags;
#define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0)
#define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1)
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2)
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3)
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4)
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5)
#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5
#define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7)
#define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7
uint16_t r2tq_cons;
#endif
uint32_t hq_rxmit_tcp_seq;
};
struct xstorm_iscsi_st_context
{
struct xstorm_common_context_section common;
struct xstorm_iscsi_context_section iscsi;
};
struct iscsi_context
{
struct ustorm_iscsi_st_context ustorm_st_context ;
struct tstorm_iscsi_st_context tstorm_st_context ;
struct xstorm_iscsi_ag_context xstorm_ag_context ;
struct tstorm_iscsi_ag_context tstorm_ag_context ;
struct cstorm_iscsi_ag_context cstorm_ag_context ;
struct ustorm_iscsi_ag_context ustorm_ag_context ;
struct timers_block_context timers_context ;
struct regpair_t upb_context ;
struct xstorm_iscsi_st_context xstorm_st_context ;
struct regpair_t xpb_context ;
struct cstorm_iscsi_st_context cstorm_st_context ;
};
struct iscsi_data_pdu_hdr_little_endian
{
#if defined(__BIG_ENDIAN)
uint8_t opcode;
uint8_t op_attr;
#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
uint16_t rsrv0;
#elif defined(__LITTLE_ENDIAN)
uint16_t rsrv0;
uint8_t op_attr;
#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
uint8_t opcode;
#endif
uint32_t data_fields;
#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
struct regpair_t lun;
uint32_t itt;
uint32_t ttt;
uint32_t rsrv2;
uint32_t exp_stat_sn;
uint32_t rsrv3;
uint32_t data_sn;
uint32_t buffer_offset;
uint32_t rsrv4;
};
struct iscsi_login_req_hdr_little_endian
{
#if defined(__BIG_ENDIAN)
uint8_t opcode;
uint8_t op_attr;
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0)
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2)
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4)
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7)
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7
uint8_t version_max;
uint8_t version_min;
#elif defined(__LITTLE_ENDIAN)
uint8_t version_min;
uint8_t version_max;
uint8_t op_attr;
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0)
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2)
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4)
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7)
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7
uint8_t opcode;
#endif
uint32_t data_fields;
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
uint32_t isid_lo;
#if defined(__BIG_ENDIAN)
uint16_t isid_hi;
uint16_t tsih;
#elif defined(__LITTLE_ENDIAN)
uint16_t tsih;
uint16_t isid_hi;
#endif
uint32_t itt;
#if defined(__BIG_ENDIAN)
uint16_t cid;
uint16_t rsrv1;
#elif defined(__LITTLE_ENDIAN)
uint16_t rsrv1;
uint16_t cid;
#endif
uint32_t cmd_sn;
uint32_t exp_stat_sn;
uint32_t rsrv2[4];
};
struct iscsi_logout_req_hdr_little_endian
{
#if defined(__BIG_ENDIAN)
uint8_t opcode;
uint8_t op_attr;
#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0)
#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0
#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
uint16_t rsrv0;
#elif defined(__LITTLE_ENDIAN)
uint16_t rsrv0;
uint8_t op_attr;
#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0)
#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0
#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
uint8_t opcode;
#endif
uint32_t data_fields;
#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
uint32_t rsrv2[2];
uint32_t itt;
#if defined(__BIG_ENDIAN)
uint16_t cid;
uint16_t rsrv1;
#elif defined(__LITTLE_ENDIAN)
uint16_t rsrv1;
uint16_t cid;
#endif
uint32_t cmd_sn;
uint32_t exp_stat_sn;
uint32_t rsrv3[4];
};
struct iscsi_tmf_req_hdr_little_endian
{
#if defined(__BIG_ENDIAN)
uint8_t opcode;
uint8_t op_attr;
#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0)
#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0
#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
uint16_t rsrv0;
#elif defined(__LITTLE_ENDIAN)
uint16_t rsrv0;
uint8_t op_attr;
#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0)
#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0
#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
uint8_t opcode;
#endif
uint32_t data_fields;
#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
struct regpair_t lun;
uint32_t itt;
uint32_t referenced_task_tag;
uint32_t cmd_sn;
uint32_t exp_stat_sn;
uint32_t ref_cmd_sn;
uint32_t exp_data_sn;
uint32_t rsrv2[2];
};
struct iscsi_text_req_hdr_little_endian
{
#if defined(__BIG_ENDIAN)
uint8_t opcode;
uint8_t op_attr;
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0)
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7)
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7
uint16_t rsrv0;
#elif defined(__LITTLE_ENDIAN)
uint16_t rsrv0;
uint8_t op_attr;
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0)
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7)
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7
uint8_t opcode;
#endif
uint32_t data_fields;
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
struct regpair_t lun;
uint32_t itt;
uint32_t ttt;
uint32_t cmd_sn;
uint32_t exp_stat_sn;
uint32_t rsrv3[4];
};
struct iscsi_nop_out_hdr_little_endian
{
#if defined(__BIG_ENDIAN)
uint8_t opcode;
uint8_t op_attr;
#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7)
#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7
uint16_t rsrv0;
#elif defined(__LITTLE_ENDIAN)
uint16_t rsrv0;
uint8_t op_attr;
#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7)
#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7
uint8_t opcode;
#endif
uint32_t data_fields;
#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
struct regpair_t lun;
uint32_t itt;
uint32_t ttt;
uint32_t cmd_sn;
uint32_t exp_stat_sn;
uint32_t rsrv3[4];
};
union iscsi_pdu_headers_little_endian
{
uint32_t fullHeaderSize[12] ;
struct iscsi_cmd_pdu_hdr_little_endian command_pdu_hdr ;
struct iscsi_data_pdu_hdr_little_endian data_out_pdu_hdr ;
struct iscsi_login_req_hdr_little_endian login_req_pdu_hdr ;
struct iscsi_logout_req_hdr_little_endian logout_req_pdu_hdr ;
struct iscsi_tmf_req_hdr_little_endian tmf_req_pdu_hdr ;
struct iscsi_text_req_hdr_little_endian text_req_pdu_hdr ;
struct iscsi_nop_out_hdr_little_endian nop_out_pdu_hdr ;
};
struct iscsi_hq_bd
{
union iscsi_pdu_headers_little_endian pdu_header;
#if defined(__BIG_ENDIAN)
uint16_t reserved1;
uint16_t lcl_cmp_flg;
#elif defined(__LITTLE_ENDIAN)
uint16_t lcl_cmp_flg;
uint16_t reserved1;
#endif
uint32_t sgl_base_lo;
uint32_t sgl_base_hi;
#if defined(__BIG_ENDIAN)
uint8_t sgl_size;
uint8_t sge_index;
uint16_t sge_offset;
#elif defined(__LITTLE_ENDIAN)
uint16_t sge_offset;
uint8_t sge_index;
uint8_t sgl_size;
#endif
};
struct iscsi_l2_ooo_data
{
uint32_t iscsi_cid ;
uint8_t drop_isle ;
uint8_t drop_size ;
uint8_t ooo_opcode ;
uint8_t ooo_isle ;
uint8_t reserved[8];
};
struct iscsi_task_context_entry_xuc_c_write_only
{
uint32_t total_data_acked ;
};
struct iscsi_task_context_r2t_table_entry
{
uint32_t ttt;
uint32_t desired_data_len;
};
struct iscsi_task_context_entry_xuc_u_write_only
{
uint32_t exp_r2t_sn ;
struct iscsi_task_context_r2t_table_entry r2t_table[4] ;
#if defined(__BIG_ENDIAN)
uint16_t data_in_count ;
uint8_t cq_id ;
uint8_t valid_1b ;
#elif defined(__LITTLE_ENDIAN)
uint8_t valid_1b ;
uint8_t cq_id ;
uint16_t data_in_count ;
#endif
};
struct iscsi_task_context_entry_xuc
{
struct iscsi_task_context_entry_xuc_c_write_only write_c ;
uint32_t exp_data_transfer_len ;
struct iscsi_task_context_entry_xuc_x_write_only write_x ;
uint32_t lun_lo ;
struct iscsi_task_context_entry_xuc_xu_write_both write_xu ;
uint32_t lun_hi ;
struct iscsi_task_context_entry_xuc_u_write_only write_u ;
};
struct iscsi_task_context_entry_u
{
uint32_t exp_r2t_buff_offset;
uint32_t rem_rcv_len;
uint32_t exp_data_sn;
};
struct iscsi_task_context_entry
{
struct iscsi_task_context_entry_x tce_x;
#if defined(__BIG_ENDIAN)
uint16_t data_out_count;
uint16_t rsrv0;
#elif defined(__LITTLE_ENDIAN)
uint16_t rsrv0;
uint16_t data_out_count;
#endif
struct iscsi_task_context_entry_xuc tce_xuc;
struct iscsi_task_context_entry_u tce_u;
uint32_t rsrv1[7] ;
};
struct iscsi_task_context_entry_xuc_x_init_only
{
struct regpair_t lun ;
uint32_t exp_data_transfer_len ;
};
struct afex_vif_list_ramrod_data
{
uint8_t afex_vif_list_command ;
uint8_t func_bit_map ;
uint16_t vif_list_index ;
uint8_t func_to_clear ;
uint8_t echo;
uint16_t reserved1;
};
struct c2s_pri_trans_table_entry
{
uint8_t val[MAX_VLAN_PRIORITIES] ;
};
struct cfc_del_event_data
{
uint32_t cid ;
uint32_t reserved0;
uint32_t reserved1;
};
struct cmng_flags_per_port
{
uint32_t cmng_enables;
#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
uint32_t __reserved1;
};
struct rate_shaping_vars_per_port
{
uint32_t rs_periodic_timeout ;
uint32_t rs_threshold ;
};
struct fairness_vars_per_port
{
uint32_t upper_bound ;
uint32_t fair_threshold ;
uint32_t fairness_timeout ;
uint32_t reserved0;
};
struct safc_struct_per_port
{
#if defined(__BIG_ENDIAN)
uint16_t __reserved1;
uint8_t __reserved0;
uint8_t safc_timeout_usec ;
#elif defined(__LITTLE_ENDIAN)
uint8_t safc_timeout_usec ;
uint8_t __reserved0;
uint16_t __reserved1;
#endif
uint8_t cos_to_traffic_types[MAX_COS_NUMBER] ;
uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] ;
};
struct cmng_struct_per_port
{
struct rate_shaping_vars_per_port rs_vars;
struct fairness_vars_per_port fair_vars;
struct safc_struct_per_port safc_vars;
struct cmng_flags_per_port flags;
};
struct rate_shaping_counter
{
uint32_t quota ;
#if defined(__BIG_ENDIAN)
uint16_t __reserved0;
uint16_t rate ;
#elif defined(__LITTLE_ENDIAN)
uint16_t rate ;
uint16_t __reserved0;
#endif
};
struct rate_shaping_vars_per_vn
{
struct rate_shaping_counter vn_counter ;
};
struct fairness_vars_per_vn
{
uint32_t cos_credit_delta[MAX_COS_NUMBER] ;
uint32_t vn_credit_delta ;
uint32_t __reserved0;
};
struct cmng_vnic
{
struct rate_shaping_vars_per_vn vnic_max_rate[4];
struct fairness_vars_per_vn vnic_min_rate[4];
};
struct cmng_init
{
struct cmng_struct_per_port port;
struct cmng_vnic vnic;
};
struct cmng_init_input
{
uint32_t port_rate;
uint16_t vnic_min_rate[4] ;
uint16_t vnic_max_rate[4] ;
uint16_t cos_min_rate[MAX_COS_NUMBER] ;
uint16_t cos_to_pause_mask[MAX_COS_NUMBER];
struct cmng_flags_per_port flags;
};
enum common_spqe_cmd_id
{
RAMROD_CMD_ID_COMMON_UNUSED,
RAMROD_CMD_ID_COMMON_FUNCTION_START ,
RAMROD_CMD_ID_COMMON_FUNCTION_STOP ,
RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE ,
RAMROD_CMD_ID_COMMON_CFC_DEL ,
RAMROD_CMD_ID_COMMON_CFC_DEL_WB ,
RAMROD_CMD_ID_COMMON_STAT_QUERY ,
RAMROD_CMD_ID_COMMON_STOP_TRAFFIC ,
RAMROD_CMD_ID_COMMON_START_TRAFFIC ,
RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS ,
RAMROD_CMD_ID_COMMON_SET_TIMESYNC ,
MAX_COMMON_SPQE_CMD_ID};
enum connection_type
{
ETH_CONNECTION_TYPE ,
TOE_CONNECTION_TYPE ,
RDMA_CONNECTION_TYPE ,
ISCSI_CONNECTION_TYPE ,
FCOE_CONNECTION_TYPE ,
RESERVED_CONNECTION_TYPE_0,
RESERVED_CONNECTION_TYPE_1,
RESERVED_CONNECTION_TYPE_2,
NONE_CONNECTION_TYPE ,
MAX_CONNECTION_TYPE};
enum cos_mode
{
OVERRIDE_COS ,
STATIC_COS ,
FW_WRR ,
MAX_COS_MODE};
struct hc_dynamic_drv_counter
{
uint32_t val[HC_SB_MAX_DYNAMIC_INDICES] ;
};
struct cstorm_queue_zone_data
{
struct hc_dynamic_drv_counter hc_dyn_drv_cnt ;
struct regpair_t reserved[2];
};
struct vf_pf_channel_zone_data
{
uint32_t msg_addr_lo ;
uint32_t msg_addr_hi ;
};
struct non_trigger_vf_zone
{
struct vf_pf_channel_zone_data vf_pf_channel ;
};
struct vf_pf_channel_zone_trigger
{
uint8_t addr_valid ;
};
struct trigger_vf_zone
{
#if defined(__BIG_ENDIAN)
uint16_t reserved1;
uint8_t reserved0;
struct vf_pf_channel_zone_trigger vf_pf_channel;
#elif defined(__LITTLE_ENDIAN)
struct vf_pf_channel_zone_trigger vf_pf_channel;
uint8_t reserved0;
uint16_t reserved1;
#endif
uint32_t reserved2;
};
struct cstorm_vf_zone_data
{
struct non_trigger_vf_zone non_trigger ;
struct trigger_vf_zone trigger ;
};
struct dynamic_hc_sm_config
{
uint32_t threshold[3] ;
uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] ;
uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] ;
uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] ;
uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] ;
uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] ;
};
struct dynamic_hc_config
{
struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] ;
};
struct e2_integ_data
{
#if defined(__BIG_ENDIAN)
uint8_t flags;
#define E2_INTEG_DATA_TESTING_EN (0x1<<0)
#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
#define E2_INTEG_DATA_LB_TX (0x1<<1)
#define E2_INTEG_DATA_LB_TX_SHIFT 1
#define E2_INTEG_DATA_COS_TX (0x1<<2)
#define E2_INTEG_DATA_COS_TX_SHIFT 2
#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
#define E2_INTEG_DATA_RESERVED (0x7<<5)
#define E2_INTEG_DATA_RESERVED_SHIFT 5
uint8_t cos ;
uint8_t voq ;
uint8_t pbf_queue ;
#elif defined(__LITTLE_ENDIAN)
uint8_t pbf_queue ;
uint8_t voq ;
uint8_t cos ;
uint8_t flags;
#define E2_INTEG_DATA_TESTING_EN (0x1<<0)
#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
#define E2_INTEG_DATA_LB_TX (0x1<<1)
#define E2_INTEG_DATA_LB_TX_SHIFT 1
#define E2_INTEG_DATA_COS_TX (0x1<<2)
#define E2_INTEG_DATA_COS_TX_SHIFT 2
#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
#define E2_INTEG_DATA_RESERVED (0x7<<5)
#define E2_INTEG_DATA_RESERVED_SHIFT 5
#endif
#if defined(__BIG_ENDIAN)
uint16_t reserved3;
uint8_t reserved2;
uint8_t ramEn ;
#elif defined(__LITTLE_ENDIAN)
uint8_t ramEn ;
uint8_t reserved2;
uint16_t reserved3;
#endif
};
struct eth_event_data
{
uint32_t echo ;
uint32_t reserved0;
uint32_t reserved1;
};
struct vf_pf_event_data
{
uint8_t vf_id ;
uint8_t reserved0;
uint16_t reserved1;
uint32_t msg_addr_lo ;
uint32_t msg_addr_hi ;
};
struct vf_flr_event_data
{
uint8_t vf_id ;
uint8_t reserved0;
uint16_t reserved1;
uint32_t reserved2;
uint32_t reserved3;
};
struct malicious_vf_event_data
{
uint8_t vf_id ;
uint8_t err_id ;
uint16_t reserved1;
uint32_t reserved2;
uint32_t reserved3;
};
struct vif_list_event_data
{
uint8_t func_bit_map ;
uint8_t echo;
uint16_t reserved0;
uint32_t reserved1;
uint32_t reserved2;
};
struct function_update_event_data
{
uint8_t echo;
uint8_t reserved;
uint16_t reserved0;
uint32_t reserved1;
uint32_t reserved2;
};
union event_data
{
struct vf_pf_event_data vf_pf_event ;
struct eth_event_data eth_event ;
struct cfc_del_event_data cfc_del_event ;
struct vf_flr_event_data vf_flr_event ;
struct malicious_vf_event_data malicious_vf_event ;
struct vif_list_event_data vif_list_event ;
struct function_update_event_data function_update_event ;
};
struct event_ring_data
{
struct regpair_native_t base_addr ;
#if defined(__BIG_ENDIAN)
uint8_t index_id ;
uint8_t sb_id ;
uint16_t producer ;
#elif defined(__LITTLE_ENDIAN)
uint16_t producer ;
uint8_t sb_id ;
uint8_t index_id ;
#endif
uint32_t reserved0;
};
struct event_ring_msg
{
uint8_t opcode;
uint8_t error ;
uint16_t reserved1;
union event_data data ;
};
struct event_ring_next
{
struct regpair_t addr ;
uint32_t reserved[2];
};
union event_ring_elem
{
struct event_ring_msg message ;
struct event_ring_next next_page ;
};
enum event_ring_opcode
{
EVENT_RING_OPCODE_VF_PF_CHANNEL,
EVENT_RING_OPCODE_FUNCTION_START ,
EVENT_RING_OPCODE_FUNCTION_STOP ,
EVENT_RING_OPCODE_CFC_DEL ,
EVENT_RING_OPCODE_CFC_DEL_WB ,
EVENT_RING_OPCODE_STAT_QUERY ,
EVENT_RING_OPCODE_STOP_TRAFFIC ,
EVENT_RING_OPCODE_START_TRAFFIC ,
EVENT_RING_OPCODE_VF_FLR ,
EVENT_RING_OPCODE_MALICIOUS_VF ,
EVENT_RING_OPCODE_FORWARD_SETUP ,
EVENT_RING_OPCODE_RSS_UPDATE_RULES ,
EVENT_RING_OPCODE_FUNCTION_UPDATE ,
EVENT_RING_OPCODE_AFEX_VIF_LISTS ,
EVENT_RING_OPCODE_SET_MAC ,
EVENT_RING_OPCODE_CLASSIFICATION_RULES ,
EVENT_RING_OPCODE_FILTERS_RULES ,
EVENT_RING_OPCODE_MULTICAST_RULES ,
EVENT_RING_OPCODE_SET_TIMESYNC ,
MAX_EVENT_RING_OPCODE};
enum fairness_mode
{
FAIRNESS_COS_WRR_MODE ,
FAIRNESS_COS_ETS_MODE ,
MAX_FAIRNESS_MODE};
struct priority_cos
{
uint8_t priority ;
uint8_t cos ;
uint16_t reserved1;
};
struct flow_control_configuration
{
struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] ;
uint8_t dcb_enabled ;
uint8_t dcb_version ;
uint8_t dont_add_pri_0 ;
uint8_t reserved1;
uint32_t reserved2;
uint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES] ;
};
struct function_start_data
{
uint8_t function_mode ;
uint8_t allow_npar_tx_switching ;
uint16_t sd_vlan_tag ;
uint16_t vif_id ;
uint8_t path_id;
uint8_t network_cos_mode ;
uint8_t dmae_cmd_id ;
uint8_t no_added_tags ;
uint16_t reserved0;
uint32_t reserved1;
uint8_t inner_clss_vxlan ;
uint8_t inner_clss_l2gre ;
uint8_t inner_clss_l2geneve ;
uint8_t inner_rss ;
uint16_t vxlan_dst_port ;
uint16_t geneve_dst_port ;
uint8_t sd_accept_mf_clss_fail ;
uint8_t sd_accept_mf_clss_fail_match_ethtype ;
uint16_t sd_accept_mf_clss_fail_ethtype ;
uint16_t sd_vlan_eth_type ;
uint8_t sd_vlan_force_pri_flg ;
uint8_t sd_vlan_force_pri_val ;
uint8_t c2s_pri_tt_valid ;
uint8_t c2s_pri_default ;
uint8_t reserved2[6];
struct c2s_pri_trans_table_entry c2s_pri_trans_table ;
};
struct function_update_data
{
uint8_t vif_id_change_flg ;
uint8_t afex_default_vlan_change_flg ;
uint8_t allowed_priorities_change_flg ;
uint8_t network_cos_mode_change_flg ;
uint16_t vif_id ;
uint16_t afex_default_vlan ;
uint8_t allowed_priorities ;
uint8_t network_cos_mode ;
uint8_t lb_mode_en_change_flg ;
uint8_t lb_mode_en ;
uint8_t tx_switch_suspend_change_flg ;
uint8_t tx_switch_suspend ;
uint8_t echo;
uint8_t update_tunn_cfg_flg ;
uint8_t inner_clss_vxlan ;
uint8_t inner_clss_l2gre ;
uint8_t inner_clss_l2geneve ;
uint8_t inner_rss ;
uint16_t vxlan_dst_port ;
uint16_t geneve_dst_port ;
uint8_t sd_vlan_force_pri_change_flg ;
uint8_t sd_vlan_force_pri_flg ;
uint8_t sd_vlan_force_pri_val ;
uint8_t sd_vlan_tag_change_flg ;
uint8_t sd_vlan_eth_type_change_flg ;
uint8_t reserved1;
uint16_t sd_vlan_tag ;
uint16_t sd_vlan_eth_type ;
uint16_t reserved0;
uint32_t reserved2;
};
struct fw_version
{
#if defined(__BIG_ENDIAN)
uint8_t engineering ;
uint8_t revision ;
uint8_t minor ;
uint8_t major ;
#elif defined(__LITTLE_ENDIAN)
uint8_t major ;
uint8_t minor ;
uint8_t revision ;
uint8_t engineering ;
#endif
uint32_t flags;
#define FW_VERSION_OPTIMIZED (0x1<<0)
#define FW_VERSION_OPTIMIZED_SHIFT 0
#define FW_VERSION_BIG_ENDIEN (0x1<<1)
#define FW_VERSION_BIG_ENDIEN_SHIFT 1
#define FW_VERSION_CHIP_VERSION (0x3<<2)
#define FW_VERSION_CHIP_VERSION_SHIFT 2
#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
#define __FW_VERSION_RESERVED_SHIFT 4
};
struct hc_dynamic_sb_drv_counters
{
uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] ;
};
struct hc_index_data
{
#if defined(__BIG_ENDIAN)
uint8_t flags;
#define HC_INDEX_DATA_SM_ID (0x1<<0)
#define HC_INDEX_DATA_SM_ID_SHIFT 0
#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
#define HC_INDEX_DATA_RESERVE (0x1F<<3)
#define HC_INDEX_DATA_RESERVE_SHIFT 3
uint8_t timeout ;
#elif defined(__LITTLE_ENDIAN)
uint8_t timeout ;
uint8_t flags;
#define HC_INDEX_DATA_SM_ID (0x1<<0)
#define HC_INDEX_DATA_SM_ID_SHIFT 0
#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
#define HC_INDEX_DATA_RESERVE (0x1F<<3)
#define HC_INDEX_DATA_RESERVE_SHIFT 3
#endif
};
struct hc_status_block_sm
{
#if defined(__BIG_ENDIAN)
uint8_t igu_seg_id;
uint8_t igu_sb_id ;
uint8_t timer_value ;
uint8_t __flags;
#elif defined(__LITTLE_ENDIAN)
uint8_t __flags;
uint8_t timer_value ;
uint8_t igu_sb_id ;
uint8_t igu_seg_id;
#endif
uint32_t time_to_expire ;
};
struct pci_entity
{
#if defined(__BIG_ENDIAN)
uint8_t vf_valid ;
uint8_t vf_id ;
uint8_t vnic_id ;
uint8_t pf_id ;
#elif defined(__LITTLE_ENDIAN)
uint8_t pf_id ;
uint8_t vnic_id ;
uint8_t vf_id ;
uint8_t vf_valid ;
#endif
};
struct hc_sb_data
{
struct regpair_native_t host_sb_addr ;
struct hc_status_block_sm state_machine[HC_SB_MAX_SM] ;
struct pci_entity p_func ;
#if defined(__BIG_ENDIAN)
uint8_t rsrv0;
uint8_t state;
uint8_t dhc_qzone_id ;
uint8_t same_igu_sb_1b ;
#elif defined(__LITTLE_ENDIAN)
uint8_t same_igu_sb_1b ;
uint8_t dhc_qzone_id ;
uint8_t state;
uint8_t rsrv0;
#endif
struct regpair_native_t rsrv1[2];
};
enum hc_segment
{
HC_REGULAR_SEGMENT,
HC_DEFAULT_SEGMENT,
MAX_HC_SEGMENT};
struct hc_sp_status_block_data
{
struct regpair_native_t host_sb_addr ;
#if defined(__BIG_ENDIAN)
uint8_t rsrv1;
uint8_t state;
uint8_t igu_seg_id ;
uint8_t igu_sb_id ;
#elif defined(__LITTLE_ENDIAN)
uint8_t igu_sb_id ;
uint8_t igu_seg_id ;
uint8_t state;
uint8_t rsrv1;
#endif
struct pci_entity p_func ;
};
struct hc_status_block_data_e1x
{
struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] ;
struct hc_sb_data common ;
};
struct hc_status_block_data_e2
{
struct hc_index_data index_data[HC_SB_MAX_INDICES_E2] ;
struct hc_sb_data common ;
};
enum igu_mode
{
HC_IGU_BC_MODE ,
HC_IGU_NBC_MODE ,
MAX_IGU_MODE};
enum inner_clss_type
{
INNER_CLSS_DISABLED ,
INNER_CLSS_USE_VLAN ,
INNER_CLSS_USE_VNI ,
MAX_INNER_CLSS_TYPE};
enum ip_ver
{
IP_V4,
IP_V6,
MAX_IP_VER};
enum malicious_vf_error_id
{
MALICIOUS_VF_NO_ERROR ,
VF_PF_CHANNEL_NOT_READY ,
ETH_ILLEGAL_BD_LENGTHS ,
ETH_PACKET_TOO_SHORT ,
ETH_PAYLOAD_TOO_BIG ,
ETH_ILLEGAL_ETH_TYPE ,
ETH_ILLEGAL_LSO_HDR_LEN ,
ETH_TOO_MANY_BDS ,
ETH_ZERO_HDR_NBDS ,
ETH_START_BD_NOT_SET ,
ETH_ILLEGAL_PARSE_NBDS ,
ETH_IPV6_AND_CHECKSUM ,
ETH_VLAN_FLG_INCORRECT ,
ETH_ILLEGAL_LSO_MSS ,
ETH_TUNNEL_NOT_SUPPORTED ,
MAX_MALICIOUS_VF_ERROR_ID};
enum mf_mode
{
SINGLE_FUNCTION,
MULTI_FUNCTION_SD ,
MULTI_FUNCTION_SI ,
MULTI_FUNCTION_AFEX ,
MAX_MF_MODE};
struct tstorm_per_pf_stats
{
struct regpair_t rcv_error_bytes ;
};
struct per_pf_stats
{
struct tstorm_per_pf_stats tstorm_pf_statistics;
};
struct tstorm_per_port_stats
{
uint32_t mac_discard ;
uint32_t mac_filter_discard ;
uint32_t brb_truncate_discard ;
uint32_t mf_tag_discard ;
uint32_t packet_drop ;
uint32_t reserved;
};
struct per_port_stats
{
struct tstorm_per_port_stats tstorm_port_statistics;
};
struct tstorm_per_queue_stats
{
struct regpair_t rcv_ucast_bytes ;
uint32_t rcv_ucast_pkts ;
uint32_t checksum_discard ;
struct regpair_t rcv_bcast_bytes ;
uint32_t rcv_bcast_pkts ;
uint32_t pkts_too_big_discard ;
struct regpair_t rcv_mcast_bytes ;
uint32_t rcv_mcast_pkts ;
uint32_t ttl0_discard ;
uint16_t no_buff_discard;
uint16_t reserved0;
uint32_t reserved1;
};
struct ustorm_per_queue_stats
{
struct regpair_t ucast_no_buff_bytes ;
struct regpair_t mcast_no_buff_bytes ;
struct regpair_t bcast_no_buff_bytes ;
uint32_t ucast_no_buff_pkts ;
uint32_t mcast_no_buff_pkts ;
uint32_t bcast_no_buff_pkts ;
uint32_t coalesced_pkts ;
struct regpair_t coalesced_bytes ;
uint32_t coalesced_events ;
uint32_t coalesced_aborts ;
};
struct xstorm_per_queue_stats
{
struct regpair_t ucast_bytes_sent ;
struct regpair_t mcast_bytes_sent ;
struct regpair_t bcast_bytes_sent ;
uint32_t ucast_pkts_sent ;
uint32_t mcast_pkts_sent ;
uint32_t bcast_pkts_sent ;
uint32_t error_drop_pkts ;
};
struct per_queue_stats
{
struct tstorm_per_queue_stats tstorm_queue_statistics;
struct ustorm_per_queue_stats ustorm_queue_statistics;
struct xstorm_per_queue_stats xstorm_queue_statistics;
};
struct pram_fw_version
{
uint8_t major ;
uint8_t minor ;
uint8_t revision ;
uint8_t engineering ;
uint8_t flags;
#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
#define PRAM_FW_VERSION_STORM_ID (0x3<<1)
#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
};
union protocol_common_specific_data
{
uint8_t protocol_data[8] ;
struct regpair_t phy_address ;
struct regpair_t mac_config_addr ;
struct afex_vif_list_ramrod_data afex_vif_list_data ;
};
struct protocol_common_spe
{
struct spe_hdr_t hdr ;
union protocol_common_specific_data data ;
};
struct set_timesync_ramrod_data
{
uint8_t drift_adjust_cmd ;
uint8_t offset_cmd ;
uint8_t add_sub_drift_adjust_value ;
uint8_t drift_adjust_value ;
uint32_t drift_adjust_period ;
struct regpair_t offset_delta ;
};
struct slow_path_element
{
struct spe_hdr_t hdr ;
struct regpair_t protocol_data ;
};
struct stats_counter
{
uint16_t xstats_counter ;
uint16_t reserved0;
uint32_t reserved1;
uint16_t tstats_counter ;
uint16_t reserved2;
uint32_t reserved3;
uint16_t ustats_counter ;
uint16_t reserved4;
uint32_t reserved5;
uint16_t cstats_counter ;
uint16_t reserved6;
uint32_t reserved7;
};
struct stats_query_entry
{
uint8_t kind;
uint8_t index ;
uint16_t funcID ;
uint32_t reserved;
struct regpair_t address ;
};
struct stats_query_cmd_group
{
struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
};
struct stats_query_header
{
uint8_t cmd_num ;
uint8_t reserved0;
uint16_t drv_stats_counter;
uint32_t reserved1;
struct regpair_t stats_counters_addrs ;
};
enum stats_query_type
{
STATS_TYPE_QUEUE,
STATS_TYPE_PORT,
STATS_TYPE_PF,
STATS_TYPE_TOE,
STATS_TYPE_FCOE,
MAX_STATS_QUERY_TYPE};
enum status_block_state
{
SB_DISABLED,
SB_ENABLED,
SB_CLEANED,
MAX_STATUS_BLOCK_STATE};
enum storm_id
{
USTORM_ID,
CSTORM_ID,
XSTORM_ID,
TSTORM_ID,
ATTENTION_ID,
MAX_STORM_ID};
enum traffic_type
{
LLFC_TRAFFIC_TYPE_NW ,
LLFC_TRAFFIC_TYPE_FCOE ,
LLFC_TRAFFIC_TYPE_ISCSI ,
MAX_TRAFFIC_TYPE};
struct tstorm_queue_zone_data
{
struct regpair_t reserved[4];
};
struct tstorm_vf_zone_data
{
struct regpair_t reserved;
};
enum ts_add_sub_value
{
TS_SUB_VALUE ,
TS_ADD_VALUE ,
MAX_TS_ADD_SUB_VALUE};
enum ts_drift_adjust_cmd
{
TS_DRIFT_ADJUST_KEEP ,
TS_DRIFT_ADJUST_SET ,
TS_DRIFT_ADJUST_RESET ,
MAX_TS_DRIFT_ADJUST_CMD};
enum ts_offset_cmd
{
TS_OFFSET_KEEP ,
TS_OFFSET_INC ,
TS_OFFSET_DEC ,
MAX_TS_OFFSET_CMD};
struct t_measure_pci_latency_ctrl
{
struct regpair_t read_addr ;
#if defined(__BIG_ENDIAN)
uint8_t sleep ;
uint8_t enable ;
uint8_t func_id ;
uint8_t read_size ;
#elif defined(__LITTLE_ENDIAN)
uint8_t read_size ;
uint8_t func_id ;
uint8_t enable ;
uint8_t sleep ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t num_meas ;
uint8_t reserved;
uint8_t period_10us ;
#elif defined(__LITTLE_ENDIAN)
uint8_t period_10us ;
uint8_t reserved;
uint16_t num_meas ;
#endif
};
struct t_measure_pci_latency_data
{
#if defined(__BIG_ENDIAN)
uint16_t max_time_ns ;
uint16_t min_time_ns ;
#elif defined(__LITTLE_ENDIAN)
uint16_t min_time_ns ;
uint16_t max_time_ns ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t reserved;
uint16_t num_reads ;
#elif defined(__LITTLE_ENDIAN)
uint16_t num_reads ;
uint16_t reserved;
#endif
struct regpair_t sum_time_ns ;
};
struct ustorm_queue_zone_data
{
struct ustorm_eth_rx_producers eth_rx_producers ;
struct regpair_t reserved[3];
};
struct ustorm_vf_zone_data
{
struct regpair_t reserved;
};
struct vf_pf_channel_data
{
#if defined(__BIG_ENDIAN)
uint16_t reserved0;
uint8_t valid ;
uint8_t state ;
#elif defined(__LITTLE_ENDIAN)
uint8_t state ;
uint8_t valid ;
uint16_t reserved0;
#endif
uint32_t reserved1;
};
enum vf_pf_channel_state
{
VF_PF_CHANNEL_STATE_READY ,
VF_PF_CHANNEL_STATE_WAITING_FOR_ACK ,
MAX_VF_PF_CHANNEL_STATE};
enum vif_list_rule_kind
{
VIF_LIST_RULE_SET,
VIF_LIST_RULE_GET,
VIF_LIST_RULE_CLEAR_ALL,
VIF_LIST_RULE_CLEAR_FUNC,
MAX_VIF_LIST_RULE_KIND};
struct xstorm_queue_zone_data
{
struct regpair_t reserved[4];
};
struct xstorm_vf_zone_data
{
struct regpair_t reserved;
};
enum tcp_ooo_event
{
TCP_EVENT_ADD_PEN=0,
TCP_EVENT_ADD_NEW_ISLE=1,
TCP_EVENT_ADD_ISLE_RIGHT=2,
TCP_EVENT_ADD_ISLE_LEFT=3,
TCP_EVENT_JOIN=4,
TCP_EVENT_NOP=5,
MAX_TCP_OOO_EVENT};
enum tcp_tstorm_ooo
{
TCP_TSTORM_OOO_DROP_AND_PROC_ACK,
TCP_TSTORM_OOO_SEND_PURE_ACK,
TCP_TSTORM_OOO_SUPPORTED,
MAX_TCP_TSTORM_OOO};
struct cstorm_toe_stats
{
uint32_t no_tx_cqes ;
uint32_t reserved;
};
struct cstorm_toe_st_context
{
uint32_t bds_ring_page_base_addr_lo ;
uint32_t bds_ring_page_base_addr_hi ;
uint32_t free_seq ;
uint32_t __last_rel_to_notify ;
#if defined(__BIG_ENDIAN)
uint16_t __rss_params_ram_line ;
uint16_t bd_cons ;
#elif defined(__LITTLE_ENDIAN)
uint16_t bd_cons ;
uint16_t __rss_params_ram_line ;
#endif
uint32_t cpu_id ;
uint32_t prev_snd_max ;
uint32_t __reserved4 ;
};
struct cstorm_toe_st_aligned_context
{
struct cstorm_toe_st_context context ;
};
struct ustorm_toe_prefetched_isle_bd
{
uint32_t __addr_lo ;
uint32_t __addr_hi ;
#if defined(__BIG_ENDIAN)
uint8_t __reserved1 ;
uint8_t __isle_num ;
uint16_t __buf_un_used ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __buf_un_used ;
uint8_t __isle_num ;
uint8_t __reserved1 ;
#endif
};
struct ustorm_toe_ring_params
{
uint32_t rq_cons_addr_lo ;
uint32_t rq_cons_addr_hi ;
#if defined(__BIG_ENDIAN)
uint8_t __rq_local_cons ;
uint8_t __rq_local_prod ;
uint16_t rq_cons ;
#elif defined(__LITTLE_ENDIAN)
uint16_t rq_cons ;
uint8_t __rq_local_prod ;
uint8_t __rq_local_cons ;
#endif
};
struct ustorm_toe_prefetched_bd
{
uint32_t __addr_lo ;
uint32_t __addr_hi ;
#if defined(__BIG_ENDIAN)
uint16_t flags;
#define __USTORM_TOE_PREFETCHED_BD_START (0x1<<0)
#define __USTORM_TOE_PREFETCHED_BD_START_SHIFT 0
#define __USTORM_TOE_PREFETCHED_BD_END (0x1<<1)
#define __USTORM_TOE_PREFETCHED_BD_END_SHIFT 1
#define __USTORM_TOE_PREFETCHED_BD_NO_PUSH (0x1<<2)
#define __USTORM_TOE_PREFETCHED_BD_NO_PUSH_SHIFT 2
#define USTORM_TOE_PREFETCHED_BD_SPLIT (0x1<<3)
#define USTORM_TOE_PREFETCHED_BD_SPLIT_SHIFT 3
#define __USTORM_TOE_PREFETCHED_BD_RESERVED1 (0xFFF<<4)
#define __USTORM_TOE_PREFETCHED_BD_RESERVED1_SHIFT 4
uint16_t __buf_un_used ;
#elif defined(__LITTLE_ENDIAN)
uint16_t __buf_un_used ;
uint16_t flags;
#define __USTORM_TOE_PREFETCHED_BD_START (0x1<<0)
#define __USTORM_TOE_PREFETCHED_BD_START_SHIFT 0
#define __USTORM_TOE_PREFETCHED_BD_END (0x1<<1)
#define __USTORM_TOE_PREFETCHED_BD_END_SHIFT 1
#define __USTORM_TOE_PREFETCHED_BD_NO_PUSH (0x1<<2)
#define __USTORM_TOE_PREFETCHED_BD_NO_PUSH_SHIFT 2
#define USTORM_TOE_PREFETCHED_BD_SPLIT (0x1<<3)
#define USTORM_TOE_PREFETCHED_BD_SPLIT_SHIFT 3
#define __USTORM_TOE_PREFETCHED_BD_RESERVED1 (0xFFF<<4)
#define __USTORM_TOE_PREFETCHED_BD_RESERVED1_SHIFT 4
#endif
};
struct ustorm_toe_st_context
{
uint32_t __pen_rq_placed ;
uint32_t pen_grq_placed_bytes ;
#if defined(__BIG_ENDIAN)
uint8_t flags2;
#define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH (0x1<<0)
#define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH_SHIFT 0
#define USTORM_TOE_ST_CONTEXT_PUSH_FLAG (0x1<<1)
#define USTORM_TOE_ST_CONTEXT_PUSH_FLAG_SHIFT 1
#define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED (0x1<<2)
#define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED_SHIFT 2
#define USTORM_TOE_ST_CONTEXT_RESERVED0 (0x1F<<3)
#define USTORM_TOE_ST_CONTEXT_RESERVED0_SHIFT 3
uint8_t __indirection_shift ;
uint16_t indirection_ram_offset ;
#elif defined(__LITTLE_ENDIAN)
uint16_t indirection_ram_offset ;
uint8_t __indirection_shift ;
uint8_t flags2;
#define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH (0x1<<0)
#define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH_SHIFT 0
#define USTORM_TOE_ST_CONTEXT_PUSH_FLAG (0x1<<1)
#define USTORM_TOE_ST_CONTEXT_PUSH_FLAG_SHIFT 1
#define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED (0x1<<2)
#define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED_SHIFT 2
#define USTORM_TOE_ST_CONTEXT_RESERVED0 (0x1F<<3)
#define USTORM_TOE_ST_CONTEXT_RESERVED0_SHIFT 3
#endif
uint32_t __rq_available_bytes;
#if defined(__BIG_ENDIAN)
uint8_t isles_counter ;
uint8_t __push_timer_state ;
uint16_t rcv_indication_size ;
#elif defined(__LITTLE_ENDIAN)
uint16_t rcv_indication_size ;
uint8_t __push_timer_state ;
uint8_t isles_counter ;
#endif
uint32_t __min_expiration_time ;
uint32_t initial_rcv_wnd ;
uint32_t __bytes_cons ;
uint32_t __prev_consumed_grq_bytes ;
uint32_t prev_rcv_win_right_edge ;
uint32_t rcv_nxt ;
struct ustorm_toe_prefetched_isle_bd __isle_bd ;
struct ustorm_toe_ring_params pen_ring_params ;
struct ustorm_toe_prefetched_bd __pen_bd_0 ;
struct ustorm_toe_prefetched_bd __pen_bd_1 ;
struct ustorm_toe_prefetched_bd __pen_bd_2 ;
struct ustorm_toe_prefetched_bd __pen_bd_3 ;
struct ustorm_toe_prefetched_bd __pen_bd_4 ;
struct ustorm_toe_prefetched_bd __pen_bd_5 ;
struct ustorm_toe_prefetched_bd __pen_bd_6 ;
struct ustorm_toe_prefetched_bd __pen_bd_7 ;
struct ustorm_toe_prefetched_bd __pen_bd_8 ;
struct ustorm_toe_prefetched_bd __pen_bd_9 ;
uint32_t __reserved3 ;
};
struct ustorm_toe_st_aligned_context
{
struct ustorm_toe_st_context context ;
};
struct tstorm_toe_st_context_section
{
uint32_t reserved0[3];
};
struct tstorm_toe_st_context
{
struct tstorm_tcp_st_context_section tcp ;
struct tstorm_toe_st_context_section toe ;
};
struct tstorm_toe_st_aligned_context
{
struct tstorm_toe_st_context context ;
uint8_t padding[16] ;
};
struct xstorm_toe_context_section
{
uint32_t tx_bd_page_base_lo ;
uint32_t tx_bd_page_base_hi ;
#if defined(__BIG_ENDIAN)
uint16_t tx_bd_offset ;
uint16_t tx_bd_cons ;
#elif defined(__LITTLE_ENDIAN)
uint16_t tx_bd_cons ;
uint16_t tx_bd_offset ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t bd_prod;
uint16_t seqMismatchCnt;
#elif defined(__LITTLE_ENDIAN)
uint16_t seqMismatchCnt;
uint16_t bd_prod;
#endif
uint32_t driver_doorbell_info_ptr_lo;
uint32_t driver_doorbell_info_ptr_hi;
};
struct xstorm_toe_st_context
{
struct xstorm_common_context_section common;
struct xstorm_toe_context_section toe;
};
struct xstorm_toe_st_aligned_context
{
struct xstorm_toe_st_context context ;
};
struct toe_context
{
struct ustorm_toe_st_aligned_context ustorm_st_context ;
struct tstorm_toe_st_aligned_context tstorm_st_context ;
struct xstorm_toe_ag_context xstorm_ag_context ;
struct tstorm_toe_ag_context tstorm_ag_context ;
struct cstorm_toe_ag_context cstorm_ag_context ;
struct ustorm_toe_ag_context ustorm_ag_context ;
struct timers_block_context timers_context ;
struct xstorm_toe_st_aligned_context xstorm_st_context ;
struct cstorm_toe_st_aligned_context cstorm_st_context ;
};
struct toe_initiate_offload_ramrod_data
{
uint32_t flags;
#define TOE_INITIATE_OFFLOAD_RAMROD_DATA_SEARCH_CONFIG_FAILED (0x1<<0)
#define TOE_INITIATE_OFFLOAD_RAMROD_DATA_SEARCH_CONFIG_FAILED_SHIFT 0
#define TOE_INITIATE_OFFLOAD_RAMROD_DATA_LICENSE_FAILURE (0x1<<1)
#define TOE_INITIATE_OFFLOAD_RAMROD_DATA_LICENSE_FAILURE_SHIFT 1
#define TOE_INITIATE_OFFLOAD_RAMROD_DATA_RESERVED0 (0x3FFFFFFF<<2)
#define TOE_INITIATE_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 2
uint32_t reserved1;
};
struct toe_init_ramrod_data
{
#if defined(__BIG_ENDIAN)
uint16_t reserved1;
uint8_t reserved0;
uint8_t rss_num ;
#elif defined(__LITTLE_ENDIAN)
uint8_t rss_num ;
uint8_t reserved0;
uint16_t reserved1;
#endif
uint32_t reserved2;
};
struct toe_page_addr_bd
{
uint32_t addr_lo ;
uint32_t addr_hi ;
uint8_t reserved[8] ;
};
union toe_ramrod_data
{
struct ramrod_data general;
struct toe_initiate_offload_ramrod_data initiate_offload;
};
enum toe_rss_update_opcode
{
TOE_RSS_UPD_QUIET,
TOE_RSS_UPD_SLEEPING,
TOE_RSS_UPD_DELAYED,
MAX_TOE_RSS_UPDATE_OPCODE};
struct toe_rss_update_ramrod_data
{
uint8_t indirection_table[128] ;
#if defined(__BIG_ENDIAN)
uint16_t reserved0;
uint16_t toe_rss_bitmap ;
#elif defined(__LITTLE_ENDIAN)
uint16_t toe_rss_bitmap ;
uint16_t reserved0;
#endif
uint32_t reserved1;
};
struct toe_rx_bd
{
uint32_t addr_lo ;
uint32_t addr_hi ;
#if defined(__BIG_ENDIAN)
uint16_t flags;
#define TOE_RX_BD_START (0x1<<0)
#define TOE_RX_BD_START_SHIFT 0
#define TOE_RX_BD_END (0x1<<1)
#define TOE_RX_BD_END_SHIFT 1
#define TOE_RX_BD_NO_PUSH (0x1<<2)
#define TOE_RX_BD_NO_PUSH_SHIFT 2
#define TOE_RX_BD_SPLIT (0x1<<3)
#define TOE_RX_BD_SPLIT_SHIFT 3
#define TOE_RX_BD_RESERVED1 (0xFFF<<4)
#define TOE_RX_BD_RESERVED1_SHIFT 4
uint16_t size ;
#elif defined(__LITTLE_ENDIAN)
uint16_t size ;
uint16_t flags;
#define TOE_RX_BD_START (0x1<<0)
#define TOE_RX_BD_START_SHIFT 0
#define TOE_RX_BD_END (0x1<<1)
#define TOE_RX_BD_END_SHIFT 1
#define TOE_RX_BD_NO_PUSH (0x1<<2)
#define TOE_RX_BD_NO_PUSH_SHIFT 2
#define TOE_RX_BD_SPLIT (0x1<<3)
#define TOE_RX_BD_SPLIT_SHIFT 3
#define TOE_RX_BD_RESERVED1 (0xFFF<<4)
#define TOE_RX_BD_RESERVED1_SHIFT 4
#endif
uint32_t dbg_bytes_prod ;
};
struct toe_rx_completion_ramrod_data
{
#if defined(__BIG_ENDIAN)
uint16_t reserved0;
uint16_t hash_value ;
#elif defined(__LITTLE_ENDIAN)
uint16_t hash_value ;
uint16_t reserved0;
#endif
uint32_t reserved1;
};
struct toe_rx_cqe_ooo_params
{
uint32_t ooo_params;
#define TOE_RX_CQE_OOO_PARAMS_NBYTES (0xFFFFFF<<0)
#define TOE_RX_CQE_OOO_PARAMS_NBYTES_SHIFT 0
#define TOE_RX_CQE_OOO_PARAMS_ISLE_NUM (0xFF<<24)
#define TOE_RX_CQE_OOO_PARAMS_ISLE_NUM_SHIFT 24
};
struct toe_rx_cqe_in_order_params
{
uint32_t in_order_params;
#define TOE_RX_CQE_IN_ORDER_PARAMS_NBYTES (0xFFFFFFFF<<0)
#define TOE_RX_CQE_IN_ORDER_PARAMS_NBYTES_SHIFT 0
};
union toe_rx_cqe_data_union
{
struct toe_rx_cqe_ooo_params ooo_params ;
struct toe_rx_cqe_in_order_params in_order_params ;
uint32_t raw_data ;
};
struct toe_rx_cqe
{
uint32_t params1;
#define TOE_RX_CQE_CID (0xFFFFFF<<0)
#define TOE_RX_CQE_CID_SHIFT 0
#define TOE_RX_CQE_COMPLETION_OPCODE (0xFF<<24)
#define TOE_RX_CQE_COMPLETION_OPCODE_SHIFT 24
union toe_rx_cqe_data_union data ;
};
struct toe_rx_db_data
{
uint32_t rcv_win_right_edge ;
uint32_t bytes_prod ;
#if defined(__BIG_ENDIAN)
uint8_t reserved1 ;
uint8_t flags;
#define TOE_RX_DB_DATA_IGNORE_WND_UPDATES (0x1<<0)
#define TOE_RX_DB_DATA_IGNORE_WND_UPDATES_SHIFT 0
#define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF (0x1<<1)
#define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF_SHIFT 1
#define TOE_RX_DB_DATA_RESERVED0 (0x3F<<2)
#define TOE_RX_DB_DATA_RESERVED0_SHIFT 2
uint16_t bds_prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t bds_prod ;
uint8_t flags;
#define TOE_RX_DB_DATA_IGNORE_WND_UPDATES (0x1<<0)
#define TOE_RX_DB_DATA_IGNORE_WND_UPDATES_SHIFT 0
#define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF (0x1<<1)
#define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF_SHIFT 1
#define TOE_RX_DB_DATA_RESERVED0 (0x3F<<2)
#define TOE_RX_DB_DATA_RESERVED0_SHIFT 2
uint8_t reserved1 ;
#endif
uint32_t consumed_grq_bytes ;
};
struct toe_rx_grq_bd
{
uint32_t addr_lo ;
uint32_t addr_hi ;
};
union toe_spe_data
{
uint8_t protocol_data[8] ;
struct regpair_t phys_addr ;
struct toe_rx_completion_ramrod_data rx_completion ;
struct toe_init_ramrod_data toe_init ;
};
struct toe_spe
{
struct spe_hdr_t hdr ;
union toe_spe_data toe_data ;
};
enum toe_sq_opcode_type
{
CMP_OPCODE_TOE_GA=1,
CMP_OPCODE_TOE_GR=2,
CMP_OPCODE_TOE_GNI=3,
CMP_OPCODE_TOE_GAIR=4,
CMP_OPCODE_TOE_GAIL=5,
CMP_OPCODE_TOE_GRI=6,
CMP_OPCODE_TOE_GJ=7,
CMP_OPCODE_TOE_DGI=8,
CMP_OPCODE_TOE_CMP=9,
CMP_OPCODE_TOE_REL=10,
CMP_OPCODE_TOE_SKP=11,
CMP_OPCODE_TOE_URG=12,
CMP_OPCODE_TOE_RT_TO=13,
CMP_OPCODE_TOE_KA_TO=14,
CMP_OPCODE_TOE_MAX_RT=15,
CMP_OPCODE_TOE_DBT_RE=16,
CMP_OPCODE_TOE_SYN=17,
CMP_OPCODE_TOE_OPT_ERR=18,
CMP_OPCODE_TOE_FW2_TO=19,
CMP_OPCODE_TOE_2WY_CLS=20,
CMP_OPCODE_TOE_TX_CMP=21,
RAMROD_OPCODE_TOE_INIT=32,
RAMROD_OPCODE_TOE_RSS_UPDATE=33,
RAMROD_OPCODE_TOE_TERMINATE_RING=34,
CMP_OPCODE_TOE_RST_RCV=48,
CMP_OPCODE_TOE_FIN_RCV=49,
CMP_OPCODE_TOE_FIN_UPL=50,
CMP_OPCODE_TOE_SRC_ERR=51,
CMP_OPCODE_TOE_LCN_ERR=52,
RAMROD_OPCODE_TOE_INITIATE_OFFLOAD=80,
RAMROD_OPCODE_TOE_SEARCHER_DELETE=81,
RAMROD_OPCODE_TOE_TERMINATE=82,
RAMROD_OPCODE_TOE_QUERY=83,
RAMROD_OPCODE_TOE_RESET_SEND=84,
RAMROD_OPCODE_TOE_INVALIDATE=85,
RAMROD_OPCODE_TOE_EMPTY_RAMROD=86,
RAMROD_OPCODE_TOE_UPDATE=87,
MAX_TOE_SQ_OPCODE_TYPE};
struct xstorm_toe_stats_section
{
uint32_t tcp_out_segments;
uint32_t tcp_retransmitted_segments;
struct regpair_t ip_out_octets;
uint32_t ip_out_requests;
uint32_t reserved;
};
struct xstorm_toe_stats
{
struct xstorm_toe_stats_section statistics[2] ;
uint32_t reserved[2];
};
struct tstorm_toe_stats_section
{
uint32_t ip_in_receives;
uint32_t ip_in_delivers;
struct regpair_t ip_in_octets;
uint32_t tcp_in_errors ;
uint32_t ip_in_header_errors ;
uint32_t ip_in_discards ;
uint32_t ip_in_truncated_packets;
};
struct tstorm_toe_stats
{
struct tstorm_toe_stats_section statistics[2] ;
uint32_t reserved[2];
};
struct toe_stats_query
{
struct xstorm_toe_stats xstorm_toe ;
struct tstorm_toe_stats tstorm_toe ;
struct cstorm_toe_stats cstorm_toe ;
};
struct toe_tx_bd
{
uint32_t addr_lo ;
uint32_t addr_hi ;
#if defined(__BIG_ENDIAN)
uint16_t flags;
#define TOE_TX_BD_PUSH (0x1<<0)
#define TOE_TX_BD_PUSH_SHIFT 0
#define TOE_TX_BD_NOTIFY (0x1<<1)
#define TOE_TX_BD_NOTIFY_SHIFT 1
#define TOE_TX_BD_FIN (0x1<<2)
#define TOE_TX_BD_FIN_SHIFT 2
#define TOE_TX_BD_LARGE_IO (0x1<<3)
#define TOE_TX_BD_LARGE_IO_SHIFT 3
#define TOE_TX_BD_RESERVED1 (0xFFF<<4)
#define TOE_TX_BD_RESERVED1_SHIFT 4
uint16_t size ;
#elif defined(__LITTLE_ENDIAN)
uint16_t size ;
uint16_t flags;
#define TOE_TX_BD_PUSH (0x1<<0)
#define TOE_TX_BD_PUSH_SHIFT 0
#define TOE_TX_BD_NOTIFY (0x1<<1)
#define TOE_TX_BD_NOTIFY_SHIFT 1
#define TOE_TX_BD_FIN (0x1<<2)
#define TOE_TX_BD_FIN_SHIFT 2
#define TOE_TX_BD_LARGE_IO (0x1<<3)
#define TOE_TX_BD_LARGE_IO_SHIFT 3
#define TOE_TX_BD_RESERVED1 (0xFFF<<4)
#define TOE_TX_BD_RESERVED1_SHIFT 4
#endif
uint32_t nextBdStartSeq;
};
struct toe_tx_cqe
{
uint32_t params;
#define TOE_TX_CQE_CID (0xFFFFFF<<0)
#define TOE_TX_CQE_CID_SHIFT 0
#define TOE_TX_CQE_COMPLETION_OPCODE (0xFF<<24)
#define TOE_TX_CQE_COMPLETION_OPCODE_SHIFT 24
uint32_t len ;
};
struct toe_tx_db_data
{
uint32_t bytes_prod_seq ;
#if defined(__BIG_ENDIAN)
uint16_t flags;
#define TOE_TX_DB_DATA_FIN (0x1<<0)
#define TOE_TX_DB_DATA_FIN_SHIFT 0
#define TOE_TX_DB_DATA_FLUSH (0x1<<1)
#define TOE_TX_DB_DATA_FLUSH_SHIFT 1
#define TOE_TX_DB_DATA_RESERVE (0x3FFF<<2)
#define TOE_TX_DB_DATA_RESERVE_SHIFT 2
uint16_t bds_prod ;
#elif defined(__LITTLE_ENDIAN)
uint16_t bds_prod ;
uint16_t flags;
#define TOE_TX_DB_DATA_FIN (0x1<<0)
#define TOE_TX_DB_DATA_FIN_SHIFT 0
#define TOE_TX_DB_DATA_FLUSH (0x1<<1)
#define TOE_TX_DB_DATA_FLUSH_SHIFT 1
#define TOE_TX_DB_DATA_RESERVE (0x3FFF<<2)
#define TOE_TX_DB_DATA_RESERVE_SHIFT 2
#endif
};
struct toe_update_ramrod_cached_params
{
uint16_t changed_fields;
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_DEST_ADDR_CHANGED (0x1<<0)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_DEST_ADDR_CHANGED_SHIFT 0
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_MSS_CHANGED (0x1<<1)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_MSS_CHANGED_SHIFT 1
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_TIMEOUT_CHANGED (0x1<<2)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_TIMEOUT_CHANGED_SHIFT 2
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_INTERVAL_CHANGED (0x1<<3)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_INTERVAL_CHANGED_SHIFT 3
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_MAX_RT_CHANGED (0x1<<4)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_MAX_RT_CHANGED_SHIFT 4
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_RCV_INDICATION_SIZE_CHANGED (0x1<<5)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_RCV_INDICATION_SIZE_CHANGED_SHIFT 5
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_FLOW_LABEL_CHANGED (0x1<<6)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_FLOW_LABEL_CHANGED_SHIFT 6
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_KEEPALIVE_CHANGED (0x1<<7)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_KEEPALIVE_CHANGED_SHIFT 7
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_NAGLE_CHANGED (0x1<<8)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_NAGLE_CHANGED_SHIFT 8
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_TTL_CHANGED (0x1<<9)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_TTL_CHANGED_SHIFT 9
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_HOP_LIMIT_CHANGED (0x1<<10)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_HOP_LIMIT_CHANGED_SHIFT 10
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_TOS_CHANGED (0x1<<11)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_TOS_CHANGED_SHIFT 11
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_TRAFFIC_CLASS_CHANGED (0x1<<12)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_TRAFFIC_CLASS_CHANGED_SHIFT 12
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_MAX_PROBE_COUNT_CHANGED (0x1<<13)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_MAX_PROBE_COUNT_CHANGED_SHIFT 13
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_USER_PRIORITY_CHANGED (0x1<<14)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_USER_PRIORITY_CHANGED_SHIFT 14
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_INITIAL_RCV_WND_CHANGED (0x1<<15)
#define TOE_UPDATE_RAMROD_CACHED_PARAMS_INITIAL_RCV_WND_CHANGED_SHIFT 15
uint8_t ka_restart ;
uint8_t retransmit_restart ;
uint8_t dest_addr[6];
uint16_t mss;
uint32_t ka_timeout;
uint32_t ka_interval;
uint32_t max_rt;
uint32_t flow_label ;
uint16_t rcv_indication_size;
uint8_t enable_keepalive ;
uint8_t enable_nagle ;
uint8_t ttl;
uint8_t hop_limit;
uint8_t tos;
uint8_t traffic_class;
uint8_t ka_max_probe_count;
uint8_t user_priority ;
uint16_t reserved2;
uint32_t initial_rcv_wnd;
uint32_t reserved1;
};
struct ustorm_toe_rx_pause_data_e1h
{
#if defined(__BIG_ENDIAN)
uint16_t grq_thr_low ;
uint16_t cq_thr_low ;
#elif defined(__LITTLE_ENDIAN)
uint16_t cq_thr_low ;
uint16_t grq_thr_low ;
#endif
#if defined(__BIG_ENDIAN)
uint16_t grq_thr_high ;
uint16_t cq_thr_high ;
#elif defined(__LITTLE_ENDIAN)
uint16_t cq_thr_high ;
uint16_t grq_thr_high ;
#endif
};
#endif
