CoCalc -- ccu

GitHub Repository: freebsd/freebsd-src
Path: blob/main/sys/dev/clk/allwinner/ccu_h6.c
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/*-
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 * SPDX-License-Identifier: BSD-2-Clause
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 *
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 * Copyright (c) 2019 Emmanuel Vadot <[email protected]>
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * 1. Redistributions of source code must retain the above copyright
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 *    notice, this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright
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 *    notice, this list of conditions and the following disclaimer in the
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 *    documentation and/or other materials provided with the distribution.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/clk/clk_div.h>
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#include <dev/clk/clk_fixed.h>
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#include <dev/clk/clk_mux.h>
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#include <dev/clk/allwinner/aw_ccung.h>
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#include <dt-bindings/clock/sun50i-h6-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-ccu.h>
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/* Non-exported clocks */
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#define	CLK_OSC_12M		0
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#define	CLK_PLL_CPUX		1
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#define	CLK_PLL_DDR0		2
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#define	CLK_PLL_PERIPH0_2X	4
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#define	CLK_PLL_PERIPH0_4X	5
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#define	CLK_PLL_PERIPH1		6
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#define	CLK_PLL_PERIPH1_2X	7
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#define	CLK_PLL_PERIPH1_4X	8
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#define	CLK_PLL_GPU		9
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#define	CLK_PLL_VIDEO0		10
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#define	CLK_PLL_VIDEO0_4X	11
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#define	CLK_PLL_VIDEO1		12
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#define	CLK_PLL_VIDEO1_4X	13
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#define	CLK_PLL_VE		14
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#define	CLK_PLL_DE		14
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#define	CLK_PLL_HSIC		16
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#define	CLK_PSI_AHB1_AHB2	24
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#define	CLK_AHB3		25
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#define	CLK_APB2		27
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static struct aw_ccung_reset h6_ccu_resets[] = {
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	/* PSI_BGR_REG */
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	CCU_RESET(RST_BUS_PSI, 0x79c, 16)
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	/* SMHC_BGR_REG */
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	CCU_RESET(RST_BUS_MMC0, 0x84c, 16)
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	CCU_RESET(RST_BUS_MMC1, 0x84c, 17)
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	CCU_RESET(RST_BUS_MMC2, 0x84c, 18)
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	/* UART_BGR_REG */
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	CCU_RESET(RST_BUS_UART0, 0x90c, 16)
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	CCU_RESET(RST_BUS_UART1, 0x90c, 17)
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	CCU_RESET(RST_BUS_UART2, 0x90c, 18)
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	CCU_RESET(RST_BUS_UART3, 0x90c, 19)
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	/* TWI_BGR_REG */
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	CCU_RESET(RST_BUS_I2C0, 0x91c, 16)
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	CCU_RESET(RST_BUS_I2C1, 0x91c, 17)
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	CCU_RESET(RST_BUS_I2C2, 0x91c, 18)
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	CCU_RESET(RST_BUS_I2C3, 0x91c, 19)
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	/* EMAC_BGR_REG */
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	CCU_RESET(RST_BUS_EMAC, 0x97c, 16)
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	/* USB0_CLK_REG */
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	CCU_RESET(RST_USB_PHY0, 0xa70, 30)
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	/* USB1_CLK_REG */
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	CCU_RESET(RST_USB_PHY1, 0xa74, 30)
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	/* USB3_CLK_REG */
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	CCU_RESET(RST_USB_HSIC, 0xa7c, 28)
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	CCU_RESET(RST_USB_PHY3, 0xa7c, 30)
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	/* USB_BGR_REG */
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	CCU_RESET(RST_BUS_OHCI0, 0xa8c, 16)
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	CCU_RESET(RST_BUS_OHCI3, 0xa8c, 19)
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	CCU_RESET(RST_BUS_EHCI0, 0xa8c, 20)
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	CCU_RESET(RST_BUS_XHCI, 0xa8c, 21)
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	CCU_RESET(RST_BUS_EHCI3, 0xa8c, 23)
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	CCU_RESET(RST_BUS_OTG, 0xa8c, 24)
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};
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static struct aw_ccung_gate h6_ccu_gates[] = {
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	/* PSI_BGR_REG */
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	CCU_GATE(CLK_BUS_PSI, "bus-psi", "psi_ahb1_ahb2", 0x79c, 0)
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	/* SMHC_BGR_REG */
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	CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb3", 0x84c, 0)
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	CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb3", 0x84c, 1)
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	CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb3", 0x84c, 2)
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	/* UART_BGR_REG Enabling the gate enable weir behavior ... */
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	/* CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x90c, 0) */
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	/* CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x90c, 1) */
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	/* CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x90c, 2) */
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	/* CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x90c, 3) */
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	/* TWI_BGR_REG */
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	CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x91c, 0)
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	CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x91c, 1)
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	CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x91c, 2)
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	CCU_GATE(CLK_BUS_I2C3, "bus-i2c3", "apb2", 0x91c, 3)
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	/* EMAC_BGR_REG */
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	CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb3", 0x97c, 0)
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	/* USB0_CLK_REG */
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	CCU_GATE(CLK_USB_PHY0, "usb-phy0", "ahb3", 0xa70, 29)
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	CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "ahb3", 0xa70, 31)
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	/* USB1_CLK_REG */
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	CCU_GATE(CLK_USB_PHY1, "usb-phy1", "ahb3", 0xa74, 29)
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	/* USB3_CLK_REG */
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	CCU_GATE(CLK_USB_HSIC, "usb-hsic", "ahb3", 0xa7c, 26)
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	CCU_GATE(CLK_USB_HSIC_12M, "usb-hsic-12M", "ahb3", 0xa7c, 27)
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	CCU_GATE(CLK_USB_PHY3, "usb-phy3", "ahb3", 0xa7c, 29)
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	CCU_GATE(CLK_USB_OHCI3, "usb-ohci3", "ahb3", 0xa7c, 31)
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	/* USB_BGR_REG */
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	CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb3", 0xa8c, 0)
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	CCU_GATE(CLK_BUS_OHCI3, "bus-ohci3", "ahb3", 0xa8c, 3)
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	CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb3", 0xa8c, 4)
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	CCU_GATE(CLK_BUS_XHCI, "bus-xhci", "ahb3", 0xa8c, 5)
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	CCU_GATE(CLK_BUS_EHCI3, "bus-ehci3", "ahb3", 0xa8c, 7)
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	CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb3", 0xa8c, 8)
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};
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static const char *osc12m_parents[] = {"osc24M"};
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FIXED_CLK(osc12m_clk,
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    CLK_OSC_12M,			/* id */
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    "osc12M",				/* name */
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    osc12m_parents,			/* parent */
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    0,					/* freq */
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    1,					/* mult */
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    2,					/* div */
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    0);					/* flags */
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static const char *pll_cpux_parents[] = {"osc24M"};
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NP_CLK(pll_cpux_clk,
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    CLK_PLL_CPUX,				/* id */
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    "pll_cpux", pll_cpux_parents,		/* name, parents */
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    0x00,					/* offset */
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    8, 7, 0, 0,					/* n factor */
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    0, 2, 0, 0,					/* p factor */
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    31,						/* gate */
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    28, 1000,					/* lock */
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    AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);		/* flags */
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static const char *pll_ddr0_parents[] = {"osc24M"};
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NMM_CLK(pll_ddr0_clk,
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    CLK_PLL_DDR0,				/* id */
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    "pll_ddr0", pll_ddr0_parents,		/* name, parents */
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    0x10,					/* offset */
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    8, 7, 0, 0,					/* n factor */
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    0, 1, 0, 0,					/* m0 factor */
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    1, 1, 0, 0,					/* m1 factor */
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    31,						/* gate */
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    28, 1000,					/* lock */
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    AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);		/* flags */
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static const char *pll_peri0_4x_parents[] = {"osc24M"};
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NMM_CLK(pll_peri0_4x_clk,
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    CLK_PLL_PERIPH0_4X,				/* id */
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    "pll_periph0_4x", pll_peri0_4x_parents,	/* name, parents */
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    0x20,					/* offset */
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    8, 7, 0, 0,					/* n factor */
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    0, 1, 0, 0,					/* m0 factor */
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    1, 1, 0, 0,					/* m1 factor */
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    31,						/* gate */
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    28, 1000,					/* lock */
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    AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);		/* flags */
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static const char *pll_peri0_2x_parents[] = {"pll_periph0_4x"};
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FIXED_CLK(pll_peri0_2x_clk,
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    CLK_PLL_PERIPH0_2X,			/* id */
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    "pll_periph0_2x",			/* name */
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    pll_peri0_2x_parents,		/* parent */
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    0,					/* freq */
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    1,					/* mult */
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    2,					/* div */
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    0);					/* flags */
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static const char *pll_peri0_parents[] = {"pll_periph0_4x"};
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FIXED_CLK(pll_peri0_clk,
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    CLK_PLL_PERIPH0,			/* id */
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    "pll_periph0",			/* name */
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    pll_peri0_parents,			/* parent */
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    0,					/* freq */
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    1,					/* mult */
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    4,					/* div */
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    0);					/* flags */
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static const char *pll_peri1_4x_parents[] = {"osc24M"};
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NMM_CLK(pll_peri1_4x_clk,
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    CLK_PLL_PERIPH1_4X,				/* id */
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    "pll_periph1_4x", pll_peri1_4x_parents,	/* name, parents */
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    0x28,					/* offset */
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    8, 7, 0, 0,					/* n factor */
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    0, 1, 0, 0,					/* m0 factor */
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    1, 1, 0, 0,					/* m1 factor */
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    31,						/* gate */
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    28, 1000,					/* lock */
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    AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);		/* flags */
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static const char *pll_peri1_2x_parents[] = {"pll_periph1_4x"};
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FIXED_CLK(pll_peri1_2x_clk,
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    CLK_PLL_PERIPH1_2X,			/* id */
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    "pll_periph1_2x",			/* name */
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    pll_peri1_2x_parents,		/* parent */
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    0,					/* freq */
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    1,					/* mult */
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    2,					/* div */
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    0);					/* flags */
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static const char *pll_peri1_parents[] = {"pll_periph1_4x"};
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FIXED_CLK(pll_peri1_clk,
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    CLK_PLL_PERIPH1,			/* id */
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    "pll_periph1",			/* name */
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    pll_peri1_parents,			/* parent */
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    0,					/* freq */
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    1,					/* mult */
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    4,					/* div */
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    0);					/* flags */
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static const char *pll_gpu_parents[] = {"osc24M"};
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NMM_CLK(pll_gpu_clk,
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    CLK_PLL_GPU,				/* id */
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    "pll_gpu", pll_gpu_parents,			/* name, parents */
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    0x30,					/* offset */
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    8, 7, 0, 0,					/* n factor */
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    0, 1, 0, 0,					/* m0 factor */
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    1, 1, 0, 0,					/* m1 factor */
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    31,						/* gate */
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    28, 1000,					/* lock */
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    AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);		/* flags */
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static const char *pll_video0_4x_parents[] = {"osc24M"};
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NMM_CLK(pll_video0_4x_clk,
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    CLK_PLL_VIDEO0_4X,				/* id */
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    "pll_video0_4x", pll_video0_4x_parents,	/* name, parents */
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    0x40,					/* offset */
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    8, 7, 0, 0,					/* n factor */
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    0, 1, 0, 0,					/* m0 factor */
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    1, 1, 0, 0,					/* m1 factor */
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    31,						/* gate */
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    28, 1000,					/* lock */
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    AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);		/* flags */
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static const char *pll_video0_parents[] = {"pll_video0_4x"};
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FIXED_CLK(pll_video0_clk,
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    CLK_PLL_VIDEO0,			/* id */
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    "pll_video0",			/* name */
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    pll_video0_parents,			/* parent */
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    0,					/* freq */
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    1,					/* mult */
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    4,					/* div */
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    0);					/* flags */
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static const char *pll_video1_4x_parents[] = {"osc24M"};
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NMM_CLK(pll_video1_4x_clk,
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    CLK_PLL_VIDEO1_4X,				/* id */
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    "pll_video1_4x", pll_video1_4x_parents,	/* name, parents */
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    0x48,					/* offset */
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    8, 7, 0, 0,					/* n factor */
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    0, 1, 0, 0,					/* m0 factor */
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    1, 1, 0, 0,					/* m1 factor */
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    31,						/* gate */
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    28, 1000,					/* lock */
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    AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);		/* flags */
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static const char *pll_video1_parents[] = {"pll_video1_4x"};
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FIXED_CLK(pll_video1_clk,
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    CLK_PLL_VIDEO1,			/* id */
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    "pll_video1",			/* name */
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    pll_video1_parents,			/* parent */
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    0,					/* freq */
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    1,					/* mult */
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    4,					/* div */
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    0);					/* flags */
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static const char *pll_ve_parents[] = {"osc24M"};
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NMM_CLK(pll_ve_clk,
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    CLK_PLL_VE,					/* id */
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    "pll_ve", pll_ve_parents,			/* name, parents */
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    0x58,					/* offset */
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    8, 7, 0, 0,					/* n factor */
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    0, 1, 0, 0,					/* m0 factor */
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    1, 1, 0, 0,					/* m1 factor */
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    31,						/* gate */
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    28, 1000,					/* lock */
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    AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);		/* flags */
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static const char *pll_de_parents[] = {"osc24M"};
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NMM_CLK(pll_de_clk,
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    CLK_PLL_DE,					/* id */
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    "pll_de", pll_de_parents,			/* name, parents */
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    0x60,					/* offset */
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    8, 7, 0, 0,					/* n factor */
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    0, 1, 0, 0,					/* m0 factor */
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    1, 1, 0, 0,					/* m1 factor */
328
    31,						/* gate */
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    28, 1000,					/* lock */
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    AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);		/* flags */
331

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static const char *pll_hsic_parents[] = {"osc24M"};
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NMM_CLK(pll_hsic_clk,
334
    CLK_PLL_HSIC,				/* id */
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    "pll_hsic", pll_hsic_parents,		/* name, parents */
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    0x70,					/* offset */
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    8, 7, 0, 0,					/* n factor */
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    0, 1, 0, 0,					/* m0 factor */
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    1, 1, 0, 0,					/* m1 factor */
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    31,						/* gate */
341
    28, 1000,					/* lock */
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    AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);		/* flags */
343

344
/* PLL_AUDIO missing */
345

346
/* CPUX_AXI missing */
347

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static const char *psi_ahb1_ahb2_parents[] = {"osc24M", "osc32k", "iosc", "pll_periph0"};
349
NM_CLK(psi_ahb1_ahb2_clk,
350
    CLK_PSI_AHB1_AHB2, "psi_ahb1_ahb2", psi_ahb1_ahb2_parents,		/* id, name, parents */
351
    0x510,					/* offset */
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    8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,	/* n factor */
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    0, 2, 0, 0,					/* m factor */
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    24, 2,					/* mux */
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    0,						/* gate */
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    AW_CLK_HAS_MUX | AW_CLK_REPARENT);		/* flags */
357

358
static const char *ahb3_parents[] = {"osc24M", "osc32k", "psi_ahb1_ahb2", "pll_periph0"};
359
NM_CLK(ahb3_clk,
360
    CLK_AHB3, "ahb3", ahb3_parents,		/* id, name, parents */
361
    0x51C,					/* offset */
362
    8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,	/* n factor */
363
    0, 2, 0, 0,					/* m factor */
364
    24, 2,					/* mux */
365
    0,						/* gate */
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    AW_CLK_HAS_MUX | AW_CLK_REPARENT);		/* flags */
367

368
static const char *apb1_parents[] = {"osc24M", "osc32k", "psi_ahb1_ahb2", "pll_periph0"};
369
NM_CLK(apb1_clk,
370
    CLK_APB1, "apb1", apb1_parents,		/* id, name, parents */
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    0x520,					/* offset */
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    8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,	/* n factor */
373
    0, 2, 0, 0,					/* m factor */
374
    24, 2,					/* mux */
375
    0,						/* gate */
376
    AW_CLK_HAS_MUX | AW_CLK_REPARENT);		/* flags */
377

378
static const char *apb2_parents[] = {"osc24M", "osc32k", "psi_ahb1_ahb2", "pll_periph0"};
379
NM_CLK(apb2_clk,
380
    CLK_APB2, "apb2", apb2_parents,		/* id, name, parents */
381
    0x524,					/* offset */
382
    8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,	/* n factor */
383
    0, 2, 0, 0,					/* m factor */
384
    24, 2,					/* mux */
385
    0,						/* gate */
386
    AW_CLK_HAS_MUX | AW_CLK_REPARENT);		/* flags */
387

388
/* Missing MBUS clock */
389

390
static const char *mod_parents[] = {"osc24M", "pll_periph0_2x", "pll_periph1_2x"};
391
NM_CLK(mmc0_clk,
392
    CLK_MMC0, "mmc0", mod_parents,		/* id, name, parents */
393
    0x830,					/* offset */
394
    8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,	/* n factor */
395
    0, 4, 0, 0,					/* m factor */
396
    24, 2,					/* mux */
397
    31,						/* gate */
398
    AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
399
    AW_CLK_REPARENT);				/* flags */
400

401
NM_CLK(mmc1_clk,
402
    CLK_MMC1, "mmc1", mod_parents,		/* id, name, parents */
403
    0x834,					/* offset */
404
    8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,	/* n factor */
405
    0, 4, 0, 0,					/* m factor */
406
    24, 2,					/* mux */
407
    31,						/* gate */
408
    AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
409
    AW_CLK_REPARENT);				/* flags */
410

411
NM_CLK(mmc2_clk,
412
    CLK_MMC2, "mmc2", mod_parents,		/* id, name, parents */
413
    0x838,					/* offset */
414
    8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,	/* n factor */
415
    0, 4, 0, 0,					/* m factor */
416
    24, 2,					/* mux */
417
    31,						/* gate */
418
    AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
419
    AW_CLK_REPARENT);				/* flags */
420

421
static struct aw_ccung_clk h6_ccu_clks[] = {
422
	{ .type = AW_CLK_NP, .clk.np = &pll_cpux_clk},
423
	{ .type = AW_CLK_NMM, .clk.nmm = &pll_ddr0_clk},
424
	{ .type = AW_CLK_NMM, .clk.nmm = &pll_peri0_4x_clk},
425
	{ .type = AW_CLK_NMM, .clk.nmm = &pll_peri1_4x_clk},
426
	{ .type = AW_CLK_NMM, .clk.nmm = &pll_gpu_clk},
427
	{ .type = AW_CLK_NMM, .clk.nmm = &pll_video0_4x_clk},
428
	{ .type = AW_CLK_NMM, .clk.nmm = &pll_video1_4x_clk},
429
	{ .type = AW_CLK_NMM, .clk.nmm = &pll_ve_clk},
430
	{ .type = AW_CLK_NMM, .clk.nmm = &pll_de_clk},
431
	{ .type = AW_CLK_NMM, .clk.nmm = &pll_hsic_clk},
432

433
	{ .type = AW_CLK_NM, .clk.nm = &psi_ahb1_ahb2_clk},
434
	{ .type = AW_CLK_NM, .clk.nm = &ahb3_clk},
435
	{ .type = AW_CLK_NM, .clk.nm = &apb1_clk},
436
	{ .type = AW_CLK_NM, .clk.nm = &apb2_clk},
437

438
	{ .type = AW_CLK_NM, .clk.nm = &mmc0_clk},
439
	{ .type = AW_CLK_NM, .clk.nm = &mmc1_clk},
440
	{ .type = AW_CLK_NM, .clk.nm = &mmc2_clk},
441

442
	{ .type = AW_CLK_FIXED, .clk.fixed = &osc12m_clk},
443
	{ .type = AW_CLK_FIXED, .clk.fixed = &pll_peri0_2x_clk},
444
	{ .type = AW_CLK_FIXED, .clk.fixed = &pll_peri0_clk},
445
	{ .type = AW_CLK_FIXED, .clk.fixed = &pll_peri1_2x_clk},
446
	{ .type = AW_CLK_FIXED, .clk.fixed = &pll_peri1_clk},
447
	{ .type = AW_CLK_FIXED, .clk.fixed = &pll_video0_clk},
448
	{ .type = AW_CLK_FIXED, .clk.fixed = &pll_video1_clk},
449
};
450

451
static int
452
ccu_h6_probe(device_t dev)
453
{
454

455
	if (!ofw_bus_status_okay(dev))
456
		return (ENXIO);
457

458
	if (!ofw_bus_is_compatible(dev, "allwinner,sun50i-h6-ccu"))
459
		return (ENXIO);
460

461
	device_set_desc(dev, "Allwinner H6 Clock Control Unit NG");
462
	return (BUS_PROBE_DEFAULT);
463
}
464

465
static int
466
ccu_h6_attach(device_t dev)
467
{
468
	struct aw_ccung_softc *sc;
469

470
	sc = device_get_softc(dev);
471

472
	sc->resets = h6_ccu_resets;
473
	sc->nresets = nitems(h6_ccu_resets);
474
	sc->gates = h6_ccu_gates;
475
	sc->ngates = nitems(h6_ccu_gates);
476
	sc->clks = h6_ccu_clks;
477
	sc->nclks = nitems(h6_ccu_clks);
478

479
	return (aw_ccung_attach(dev));
480
}
481

482
static device_method_t ccu_h6ng_methods[] = {
483
	/* Device interface */
484
	DEVMETHOD(device_probe,		ccu_h6_probe),
485
	DEVMETHOD(device_attach,	ccu_h6_attach),
486

487
	DEVMETHOD_END
488
};
489

490
DEFINE_CLASS_1(ccu_h6ng, ccu_h6ng_driver, ccu_h6ng_methods,
491
  sizeof(struct aw_ccung_softc), aw_ccung_driver);
492

493
EARLY_DRIVER_MODULE(ccu_h6ng, simplebus, ccu_h6ng_driver, 0, 0,
494
    BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
495

496
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